Microcontroller chip

Abstract

The invention provides a microcontroller chip, which is specifically characterized in that a micro-control bare chip and at least one flash memory bare chip are packaged in the same packaging body through an advanced packaging process, a first welding pad is additionally arranged on the micro-control bare chip, a second welding pad corresponding to the first welding pad is additionally arranged on the flash memory bare chip, and the first welding pad and the second welding pad are arranged on the same packaging body. The first welding pad and the second welding pad are connected together by the plurality of first interconnection lines, so that a multi-bit address line, a multi-bit data line and a multi-bit storage control line are led out between the microcontroller bare chip and the flash memory bare chip, and address signals, data signals and read-write-erase control signals between the microcontroller bare chip and the flash memory bare chip are transmitted in parallel; compared with a Sip FLASH scheme adopted by an existing microcontroller chip, the data read-write speed is high, and the data read-write effect similar to that of eFLASH can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chips, and in particular to a microcontroller chip. Background Art

[0002] MCU (Microcontroller Unit), also known as microcontroller, is a lightweight computing chip and the control core of many electronic devices. It has low power consumption and flexible programmable performance. MCU needs to apply corresponding memory to store code and data generated during the use of MCU.

[0003] FLASH is an essential component of MCU chips. It is not only used to store codes, but also to store data generated during use. The usual embedded flash memory (eFLASH) integrates the FLASH circuit and the MCU standard circuit on the same MCU die. The biggest disadvantage of embedded flash memory is that the FLASH circuit must use the same process as the MCU standard circuit. As MCU chips advance to higher processes, eFLASH also brings requirements to the process technology reserves of wafer foundries; the cost of embedded flash memory circuits with the same process and area is usually 30% higher than that of standard circuits. The 28nm / 22nm silicon lithography node will be the last cost-effective technology node for eFLASH, which is the main obstacle for the current MCU to move towards more advanced processes.

[0004] To solve the above problems, the existing solution is to use Sip (System In a Package) FLASH solution. Figure 1Specifically, the solution is to integrate the logic circuits required by the MCU chip 100, such as the storage control logic circuit 101a (also called the storage control module), the bus 101b and the random access memory 101c, and separately make them into an MCU bare chip 101, and then use the system-level packaging SiP method to seal the FLASH bare chip 102 and the MCU bare chip 101 together to form a sealed chip 100 as the MCU chip. As a result, the MCU code and data are stored in an independent and external FLASH relative to the MCU bare chip 101. On the bare chip 102, the FLASH bare chip 102 and the MCU bare chip 101 communicate through the SPI serial port. When the bus 101b receives a read access request, the storage control logic circuit 101a controls the data in the FLASH bare chip 102 to be copied to the random access memory 101c, and the MCU bare chip 101 reads the required data from the random access memory 101c. When the bus 101b receives a write access request, the storage control logic circuit 101a writes the data to be written into the random access memory 101c and the FLASH bare chip 102. This scheme has the advantages of high capacity, low memory price, fast time to market, etc., and there is no too large technical obstacle in manufacturing, but because the interface between the Sip FLASH bare chip 102 and the MCU bare chip 101 is a SPI serial port, even if it is an SPI serial port (such as an OSPI interface) with 8 IO data lines, the reading and writing of data in the FLASH also needs to be transmitted byte by byte, so the code / data reading speed is slow. In addition, the scheme also needs to set a matching random access memory 101c, which increases the area of ​​the MCU bare chip 101. Summary of the invention

[0005] The object of the present invention is to provide a microcontroller chip, which can improve the configuration flexibility of the memory chip and greatly improve the data reading and writing speed of the memory.

[0006] To achieve the above object, the present invention provides a microcontroller chip, which includes:

[0007] A microcontroller die, wherein a storage control logic circuit is integrated inside the microcontroller die and a plurality of first pads are provided on a first external side thereof;

[0008] At least one flash memory die, wherein a storage array is integrated inside the flash memory die and a plurality of second pads are disposed on a second side of the outside;

[0009] A plurality of first interconnection lines connect the plurality of first bonding pads and the plurality of second bonding pads in a one-to-one correspondence to form a multi-bit address line, a multi-bit data line and a multi-bit storage control signal line.

[0010] As a result, on the one hand, the address signals, data signals and read-write-erase control signals between the MCU die and the FLASH die can be directly transmitted in parallel point-to-point without protocol conversion. Compared with the Sip FLASH solution adopted by the existing MCU, the data programming and reading speeds are fast. On the other hand, the data reading and writing effect between the MCU die and its external FLASH die can achieve a data reading and writing effect similar to that of eFLASH (i.e. embedded flash memory, which integrates FLASH circuits and MCU storage control logic circuits on a single die), and there is no need to integrate Flash circuits inside the MCU die. Therefore, compared with eFLASH, it can save chip area and reduce the difficulty of manufacturing process.

[0011] In addition, for microcontroller chips using traditional eFLASH, if the specifications of the flash memory circuit need to be changed, the MCU chip manufacturer needs to tape out different versions of the MCU bare chip; and in order to not modify the layout and wiring of other standard circuits when the MCU bare chip version is modified, the MCU bare chip usually needs to reserve an area according to the maximum capacity of the eFLASH circuit during layout and wiring, resulting in a certain degree of waste of chip area. However, if the microcontroller chip of an embodiment of the present invention needs to change the flash capacity, the FLASH bare chip is directly replaced and the MCU bare chip does not need to be re-taped, shortening the development cycle of the microcontroller chip; in addition, it is not necessary to reserve an area according to the maximum capacity of the eFLASH, saving the overall area of ​​the microcontroller chip.

[0012] Optionally, the microcontroller die and the flash memory die are arranged side by side, the first pad is arranged on the first side adjacent to the microcontroller die and the flash memory die, and the second pad is arranged on the second side adjacent to the flash memory die and the microcontroller die. This arrangement method of distributing the first pad and the second pad adjacent to each other on the same side is conducive to reducing the design difficulty of the first interconnection line, shortening the length of the first interconnection line, and improving the line reliability and signal transmission speed.

[0013] Optionally, the top surface of the microcontroller die and the top surface of the flash die together form a fan-out surface of the intermediate package body in the package body. Fan-out expansion is achieved, and then after fan-out expansion, the chip packaging is completed directly through advanced packaging technology without the need for lead frames and packaging substrates, and the corresponding chip packaging shape is produced, so that the performance is better, the product size is smaller, and the performance of thermal simulation and the like is also better.

[0014] Optionally, the package body further comprises a rewiring layer formed on the fan-out surface, and a portion of the rewiring in the rewiring layer is rewired as the first interconnection line. Thus, the connection between the first pad and the second pad is realized inside the microcontroller chip through rewiring, without solder joints, with high reliability, and the rewiring process is conducive to optimizing the arrangement of the first pad and the second pad, reducing the cross points of the package, and in extreme cases, the risk of cross-wire bonding can be completely eliminated.

[0015] Optionally, at least one of the microcontroller die and the flash memory die is further provided with a plurality of third pads, and another corresponding portion of the rewiring layer is rewired as a second interconnection line electrically connected to the third pad, and a portion of the top surface of the second interconnection line is exposed to the outside and forms an external contact pad. Thus, the manufacture of electrical structures such as the first interconnection line, the second interconnection line, and the external contact pad required by the MCU chip is achieved through the rewiring process, which simplifies the process, reduces costs, avoids solder joints, and has high reliability. Moreover, the rewiring process is conducive to the arrangement optimization of the first pad, the second pad, the third pad, and the external contact pad, reduces the cross points of the package, and can completely eliminate the risk of cross-wire bonding in extreme cases.

[0016] Optionally, only one layer of redistribution wiring is formed in the redistribution wiring layer, a part of the layer of redistribution wiring is used as the first interconnection line, and another part of the layer of redistribution wiring is used as the second interconnection line. Thus, the manufacturing of electrical structures such as the first interconnection line and the second interconnection line can be realized by only one layer of redistribution wiring, which simplifies the process and structure, reduces the cost, avoids solder joints, has high reliability, better performance, and smaller product size.

[0017] Optionally, the rewiring layer is formed with a first layer of rewiring and a second layer of rewiring formed from bottom to top on the fan-out surface, a part of the first layer of rewiring is used as the first interconnection line, another part of the first layer of rewiring and a part of the second layer of rewiring are used as the second interconnection line to electrically connect the third pad. Among them, the rewiring process is conducive to the arrangement optimization of the first pad, the second pad and the third pad, reducing the cross points of the wire bonding of the package, and in extreme cases, the risk of cross-wire bonding can be completely eliminated. And the interconnection lines connected to each pad are all rewiring of the advanced packaging process, not the bonding wire of the ordinary package, without solder joints, high reliability, and can save time and cost. Optionally, solder balls are planted on the external contact pad. Therefore, after the fan-out expansion is realized, there is no need to set the packaging substrate at the bottom, and the rewiring layer is directly formed on the fan-out surface through the advanced packaging process and the solder balls are planted on the external contact pads, so as to produce the same appearance as the BGA / WLCSP packaged chip, with better performance and smaller product size.

[0018] Optionally, the top surface of the external contact pad forms a corresponding conductive pad, each of which is distributed around the periphery of the package body, and the top surface or side surface of each of the conductive pads is exposed to the outside by the package body. Therefore, after the fan-out expansion is realized, there is no need for a lead frame, and a redistribution layer is directly formed on the fan-out surface through advanced packaging technology and a conductive pad is formed on the external contact pad, so as to produce the same appearance as QFN packaged chips, with better performance, smaller product size, and better performance such as thermal simulation.

[0019] Optionally, the areas of the first pad and the second pad are both smaller than the area of ​​the third pad, thereby making the areas of the first pad and the second pad very small and avoiding the increase of additional chip area as much as possible.

[0020] Optionally, the area and size of the first pad and the second pad are both the minimum specifications allowed by the first interconnection line connection process, thereby minimizing the area of ​​the first pad and the second pad in terms of process, thereby avoiding the increase of additional chip area to the greatest extent.

[0021] Optionally, the package body further has a semiconductor substrate, the microcontroller die and the flash memory die are both installed in the grooves of the semiconductor substrate, and the microcontroller die, the flash memory die and the top surface of the semiconductor substrate together constitute the fan-out surface, wherein the microcontroller die and the flash memory die are both bonded to the bottom of the same groove or different grooves of the semiconductor substrate through an adhesive layer, and the gaps in each of the grooves after the microcontroller die and the flash memory die are installed are filled with dielectric material.

[0022] When the number of first pads on the MCU die is sufficient, the number and capacity of the FLASH die that can be matched with it and the number of second pads it has are all variable, so the design flexibility of the MCU chip is high, the development cycle is short, and the efficiency is high. Optionally, there are two flash memory die, one of which is used to support the online operation of the microcontroller chip, and the other flash memory die is used to support the upgrade of the microcontroller chip.

[0023] Optionally, the number of the first interconnection lines serving as the multi-bit address lines is (A+1), and the maximum physical addressing space of the corresponding storage array is [0,2 A+1 -1].

[0024] Optionally, the first interconnecting line serving as the multi-bit storage control signal line is used to transmit the control signal generated by the storage control logic circuit in response to the read, write and erase instructions; the number of the first interconnecting lines serving as the multi-bit data lines is (D+1), corresponding to the read and write data bit width of the storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0026] Figure 1 This is a system architecture diagram of the MCU chip using the Sip FLASH solution.

[0027] Figure 2 Schematic diagram of the system architecture of a microcontroller (MCU) chip according to the first embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram of an exemplary cross-sectional structure of a microcontroller (MCU) chip according to the first embodiment of the present invention after undergoing a fan-out packaging process.

[0029] Figure 4 yes Figure 3 The cross-sectional structure diagram of the microcontroller (MCU) chip shown in FIG. 1 is a schematic diagram of the cross-sectional structure of the microcontroller (MCU) chip after the QFN packaging process.

[0030] Figure 5 yes Figure 3 The schematic diagram of the top view of the microcontroller (MCU) chip after the QFN packaging process is shown.

[0031] Figure 6 yes Figure 3 The cross-sectional structure diagram of the microcontroller (MCU) chip shown is after the BGA / WLCSP packaging process.

[0032] Figure 7 yes Figure 3 The schematic diagram of the top view of the microcontroller (MCU) chip after the BGA / WLCSP packaging process is shown.

[0033] Figure 8 This is another exemplary structural diagram of the microcontroller (MCU) chip of the first embodiment of the present invention after undergoing the BGA / WLCSP packaging process.

[0034] Figures 9 to 11 It is a schematic cross-sectional structure diagram of the microcontroller (MCU) chip of the first embodiment of the present invention after undergoing other advanced packaging processes.

[0035] Fig.12It is a schematic diagram of the timing of data transmission between a microcontroller die and a flash memory die in a microcontroller (MCU) chip according to the first embodiment of the present invention.

[0036] Fig.13 Schematic diagram of the system architecture of a microcontroller (MCU) chip according to the second embodiment of the present invention.

[0037] Fig.14 yes Fig.13 Schematic diagram of the top view of the microcontroller (MCU) chip shown.

[0038] The reference numerals in the accompanying drawings are as follows:

[0039] 100-MCU chip; 101-MCU bare chip; 101b-bus; 101c-random access memory; 102-FLASH bare chip; 200-semiconductor substrate; 200a-groove; 201-microcontroller bare chip; 101a, 201a-storage control logic circuit; 2011-first pad; 2012, 2012A, 2022-third pad; 202, 202a, 202b-flash memory bare chip; 2021-second pad; 203-first interconnection line; 204, 2041-second interconnection line; 204a-external contact pad; 205-adhesive layer; 206-dielectric material; 207-first dielectric layer; 208-solder paste; 209-conductive pad; 210-second dielectric layer; 211-solder ball; DATA, DATA a ,DATA b -Data line; RWCTL, RWCTL a 、RWCTL b -Storage control signal line; ADDR, ADDR a 、ADDR b - Address lines. DETAILED DESCRIPTION

[0040] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] First embodiment

[0043] Please refer to Figures 2 to 7 The present embodiment provides a microcontroller chip (i.e., MCU chip), which includes a microcontroller die (i.e., MCU die) 201, a flash memory die (i.e., FLASH die) 202, and a plurality of first interconnection lines 203 packaged in the same package body through an advanced packaging process.

[0044] The microcontroller die 201 and the flash memory die 202 are two independent dies, which can be manufactured using different integrated circuit manufacturing processes. Since the cost of flash memory circuits with the same process and the same area is usually 30% higher than that of standard circuits, in one embodiment, the flash memory die 202 uses a process with a larger critical dimension (CD) than the microcontroller die 201, which helps to reduce costs.

[0045] The microcontroller die 201 may be integrated with a storage control logic circuit 201a and logic circuits with other functions. In the present embodiment, the microcontroller die 201 includes a plurality of first pads 2011 in addition to the third pads (PAD) 2012 required by the traditional microcontroller die 201 (for example, an I / O PAD used as an input / output interface of the MCU chip, a clock PAD used to implement clock signal transmission of the MCU chip, or a power PAD used to connect an external power supply and provide power supply voltage to the MCU chip).

[0046] The flash die 202 may be integrated with a storage array (not shown), which can read, write and erase data under the control of the storage control logic circuit 201a, and is used to store the codes required for the MCU chip upgrade and operation and the data generated during the use of the MCU chip. The flash die 202 is also additionally provided with a plurality of second pads 2021, which are arranged corresponding to some or all of the first pads 2011 in the microcontroller die 201.

[0047] In some examples of this embodiment, please refer to Figure 8 In addition to the second pad 2021, the flash die 202 may also need an external third pad 2022. For example, the flash die 202 has a third pad 2022 for external power or ground, so that the external power supplies power to the flash die 202 or the flash die 202 is connected to the external ground. For another example, if the flash die 202 is required to be used as a SIP FLASH, the third pad 2022 used as a FLASH general interface may be provided. For other examples, please refer to Figures 3 to 7 If the flash memory die 202 is powered by the microcontroller die 201 , the flash memory die 202 does not need to be provided with an external third pad 2022 .

[0048] In this embodiment, a plurality of first interconnection lines 203 connect a plurality of first pads 2011 on the microcontroller die 201 and a plurality of second pads 2021 on the flash die 202 in a one-to-one correspondence, thereby forming an A+1-bit address line ADDR[A:0], a D+1-bit data line DATA[D:0], and an x+1-bit storage control signal line RWCTL[x:0]. Wherein, A, D, and x are all integers greater than 1.

[0049] It should be understood that the microcontroller chip of this embodiment is actually an MCU system architecture in which a microcontroller (MCU) die is externally mounted with a flash memory (FLASH) die, so the number of first pads 2011 added to the microcontroller die 201 can be equal to or greater than the number of second pads 2021 added to the flash memory die 202. The situation in which the number of first pads 2011 added to the microcontroller die 201 is equal to the number of second pads 2021 added to the flash memory die 202 is applicable to the personalized customization scenario of the microcontroller chip. The case where the number of first pads 2011 added to the microcontroller die 201 is greater than the number of second pads 2021 added to the flash memory die 202 is more widely applicable than the former, especially when the number of first pads 2011 added to the microcontroller die 201 reaches the maximum supported number, it can allow the use of flash memory die 202 of various specifications, the capacities of these flash memory die 202 can be different, and the number of second pads 2021 can be less than or equal to the maximum supported number of first pads 2011, thereby making the microcontroller design more flexible, with a shorter development cycle and higher efficiency.

[0050] It is worth noting that for a microcontroller chip using traditional eFLASH, if the specification (e.g., capacity) of the flash memory circuit needs to be changed, the MCU chip manufacturer needs to tape out different versions of the MCU bare chip; and in order to not modify the layout and wiring of other standard circuits of the MCU when the MCU bare chip version is modified, the MCU bare chip usually needs to reserve an area according to the maximum capacity eFLASH circuit during layout and wiring, resulting in a certain degree of waste of chip area. However, if the microcontroller chip of an embodiment of the present invention needs to change the FLASH capacity, the flash memory bare chip 202 is directly replaced and the microcontroller bare chip 201 does not need to be re-taped, shortening the development cycle of the microcontroller chip; in addition, it is not necessary to reserve an area according to the maximum capacity eFLASH, saving the overall area of ​​the microcontroller chip.

[0051] It should also be understood that the microcontroller die 201 and the flash memory die 202 of the present embodiment can be packaged in the same package by any suitable advanced packaging process, and the advanced packaging process can form the required plurality of first interconnection lines 203 .

[0052] As an example, see Figures 3 to 5 The microcontroller die 201 and the flash memory die 202 are packaged in the same package body through the Fan-out Wafer Level Packaging (FO-WLP) process and the Quad Flat No-leads Package (QFN) packaging process.

[0053] Exemplarily, the fan-out wafer level packaging (FO-WLP) process includes:

[0054] First, a semiconductor substrate 200 is provided. The semiconductor substrate 200 may be any suitable semiconductor material in the art. For example, the semiconductor substrate 200 is a silicon substrate, or may be other compound semiconductor materials.

[0055] Then, a groove 200a is formed in the semiconductor substrate 200 by photolithography and etching processes;

[0056] Afterwards, the microcontroller die 201 and the flash memory die 202 are both facing upward (i.e., the side of the microcontroller die 201 with the first pad 2011 faces upward, and the side of the flash memory die 202 with the second pad 2021 faces upward), and are placed side by side in the groove 200a, and the bottom of the microcontroller die 201 and the flash memory die 202 can be fixed to the bottom surface of the groove 200a by an adhesive layer 205 formed by any suitable chip adhesive material.

[0057] Next, the gap between the microcontroller die 201 and the flash die 202, the gap between the microcontroller die 201 and the side wall of the groove 200a, and the gap between the flash die 202 and the side wall of the groove 200a are filled with dielectric material 206. The dielectric material 206 can be filled into these gaps by any suitable process according to its material properties. For example, if the dielectric material 206 is an organic polymer dielectric material such as photoresist, it can be filled into these gaps by a coating process. For another example, if the dielectric material 206 is an inorganic dielectric material such as silicon oxide, it can be filled into these gaps by a vapor deposition process.

[0058] At this time, the intermediate package body obtained includes the semiconductor substrate 200, the microcontroller die 201, the flash memory die 202, the adhesive layer 205 and the dielectric material 206. The top surface of the microcontroller die 201, the top surface of the flash memory die 202 and the top surface of the semiconductor substrate 200 constitute a fan-out surface of the intermediate package body, and the dielectric material 206 can not only fill the above-mentioned gap, but also form a certain coverage thickness on the fan-out surface.

[0059] Then, based on the intermediate package body obtained by the above-mentioned fan-out wafer level packaging (FO-WLP) process, a quad flat no-leads package (QFN) packaging process is performed, and the process exemplarily includes:

[0060] First, the dielectric material 206 is opened by photolithography or etching, so that the dielectric material 206 can expose the surface of the first pad 2011 on the microcontroller die 201 and the surface of the second pad 2021 on the flash memory die 202 .

[0061] Next, a redistribution layer (RDL) is formed on the top surface of the dielectric material 206 by a redistribution layer (RDL) process, the redistribution layer including a first redistribution layer and a first dielectric layer 207 sequentially formed on the top surface of the dielectric material 206, and the second interconnection line 204 exposed by the first dielectric layer 207 is used as an external contact pad 204a. In addition, a portion of the first redistribution layer is used as a first interconnection line 203 to connect the first pad 2011 and the second pad 2021, as an A+1 bit address line ADDR[A:0], a D+1 bit data line DATA[D:0] and an x+1 bit storage control signal line RWCTL[x:0]. Among them, one process of the rewiring process includes: forming rewiring (i.e., metal lines) on the surface of the semiconductor substrate 200 through processes such as metal material deposition, photolithography and etching, and then forming new ports (i.e., external contact pads) through dielectric material deposition, photolithography and etching, so as to achieve the re-layout of the corresponding signal input and output ports through the electrical connection between the rewiring and the pads.

[0062] After that, please further combine Figure 4 and Figure 5 , solder paste 208 such as Ni, Au or Ni and Au alloy is applied on each external contact pad 204a, and further the conductive pad 209 is mounted on the external contact pad 204a through the solder paste 208. Each conductive pad 209 is distributed around the periphery of the semiconductor substrate 200, and the top surface and side wall of the conductive pad 209 are exposed to the outside by the first dielectric layer 207, and adjacent conductive pads 209 are spaced apart from each other. Thus, the package body structure of the conventional quad flat no-lead (QFN) is formed, and compared with the conventional QFN package, a lead frame is not required, the product size is small, and the performance of thermal simulation and the like is better.

[0063] It is worth noting that in the present embodiment, the first pad 2011 is arranged on the first side adjacent to the microcontroller die 201 and the flash memory die 202, and the second pad 2021 is arranged on the second side adjacent to the flash memory die 202 and the microcontroller die 201. Thus, the first pad 2021 and the second pad 2021 are adjacently distributed on the same side, which helps to reduce the design difficulty of the first interconnection line 203, shorten the length of the first interconnection line 203, and allow the first interconnection line 203 to be arranged in parallel, thereby avoiding the risk of cross-bonding, thereby improving line reliability and signal transmission speed.

[0064] Further, in this embodiment, the microcontroller die 201 is provided with a corresponding third pad 2012, and the specifications (i.e., area and size) of the third pad 2012 belong to the specifications of a conventional pad, and the specifications of the first pad 2011 and the second pad 2021 are the same, and can be made smaller relative to the specifications of the third pad 2012, that is, the area and size of the first pad 2011 and the second pad 2021 are both smaller than the area and size of the third pad 2012. For example, the area and size of the first pad 2011 and the second pad 2021 are both the minimum allowed by the process, that is, the minimum specifications that meet the stability and reliability of the connection process of the first interconnection line 203 are sufficient, so that the semiconductor substrate 200 does not increase additional area. In one embodiment, at least part of the material of the first pad 2011 and the second pad 2021 is metal aluminum or aluminum-copper alloy, which is convenient for connection with the first interconnection line 203 (material is, for example, copper).

[0065] Moreover, a portion of the first layer rewiring is used as the first interconnection line 203, connecting the first pad 2011 and the second pad 2021, as the A+1 bit address line ADDR[A:0], the D+1 bit data line DATA[D:0] and the x+1 bit storage control signal line RWCTL[x:0]. Another portion of the first layer rewiring is used as the second interconnection line 204, electrically connected to the third pad 2012. The first dielectric layer 207 is used as a passivation layer, burying the first interconnection line 203 and burying part of the surface of the second interconnection line 204, and the second interconnection line 204 exposed by the first dielectric layer 207 is used as an external contact pad 204a.

[0066] In this embodiment, since the first interconnection line and the second interconnection line are formed by a rewiring process, the arrangement of structures such as the external contact pad 204a, the first pad 2011 and the second pad 2021 can be optimized to reduce or even completely eliminate the risk of cross-bonding.

[0067] Moreover, compared with the traditional QFN packaging process, the QFN packaging process in this example can save the lead frame and directly use packaging technology to produce the same square package shape as the traditional QFN packaging process. The product size is smaller and the thermal simulation performance is better.

[0068] As another example, see Figure 3 , Figure 6 and Figure 7The microcontroller die 201 and the flash memory die 202 are packaged in the same package body through a fan-out wafer level packaging (FO-WLP) process and a ball grid array packaging (BGA) process or a wafer level chip scale packaging (WLCSP) process.

[0069] The process of the fan-out wafer level packaging (FO-WLP) process is the same as the above example, and will not be repeated here. The intermediate package body obtained after the fan-out wafer level packaging (FO-WLP) process includes a semiconductor substrate 200, a microcontroller die 201, a flash memory die 202, an adhesive layer 205 and a dielectric material 206. A groove 200a is formed in the semiconductor substrate 200, and the microcontroller die 201 and the flash memory die 202 are both facing upward (that is, the side of the microcontroller die 201 with the first pad 2011 faces upward, and the side of the flash memory die 202 with the second pad 2021 faces upward), and are placed side by side in the groove 200a, and the bottom of the microcontroller die 201 and the flash memory die 202 are fixed to the bottom surface of the groove 200a through the adhesive layer 205. The gap between the microcontroller die 201 and the flash memory die 202, the gap between the microcontroller die 201 and the side wall of the groove 200a, and the gap between the flash memory die 202 and the side wall of the groove 200a are all filled with dielectric material 206. The top surface of the microcontroller die 201, the top surface of the flash memory die 202, and the top surface of the semiconductor substrate 200 constitute a fan-out surface, and the dielectric material 206 not only fills the above gaps, but also forms a certain coverage thickness on the fan-out surface.

[0070] Then, based on the intermediate package body obtained by the above-mentioned fan-out wafer level packaging (FO-WLP) process, a ball grid array packaging (BGA) process is performed, and the process exemplarily includes:

[0071] First, the dielectric material 206 is opened by photolithography or etching, so that the dielectric material 206 can expose the surface of the first pad 2011 on the microcontroller die 201 and the surface of the second pad 2021 on the flash memory die 202 .

[0072] Next, a redistribution layer is formed on the top surface of the dielectric material 206 through a redistribution process, and the redistribution layer includes a first redistribution layer, a first dielectric layer 207, a second redistribution layer, and a second dielectric layer 210, which are sequentially formed on the top surface of the dielectric material 206. A portion of the first redistribution layer serves as a first interconnection line 203, connecting the first pad 2011 and the second pad 2021, serving as an A+1 bit address line ADDR[A:0], a D+1 bit data line DATA[D:0], and an x+1 bit storage control signal line RWCTL[x:0]. One end of a portion of the second redistribution layer is electrically connected to another portion of the first redistribution layer, and the other end is electrically connected to the third pad 2012 on the microcontroller die 201, so as to lead out the third pad 2012 on the microcontroller die 201. That is, a portion of the first layer rewiring is used as the first interconnection line 203, another portion of the first layer rewiring and a portion of the second layer rewiring are used as the second interconnection line 204 to electrically connect the third pad 2022, so as to lead the third pad 2022 to the outside. The second dielectric layer 210 is used as a passivation layer to bury a portion of the surface of the second interconnection line 204, and the second interconnection line 204 exposed by the second dielectric layer 210 is used as an external contact pad 204a. The materials of the first layer rewiring and the second layer rewiring can be the same, for example, both are copper Cu.

[0073] After that, please further combine Figure 6 and Figure 7 , a ball is planted on each external contact pad 204a to form a spherical or columnar solder ball (also called a conductive bump) 211. The material of the solder ball 211 can be Ni, Au, or an alloy of Ni and Au.

[0074] Moreover, compared with the traditional BGA packaging process, the BGA packaging process of this example can save the additional substrate and directly use packaging technology to produce the same package body appearance as the traditional BGA packaging process. The product size is smaller and the thermal simulation performance is better.

[0075] It is worth noting that the third pads 2012 on the microcontroller die 201 may be arranged in any form. For example, the third pads 2012 may be arranged in the peripheral edge regions of the microcontroller die 201 .

[0076] As an example, see Figures 4 to 7Some third pads 2012 may be arranged on the edge region of the first side of the microcontroller die 201 adjacent to the flash memory die 202, and some third pads 2012A among the third pads 2012 arranged on the first side of the microcontroller die 201 may be further connected to the conductive pads 209 (such as the conductive pads 209A) located near the first side of the flash memory die 202 (i.e., the side opposite to the second side thereof, which is also the side of the flash memory die 202 facing away from the microcontroller die 201) through corresponding second interconnection lines 2041. Figure 5 as shown) or solder ball 211 (as shown Figure 7 As shown), in order to reduce parasitic parameters such as parasitic capacitance, the second interconnection lines 2041 connected to the third pads 2012A can be staggered with the first interconnection lines 203.

[0077] It should be understood that in the above embodiments, the microcontroller die and the flash die are both bonded to the bottom of the same groove of the semiconductor substrate through the adhesive layer, but the technical solution of the present invention is not limited to this. In other embodiments of the present invention, a plurality of grooves may be provided in the semiconductor substrate, and the number of these grooves is equal to the total number of the microcontroller die and the flash die, and are arranged one-to-one with each die, so that the microcontroller die and the flash die are placed in different grooves during packaging. In addition, in other embodiments of the present invention, the semiconductor substrate may also be replaced by a substrate of other materials such as plastic (compound).

[0078] It should also be understood that please refer to Figures 9 to 11 In other examples of this embodiment, other fan-out advanced packaging technologies may be used to package the MCU die and the flash memory (FLASH) die together.

[0079] As an example, Fig. 9 It is an intermediate package body obtained by another fan-out wafer level packaging (FO-WLP) process, in which the microcontroller die 201 and the flash memory die 202 are both facing down (that is, the side of the microcontroller die 201 with the first pad 2011 faces down, and the side of the flash memory die 202 with the second pad 2021 faces down), and the dielectric material 206 is coated on the microcontroller die 201 and the flash memory die 202 by injection molding or the like to form a fan-out surface on the top surface of the microcontroller die 201 and the top surface of the flash memory die 202. Fig. 9 and formation Figure 3 The difference in the process of intermediate packaging is: Fig. 9 There is no need for a step of providing the semiconductor substrate 200 , and there is no need for a step of forming the groove 200 a in the semiconductor substrate 200 by photolithography and etching processes. Fig. 9 and Figure 3 The difference in the structure of the intermediate package formed is that Figure 3 The dielectric material 206 fills the gap between the microcontroller die 201 and the flash memory die 202, the gap between the microcontroller die 201 and the side wall of the groove 200a, and the gap between the flash memory die 202 and the side wall of the groove 200a, and can also form a certain covering thickness on the fan-out surface. The dielectric material 206 does not cover the back side of the microcontroller die 201 and the back side of the flash memory die 202. There is an adhesive layer 205 between the back side of the microcontroller die 201 and the back side of the flash memory die 202 and the bottom surface of the groove 200d; and Fig. 9 Since the dielectric material 206 is not filled into these gaps by a filling process but is formed by an injection molding process, it covers the back side of the microcontroller die 201 and the back side of the flash memory die 202, and its surface on the fan-out surface (i.e., the front side of the microcontroller die 201 and the front side of the flash memory die 202) is flush with the fan-out surface, and there is no Figure 3 The groove 200a and the adhesive layer 205 are formed.

[0080] In summary, whether it is Figure 3 still Fig. 9 In the embodiment of forming the intermediate package, the top surface of the microcontroller die 201 and the top surface of the flash memory die 202 together constitute a fan-out surface of the intermediate package.

[0081] Fig.10 and Fig.11 Respectively in Fig. 9 Based on the intermediate package, a quad flat no-lead (QFN) package (such as Fig.10 ) and ball grid array (BGA) packages (such as Fig.11 shown). Fig.10 The specific process and Figure 4 correspond, Fig.11 The specific process and Figure 6 Correspondingly, no further description is given here. It is worth noting that the advanced packaging processes of the above-mentioned examples are only examples, and do not mean that the advanced packaging processes of this embodiment are limited to the above-mentioned examples. Moreover, the redistribution layer is not limited to one or two layers of redistribution, and more layers of redistribution can be designed according to the wiring needs.

[0082] It should be understood that no matter what advanced packaging process is used in this embodiment to seal the microcontroller die 201 and the flash memory die 202 together, it is necessary to connect the first pad 2011 of the microcontroller die 201 and the second pad 2021 of the flash memory die 202 through the first interconnect line 203 to form a multi-bit address line ADDR[A:0], a multi-bit data line DATA[D:0] and a multi-bit storage control signal line RWCTL[x:0].

[0083] The data transmission timing diagram between the microcontroller die 201 and the flash memory die 202 is shown in FIG. Fig.12 As shown, ADDR, DATA, and RWCTL are multi-bit parallel transmissions, and different values ​​of RWCTL correspond to different operation modes, and then by changing ADDR, DATA, and RWCTL, the read, write, and erase of the flash die 202 are completed. For example, when the bus of the microcontroller die 201 receives a read access request, a corresponding value is taken by RWCTL to enter the read data mode, and then according to the address and data of the read access request, the required code and data are read in parallel from the flash die 202 through the multi-bit address line ADDR[A:0] and the multi-bit data line DATA[D:0]. When the bus of the microcontroller die 201 receives a write access request, another corresponding value is taken by RWCTL to enter the write data mode, and then according to the address and data of the read access request, the code and / or data to be written are written in parallel to the flash die 202 through the multi-bit address line ADDR[A:0] and the multi-bit data line DATA[D:0].

[0084] In one embodiment, the number of the first interconnection lines 203 as the multi-bit address lines ADDR[A:0] is (A+1), and the maximum physical addressing space of the storage array in the corresponding flash memory die 202 is [0,2 A+1 -1]. For example, A+1=32, then the maximum physical address addressing space of the FLASH corresponding to the 32 address lines ADDR[31:0] is 0xFFFFFFFF~0x00000000.

[0085] In another embodiment, the first interconnection line 203 of the multi-bit storage control signal line RWCTL is used to transmit the control signal generated by the storage control logic circuit 201a according to the read, write and erase instruction. In other embodiments, the number of the first interconnection lines as the multi-bit data line DATA[D:0] is (D+1), corresponding to the read and write data bit width of the storage array in the FLASH bare chip 202.

[0086] It is worth noting that the storage control logic circuit 201a of this embodiment is completely different from the storage control logic circuit 101a of the prior art in terms of circuit implementation. Figure 1In the embodiment, the FLASH die 102 and the MCU die 101 communicate via the SPI serial port protocol, and the storage control logic circuit 101a needs to perform serial-to-parallel protocol conversion to generate the IO signal DATAIO, the clock signal CLK and the chip select signal CS of the SPI protocol, and requires an additional buffer or latch to realize the protocol conversion; and in the embodiment, Figure 2 The FLASH die 202 and the MCU die 201 communicate with each other through a custom proprietary parallel protocol, and the storage control logic circuit 201a is directly coupled to the bus inside the microcontroller die 201 (i.e. Figure 2 The bus in the memory is a high-speed bus inside the MCU, such as an AXI or AHB bus) and the first interconnection line 203, converting the control signal of the high-speed bus inside the MCU into a FLASH interface signal (i.e., an address signal, a data signal, and a read-write-erase control signal) to control the data transmission between the MCU bare chip 201 and the FLASH bare chip 202. The MCU bare chip 201 can directly store and access the program code in the FLASH bare chip 202 through the storage control logic circuit 201a, without the need to copy the data in the FLASH bare chip 202 to the random access memory RAM (usually implemented by a static random access memory SRAM), saving the area of ​​the random access memory, thereby further reducing the cost, and the FLASH interface signal is transmitted in parallel, without the need for serial-to-parallel protocol conversion, further reducing the circuit area of ​​the microcontroller bare chip 201.

[0087] In this embodiment, since the address signal, data signal and read / write / erase control signal between the microcontroller die 201 and its external flash memory die 202 are directly transmitted in parallel point-to-point without protocol conversion, the microcontroller die 201 can read, write and erase data from the flash memory die 202 to achieve data reading and writing effects similar to eFLASH, greatly improving the data reading and writing speed. In addition, since the microcontroller die 201 and the flash memory die 202 are two independent die, the problem of eFLASH occupying the area of ​​the microcontroller die 201 will not occur.

[0088] In summary, the technical solution of this embodiment has the advantages of high capacity, low memory price, and fast time to market. There are no major technical barriers in manufacturing and it can be applied to 22nm and smaller silicon lithography technology nodes, enabling MCU chips to move towards more advanced processes.

[0089] Second embodiment

[0090] Please refer to Figure 13 to Figure 14The present embodiment provides a microcontroller chip (i.e., MCU chip), which includes a microcontroller die (i.e., MCU die) 201, two flash memory die (FLASH die) 202a, 202b, and a plurality of first interconnection lines 203 packaged in the same package body through an advanced packaging process.

[0091] Among them, the microcontroller die 201 and the two flash memory dies 202a and 202b are three independent dies, which can be manufactured using different integrated circuit manufacturing processes. In other embodiments, the two flash memory dies 202a and 202b can be manufactured using the same integrated circuit manufacturing process.

[0092] The microcontroller die 201 has a storage control logic circuit 201a and other logic circuits integrated therein, and a plurality of first pads are added on the top surface. The flash die 202a and the flash die 202b are additionally provided with a plurality of second pads, and these second pads 2021 are arranged corresponding to some or all of the first pads 2011 in the microcontroller die 201. Specifically, a portion of the first pads 2011 on the microcontroller die 201 and a plurality of second pads 2021 on the flash die 202a are connected one-to-one through a portion of the first interconnection lines, thereby forming an A+1 bit address line ADDR. a [A:0], D+1 bit data line DATA a [D:0] and x+1 bit storage control signal line RWCTL a [x:0]; another part of the first pads 2011 on the microcontroller die 201 and a number of second pads 2021 on the flash die 202b are connected one-to-one through another part of the first interconnection line, thereby forming a B+1 bit address line ADDR b [B:0], C+1 bit data line DATA b [C:0] and y+1 bit storage control signal line RWCTL b [y:0] Where A, B, C, D, x, and y are all integers greater than 1.

[0093] One of the flash die 202a and the flash die 202b is used to support the online operation of the microcontroller chip 201, and the other is used to support the upgrade of the microcontroller chip 201. That is, the flash die 202a and the flash die 202b are both integrated with corresponding storage arrays, and one of the flash die 202a and the flash die 202b is used to store the code required for the MCU chip upgrade, and the other is used to store the code required for the MCU chip operation and the generated data.

[0094] The structures of the microcontroller die 201 and the two flash memory die (FLASH die) 202a and 202b can be referred to Figures 3 to 8 , and can be packaged in the same package body using an advanced packaging process that is basically the same as the first embodiment, which will not be described in detail here.

[0095] It should be understood that the microcontroller chip of this embodiment is actually an MCU system architecture in which a microcontroller (MCU) die is externally connected to two flash memory (FLASH) dies. Therefore, the number of first pads 2011 added to the microcontroller die 201 can be equal to or greater than the total number of second pads 2021 added to the flash memory dies 202a and 202b.

[0096] Compared with the microcontroller chip of the first embodiment, the microcontroller chip of this embodiment has two flash memory dies, each of which has multi-bit parallel communication with the corresponding first pad 2011 on the microcontroller die without protocol conversion, and can support the working mode of multiple flash memory dies (FLASH die).

[0097] It should be understood that the present invention is not limited to the external application of the FLASH die 202. The microcontroller chip architecture of the present invention can also support, for example, static memory SRAM, sensor sensor, power management unit PMU and radio frequency circuit RF (Radio Frequency) and the like to be packaged in the same package body with the microcontroller die through advanced packaging technology. Specifically, Figure 2 or Fig.13 The FLASH die 202 in the illustrated embodiment is replaced by a static memory SRAM die, a sensor die, a power management unit PMU die, or a radio frequency circuit RF die.

[0098] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A microcontroller chip, characterized in that: Including the following encapsulated in the same package through advanced packaging technology: A microcontroller die, wherein a storage control logic circuit is integrated inside the microcontroller die and a plurality of first pads are provided on a first external side thereof; At least one flash memory die, wherein a storage array is integrated inside the flash memory die and a plurality of second pads are disposed on a second side of the outside; A plurality of first interconnection lines connect the plurality of first bonding pads and the plurality of second bonding pads in a one-to-one correspondence to form a multi-bit address line, a multi-bit data line and a multi-bit storage control signal line.

2. The microcontroller chip according to claim 1, characterized in that: The microcontroller die and the flash memory die are arranged side by side, the first pad is arranged on the first side of the microcontroller die adjacent to the flash memory die, and the second pad is arranged on the second side of the flash memory die adjacent to the microcontroller die.

3. The microcontroller chip according to claim 1, characterized in that: The top surface of the microcontroller die and the top surface of the flash memory die together form a fan-out surface of the intermediate package body within the package body.

4. The microcontroller chip as claimed in claim 3, characterized in that: The package also has a redistribution layer formed on the fan-out surface, and a portion of the redistribution in the redistribution layer is used as the first interconnection line.

5. The microcontroller chip as claimed in claim 4, characterized in that: A plurality of third pads are also provided on at least one of the microcontroller die and the flash memory die, and another corresponding portion of the redistribution in the redistribution layer serves as a second interconnection line electrically connected to the third pads, and a portion of the top surface of the second interconnection line is exposed to the outside and forms an external contact pad.

6. The microcontroller chip as claimed in claim 5, characterized in that: Only one layer of redistribution wiring is formed in the redistribution wiring layer, a part of the layer of redistribution wiring is used as the first interconnection line, and another part of the layer of redistribution wiring is used as the second interconnection line.

7. The microcontroller chip as claimed in claim 5, characterized in that: The redistribution layer includes a first layer of redistribution and a second layer of redistribution formed from bottom to top on the fan-out surface, a portion of the first layer of redistribution serves as the first interconnection line, another portion of the first layer of redistribution and a portion of the second layer of redistribution serve as the second interconnection line to electrically connect the third pad.

8. The microcontroller chip as claimed in claim 5, characterized in that: The outer contact pads are planted with solder balls.

9. The microcontroller chip as claimed in claim 5, characterized in that: The top surface of the external contact pad forms a corresponding conductive pad, each of the conductive pads is distributed around the periphery of the package body, and the top surface or side surface of each of the conductive pads is exposed to the outside by the package body.

10. The microcontroller chip as claimed in claim 5, characterized in that: The areas of the first welding pad and the second welding pad are both smaller than the area of ​​the third welding pad.

11. The microcontroller chip according to any one of claims 1 to 10, characterized in that: The areas and sizes of the first bonding pad and the second bonding pad are both minimum specifications allowed by the first interconnection line connection process.

12. The microcontroller chip as claimed in claim 3, characterized in that: The package body further has a semiconductor substrate, the microcontroller die and the flash memory die are both installed in the groove of the semiconductor substrate, and the microcontroller die, the flash memory die and the top surface of the semiconductor substrate together constitute the fan-out surface, wherein the microcontroller die and the flash memory die are both bonded to the bottom of the same groove or different grooves of the semiconductor substrate through an adhesive layer, and the gaps in each of the grooves after the microcontroller die and the flash memory die are installed are filled with dielectric material.

13. The microcontroller chip according to claim 1, characterized in that: There are two flash memory bare chips, one of which is used to support the online operation of the microcontroller chip, and the other of which is used to support the upgrade of the microcontroller chip.

14. The microcontroller chip according to any one of claims 1-10 or 12-13, characterized in that: The number of the first interconnection lines as the multi-bit address lines is (A+1), and the maximum physical addressing space of the corresponding storage array is [0,2 A+1 -1].

15. The microcontroller chip according to any one of claims 1-10 or 12-13, characterized in that: The first interconnecting lines serving as the multi-bit storage control signal lines are used to transmit control signals generated by the storage control logic circuit in response to read, write and erase instructions; the number of the first interconnecting lines serving as the multi-bit data lines is (D+1), corresponding to the read and write data bit width of the storage array.

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