Fast recovery diode and manufacturing method thereof

Abstract

The invention discloses a fast recovery diode. A PN main junction formed by a second electrode region and a first epitaxial layer is formed in an active region. The first epitaxial layer is formed on the top surface of a first conductive type heavily doped semiconductor substrate, and the semiconductor substrate serves as a first electrode region. The second electrode region comprises a plurality of heavily-doped injection region pattern structures of a second conduction type, the injection region pattern structures are arranged in the active region in a two-dimensional manner, the adjacent injection region pattern structures are transversely connected, and the bottom surfaces of the adjacent injection region pattern structures are located at positions with different depths in the first epitaxial layer; the junction interface of the PN main junction is a curved surface in two-dimensional periodic distribution, and the area of the junction interface of the PN main junction is larger than the area of the top surface of the first epitaxial layer of the active region, so that the power density of the fast recovery diode is increased. The invention further discloses a manufacturing method of the fast recovery diode. The power density of the device can be increased while the turn-off speed of the device is not reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a fast recovery diode (FRD); the present invention also relates to a method for manufacturing a fast recovery diode. Background Art

[0002] With the development of science and technology, power fast recovery diode devices have been widely used in many fields. Power FRD devices play a key role in energy conversion and power electronic equipment, and have become indispensable devices in life and industry.

[0003] In the design of semiconductor power FRD devices, the structure of the active region often determines the main characteristics of the device, such as forward resistance, withstand voltage, switching speed, etc. Improving the maximum forward current of the diode has always been the direction of improving device performance. The commonly used method is to increase the concentration of the anode region such as the P+ region or expand the size of the active region. Although this increases the maximum current of the device, it will cause the device to turn off more slowly and the reverse time to become longer. When the fast recovery diode is in high-frequency application, the energy consumption becomes higher and the efficiency decreases. In addition, increasing the concentration of the anode region will significantly increase the electric field at the P / N junction, increasing the risk of dynamic avalanche damage to the device.

[0004] like Figure 1A As shown in FIG. 1 , it is a schematic diagram of the cross-sectional structure of an existing fast recovery diode; Figure 1B , which is a schematic diagram of the top view structure of an existing fast recovery diode;

[0005] like Figure 1A As shown in FIG. 1 , it is a schematic diagram of the cross-sectional structure of an existing fast recovery diode; Figure 1B As shown, it is a schematic diagram of the top view structure of the existing fast recovery diode. Figure 1A is along Figure 1B A schematic diagram of the cross-sectional structure at the dotted line BB of FIG. 1 ; the existing fast recovery diode includes:

[0006] The N-type heavily doped semiconductor substrate 101 serves as a cathode region.

[0007] An N-type lightly doped first epitaxial layer 102 is formed on the top surface of the semiconductor substrate 101 .

[0008] The fast recovery diode is divided into an active region 101a and a terminal region 101b, and the terminal region 101b surrounds the active region 101a. Figure 1A In FIG. 1 , the active region 101 a is located on the left side of the dotted line AA, and the termination region 101 b is located on the right side of the dotted line AA.

[0009] A PN main junction formed by the anode region 103 and the first epitaxial layer 102 is formed in the active region 101 a .

[0010] The anode region 103 is a P-type heavily doped region. Figure 1B As shown, the anode region 103 is formed by opening the active region 101a and then implanting P-type heavily doped ions.

[0011] The structure of the terminal area 101b is a terminal structure, and the terminal structure includes:

[0012] A plurality of P-type doped field limiting rings 104. The top of each field limiting ring 104 is connected to a field plate formed by patterning the front metal layer 107 through a contact hole.

[0013] A plurality of contact holes penetrates the interlayer film 106 .

[0014] N-type heavily doped cut-off ring 105. The top of the cut-off ring 105 is connected to a metal electrode formed by patterning the front metal layer 107 through a contact hole, and the metal electrode can be connected to the first metal electrode on the back. Summary of the invention

[0015] The technical problem to be solved by the present invention is to provide a fast recovery diode which can increase the power density of the device without reducing the turn-off speed of the device and can also not affect the reverse breakdown voltage of the entire device. To this end, the present invention also provides a method for manufacturing a fast recovery diode.

[0016] In order to solve the above technical problems, the fast recovery diode provided by the present invention comprises:

[0017] A semiconductor substrate heavily doped with a first conductivity type, wherein the semiconductor substrate serves as a first electrode region.

[0018] A first epitaxial layer lightly doped with a first conductivity type is formed on the top surface of the semiconductor substrate.

[0019] The fast recovery diode is divided into an active region and a terminal region, and the terminal region surrounds the active region.

[0020] A PN main junction formed by the second electrode region and the first epitaxial layer is formed in the active region.

[0021] The second electrode region includes a plurality of heavily doped injection region graphic structures of the second conductivity type, wherein the injection region graphic structures are arranged two-dimensionally in the active region, each adjacent injection region graphic structure is laterally connected, and the bottom surface of each adjacent injection region graphic structure is located at a different depth in the first epitaxial layer, and the junction interface of the PN main junction is a two-dimensionally periodically distributed curved surface and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer in the active region, so as to increase the power density of the fast recovery diode.

[0022] A further improvement is that the structure of the curved surface of the junction interface of the PN main junction ensures that the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction is greater than the breakdown voltage of the PN main junction at the edge of the active area and the terminal structure of the terminal area.

[0023] A further improvement is that the injection region graphic structure includes at least two types, namely a first injection region graphic structure and a second injection region graphic structure.

[0024] In a top view, each of the first injection area graphic structures and each of the second injection area graphic structures are in a strip shape; the two-dimensional arrangement structure of the first injection area graphic structures and the second injection area graphic structures is: along the width direction of each of the first injection area graphic structures, each of the first injection area graphic structures and each of the second injection area graphic structures are arranged alternately in parallel.

[0025] Alternatively, in a top view, each of the first injection region graphic structures and each of the second injection region graphic structures are polygonal; and the two-dimensional arrangement structure of the first injection region graphic structure and the second injection region graphic structure is:

[0026] The first implantation region pattern structures and the second implantation region pattern structures are arranged in a row structure and a column structure.

[0027] In each of the row structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately.

[0028] In each of the column structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately.

[0029] A further improvement is that the polygon of each of the first injection region graphic structures includes a square, and the polygon of each of the second injection region graphic structures includes a square.

[0030] A further improvement is that the first conductivity type is N-type, the second conductivity type is P-type, the first electrode region is the cathode region, and the second electrode region is the anode region; or, the first conductivity type is P-type, the second conductivity type is N-type, the first electrode region is the anode region, and the second electrode region is the cathode region.

[0031] In order to solve the above technical problems, the manufacturing method of the fast recovery diode provided by the present invention comprises the following steps:

[0032] Step 1: providing a semiconductor substrate heavily doped with a first conductivity type, the semiconductor substrate serving as a first electrode region, and forming a first epitaxial layer lightly doped with a first conductivity type on a top surface of the semiconductor substrate.

[0033] Step 2: The fast recovery diode is divided into an active area and a terminal area, and the terminal area surrounds the active area; a second conductive type heavily doped ion implantation process is used to form a plurality of implantation area graphic structures in the active area, and the implantation area graphic structures are arranged two-dimensionally in the active area, and the bottom surfaces of each adjacent implantation area graphic structure are located at different depths in the first epitaxial layer.

[0034] Step three, perform annealing and diffusion to connect the graphic structures of the injection regions to form a second electrode region, and a PN main junction formed by the second electrode region and the first epitaxial layer, wherein the junction interface of the PN main junction is a two-dimensional periodically distributed curved surface and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer of the active region, so as to increase the power density of the fast recovery diode.

[0035] A further improvement is that the structure of the curved surface of the junction interface of the PN main junction ensures that the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction is greater than the breakdown voltage of the PN main junction at the edge of the active area and the terminal structure of the terminal area.

[0036] A further improvement is that the injection region graphic structure includes at least two types, namely a first injection region graphic structure and a second injection region graphic structure.

[0037] In step 2, the first implantation region graphic structure and the second implantation region graphic structure are formed simultaneously by using the same first ion implantation process, and the first ion implantation process passes through the first implantation mask layer and enters the surface area of ​​the first epitaxial layer.

[0038] Before performing the first ion implantation process, the method further includes:

[0039] The first injection mask layer is subjected to a graphical definition process so that the first injection mask layer has different thicknesses in the first injection area graphic structure and the second injection area graphic structure, and the first injection mask layer with different thicknesses defines the depth position of the bottom surface of the first injection area graphic structure and the second injection area graphic structure.

[0040] Alternatively, before performing the first ion implantation process, the method further includes:

[0041] A top surface of the first epitaxial layer of the active region is subjected to a graphic definition process, so that the positions of the top surface of the first epitaxial layer corresponding to the first implantation region graphic structure and the second implantation region graphic structure are different, and the depth positions of the bottom surfaces of the first implantation region graphic structure and the second implantation region graphic structure are defined by the different positions of the top surface of the first epitaxial layer; after the first ion implantation process, the method further includes:

[0042] The positions of the top surfaces of the first epitaxial layer corresponding to the first implantation region pattern structure and the second implantation region pattern structure are adjusted to be the same.

[0043] A further improvement is that the step of performing a patterning process on the first implantation mask layer includes the following sub-steps:

[0044] A first implant mask sublayer is grown.

[0045] A first hard mask layer is formed on a surface of the first implantation mask sublayer.

[0046] Photolithography is performed to open one of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure and to cover the other of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure.

[0047] Etching is performed to remove the first hard mask layer in the open area and the first implantation mask sublayer at the bottom.

[0048] A second implantation mask sublayer is grown in the opened region, wherein the thickness of the second implantation mask sublayer is different from the thickness of the first implantation mask sublayer.

[0049] The first hard mask layer is removed, and the first implantation mask layer is formed by the first implantation mask sublayer and the second implantation mask sublayer.

[0050] A further improvement is that the step of performing a patterning process on the top surface of the first epitaxial layer of the active region comprises the following sub-steps:

[0051] A second hard mask layer is formed on a top surface of the first epitaxial layer.

[0052] Photolithography is performed to open one of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure and to cover the other of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure.

[0053] Etching is performed to remove the second hard mask layer in the open area and to lower the top surface of the first epitaxial layer at the bottom.

[0054] The second hard mask layer is removed.

[0055] The first implantation mask layer is formed.

[0056] After the annealing and diffusion, the method further comprises:

[0057] Photolithography is performed to cover one of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure and to open the other of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure.

[0058] Etching is performed to lower the top surface of the first epitaxial layer in the open area and adjust the positions of the top surfaces of the first epitaxial layer corresponding to the first implantation region pattern structure and the second implantation region pattern structure to be the same.

[0059] A further improvement is that, in a top view, each of the first injection area graphic structures and each of the second injection area graphic structures are in a strip shape; the two-dimensional arrangement structure of the first injection area graphic structure and the second injection area graphic structure is: along the width direction of each of the first injection area graphic structures, each of the first injection area graphic structures and each of the second injection area graphic structures are arranged alternately in parallel.

[0060] Alternatively, in a top view, each of the first injection region graphic structures and each of the second injection region graphic structures are polygonal; and the two-dimensional arrangement structure of the first injection region graphic structure and the second injection region graphic structure is:

[0061] The first implantation region pattern structures and the second implantation region pattern structures are arranged in a row structure and a column structure.

[0062] In each of the row structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately.

[0063] In each of the column structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately.

[0064] A further improvement is that the polygon of each of the first injection region graphic structures includes a square, and the polygon of each of the second injection region graphic structures includes a square.

[0065] A further improvement is that the thickness of the first injection mask sublayer is 40 nm to 60 nm; and the thickness of the second injection mask sublayer is 10 nm to 30 nm.

[0066] A further improvement is that the process conditions of the first ion implantation process include:

[0067] The injection energy is 60keV~100keV, and the injection dose is 1E13cm -2 ~5E13cm -2 .

[0068] A further improvement is that in step three, the temperature of the annealing diffusion is 1000°C to 1200°C.

[0069] A further improvement is that the resistivity of the first epitaxial layer is 50 ohm·cm to 90 ohm·cm.

[0070] The second electrode region of the present invention is formed by an injection region and the injection region is patterned. By setting the depth position of the bottom surface of the injection region graphic structure, the junction interface of the second electrode region formed by connecting the injection region graphic structures and the PN main junction formed by the first epitaxial layer can be a two-dimensional periodically distributed curved surface. In this way, the area of ​​the junction interface of the PN main junction can be larger than the area of ​​the active region, that is, the top surface area of ​​the first epitaxial layer of the active region. In this way, the area of ​​the junction interface of the PN main junction is not limited by the size of the area of ​​the active region. Therefore, the area of ​​the junction interface of the PN main junction can be increased without increasing the area of ​​the active region, thereby increasing the effective emission area of ​​the second electrode region, and thus significantly improving the forward characteristics of the fast recovery tube, improving the forward current passing capacity, and thus increasing the power density of the fast recovery diode.

[0071] At the same time, since the present invention increases the power density of the fast recovery diode by increasing the area of ​​the junction interface of the PN main junction, the power density can be increased without increasing the doping concentration of the second electrode region and the area of ​​the active region, so that the turn-off speed of the device will not be reduced; moreover, the increase in the area of ​​the junction interface of the PN main junction can not only increase the number of carriers when the device is turned on, but also increase the area of ​​minority carrier extraction when the device is reversed, thereby avoiding increasing the reverse recovery time. Therefore, the present invention can improve the forward characteristics of the fast recovery tube without reducing the turn-off speed, and finally improve the performance of the device.

[0072] In addition, the second electrode region of the present invention is formed by connecting the implantation region graphic structures at different depth positions on the bottom surface, which can make the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction greater than the breakdown voltage of the PN main junction at the edge of the active region and the terminal structure of the terminal region. In this way, the overall reverse breakdown voltage of the device is still determined by the breakdown voltage of the PN main junction at the edge of the active region and the terminal structure of the terminal region, so the present invention does not affect the reverse breakdown voltage of the entire device.

[0073] In addition, the process of the implantation region graphic structure is simple and completely compatible with the existing process, so the present invention also has the advantage of being easy to implement.

[0074] In summary, the present invention can improve the power density of power devices under existing process capabilities and increase the application scenarios of the devices.

[0075] At the same time, the device structure of the present invention is relatively simple, and can adjust the area of ​​the junction interface of the PN main junction and adjust the emission area of ​​the second electrode region such as the emission area of ​​the anode region, thereby improving the forward performance under the same chip area, including reducing the forward on-resistance, increasing the maximum on-current, etc.

[0076] In addition, the present invention can also reduce the chip area. Under the condition of the same voltage and current characteristics, it can be implemented with a smaller chip area.

[0077] The manufacturing process of the present invention is fully compatible with the existing general power device FRD process, and the solution is relatively easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0079] Figure 1A It is a schematic diagram of the cross-sectional structure of an existing fast recovery diode;

[0080] Figure 1B It is a schematic diagram of the top view structure of an existing fast recovery diode;

[0081] Figure 2A is a schematic cross-sectional structure diagram of a fast recovery diode according to an embodiment of the present invention;

[0082] Figure 2B 1 is a schematic diagram of a top view structure of a fast recovery diode according to an embodiment of the present invention;

[0083] Figure 3A-3E It is a schematic diagram of the device structure in each step of the method for manufacturing a fast recovery diode according to the first preferred embodiment of the present invention;

[0084] Figure 4A-4G It is a schematic diagram of the device structure in each step of the manufacturing method of the fast recovery diode of the second preferred embodiment of the present invention. DETAILED DESCRIPTION

[0085] like Figure 2A , which is a schematic cross-sectional structure diagram of a fast recovery diode according to an embodiment of the present invention; Figure 2B , which is a schematic diagram of the top view structure of the fast recovery diode according to an embodiment of the present invention, Figure 2A is along Figure 2B A schematic diagram of the cross-sectional structure at the dotted line BB of the embodiment of the present invention; the fast recovery diode comprises:

[0086] A semiconductor substrate 201 that is heavily doped with a first conductivity type, the semiconductor substrate 201 serves as a first electrode region.

[0087] A first epitaxial layer 202 lightly doped with a first conductivity type is formed on the top surface of the semiconductor substrate 201 .

[0088] The fast recovery diode is divided into an active region 201a and a terminal region 201b, and the terminal region 201b surrounds the active region 201a. Figure 1A In the figure, the active region 201a is located on the left side of the dotted line AA, and the termination region 201b is located on the right side of the dotted line AA.

[0089] A PN main junction formed by the second electrode region 203 and the first epitaxial layer 202 is formed in the active region 201 a .

[0090] The second electrode region 203 includes a plurality of heavily doped injection region graphic structures of the second conductivity type, the injection region graphic structures are arranged two-dimensionally in the active region 201a, adjacent injection region graphic structures are laterally connected, the bottom surfaces of adjacent injection region graphic structures are located at different depths in the first epitaxial layer 202, the junction interface of the PN main junction is a two-dimensionally periodically distributed curved surface and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer 202 of the active region 201a, so as to increase the power density of the fast recovery diode.

[0091] In the embodiment of the present invention, the structure of the curved surface of the junction interface of the PN main junction ensures that the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction is greater than the breakdown voltage of the PN main junction at the edge of the active area 201a and the terminal structure of the terminal area 201b.

[0092] In the embodiment of the present invention, the injection region pattern structure includes at least two types, namely, a first injection region pattern structure 203a and a second injection region pattern structure 203b. As an example, Figure 2A In the embodiment, the depth position of the bottom surface of the first injection region graphic structure 203a is lower than the depth position of the bottom surface of the second injection region graphic structure 203b. In some embodiments, the minimum depth of the ion implantation of the second injection region graphic structure 203b can be 0nm, that is, no impurities are implanted on the surface of the first epitaxial layer 202; after annealing and diffusion, the impurities of the second injection region graphic structure 203b are formed by the diffusion of the impurities of the first injection region graphic structure 203a. In some embodiments, the depth of the ion implantation of the second injection region graphic structure 203b is greater than 0nm but less than the depth of the ion implantation of the first injection region graphic structure 203a; after annealing and diffusion, the depth position of the bottom surface of the first injection region graphic structure 203a will be lower than the depth position of the bottom surface of the second injection region graphic structure 203b. By adjusting the depth of the ion implantation of the first injection region graphic structure 203a and the second injection region graphic structure 203b, the area of ​​the junction interface of the PN main junction can be adjusted.

[0093] like Figure 2B As shown, in the embodiment of the present invention, in the top view, each first injection region graphic structure 203a and each second injection region graphic structure 203b are in the shape of strips; the two-dimensional arrangement structure of the first injection region graphic structure 203a and the second injection region graphic structure 203b is: along the width direction of each first injection region graphic structure 203a, each first injection region graphic structure 203a and each second injection region graphic structure 203b are arranged alternately in parallel. In some embodiments, the width of each first injection region graphic structure 203a is equal to the width of each second injection region graphic structure 203b. In some embodiments, it can also be: the width of each first injection region graphic structure 203a and the width of each second injection region graphic structure 203b are not equal. By adjusting the width of each first injection region graphic structure 203a and the width of each second injection region graphic structure 203b, the area of ​​the junction interface of the PN main junction can be adjusted.

[0094] In the embodiment of the present invention, the number, width and morphology of the first injection region graphic structure 203a or each second injection region graphic structure 203b can be controlled by adjusting process parameters according to the performance requirements of the device. Theoretically, the more the number of the first injection region graphic structure 203a or each second injection region graphic structure 203b, the more significant the improvement in power density.

[0095] In some embodiments, it can also be that: in the top view, each first injection region graphic structure 203a and each second injection region graphic structure 203b are polygonal; the two-dimensional arrangement structure (not shown) of the first injection region graphic structure 203a and the second injection region graphic structure 203b is:

[0096] Each first injection region graphic structure 203a and each second injection region graphic structure 203b are arranged in a row structure and a column structure. Further, in some preferred embodiments, the polygon of each first injection region graphic structure 203a includes a square, and the polygon of each second injection region graphic structure 203b includes a square. In other embodiments, each first injection region graphic structure 203a can also adopt other polygonal structures, and the polygonal structure of the second injection region graphic structure 203b is formed by surrounding the edge of the first injection region graphic structure 203a on the circumferential side.

[0097] In each row structure, each first implantation region pattern structure 203 a and each second implantation region pattern structure 203 b are aligned and arranged alternately.

[0098] In each column structure, each first implantation region pattern structure 203 a and each second implantation region pattern structure 203 b are aligned and arranged alternately.

[0099] In the embodiment of the present invention, the first conductivity type is N type, the second conductivity type is P type, the first electrode region is a cathode region, and the second electrode region 203 is an anode region. In other embodiments, the first conductivity type is P type, the second conductivity type is N type, the first electrode region is an anode region, and the second electrode region 203 is a cathode region.

[0100] like Figure 2A As shown, a second metal electrode 207a formed by patterning the front metal layer 207 is also formed on the top surface of the second electrode region 203. A first metal electrode formed by the back metal layer is formed on the back of the first electrode region. Since in the embodiment of the present invention, the first electrode region is a cathode region and the second electrode region 203 is an anode region, the first metal electrode is a cathode and the second metal electrode 207a is an anode.

[0101] The embodiment of the present invention mainly changes the structure of the active area 201a, and does not improve the structure in the terminal area 201b. The structure in the terminal area 201b is briefly introduced as follows:

[0102] The structure of the terminal area 201b is a terminal structure, which includes:

[0103] A plurality of second conductivity type doped field limiting rings 204. The top of each field limiting ring 204 is connected to a field plate patterned by a front metal layer 207 through a contact hole.

[0104] A plurality of contact holes penetrates the interlayer film 206 .

[0105] A first conductive type heavily doped cut-off ring 205. The top of the cut-off ring 205 is connected to a metal electrode patterned by the front metal layer 207 through a contact hole, and the metal electrode can be connected to the first metal electrode on the back.

[0106] The second electrode region 203 of the embodiment of the present invention is formed by an injection region and the injection region is patterned. By setting the depth position of the bottom surface of the injection region graphic structure, the junction interface of the PN main junction formed by the second electrode region 203 connected by the injection region graphic structures and the first epitaxial layer 202 can be a two-dimensional periodically distributed curved surface. In this way, the area of ​​the junction interface of the PN main junction can be larger than the area of ​​the active region 201a, that is, the top surface area of ​​the first epitaxial layer 202 of the active region 201a. In this way, the area of ​​the junction interface of the PN main junction is not limited by the size of the area of ​​the active region 201a. Therefore, the area of ​​the junction interface of the PN main junction can be increased without increasing the area of ​​the active region 201a, thereby increasing the effective emission area of ​​the second electrode region 203, and thus significantly improving the forward characteristics of the fast recovery tube, improving the forward current passing capacity, and thus increasing the power density of the fast recovery diode.

[0107] At the same time, since the embodiment of the present invention increases the power density of the fast recovery diode by increasing the area of ​​the junction interface of the PN main junction, the power density can be increased without increasing the doping concentration of the second electrode region 203 and the area of ​​the active region 201a, thereby not reducing the turn-off speed of the device; moreover, the increase in the area of ​​the junction interface of the PN main junction can not only increase the number of carriers when the device is turned on, but also increase the area of ​​minority carrier extraction when the device is reversed, thereby avoiding increasing the reverse recovery time. Therefore, the embodiment of the present invention can improve the forward characteristics of the fast recovery tube without reducing the turn-off speed, and finally improve the performance of the device.

[0108] In addition, the second electrode region 203 of the embodiment of the present invention is formed by connecting the implantation region graphic structures at different depth positions of the bottom surface, so that the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction can be greater than the breakdown voltage of the terminal structure of the PN main junction at the edge of the active region 201a and the terminal region 201b. In this way, the overall reverse breakdown voltage of the device is still determined by the breakdown voltage of the terminal structure of the PN main junction at the edge of the active region 201a and the terminal region 201b, so the present invention does not affect the reverse breakdown voltage of the entire device. This is mainly because, for FRDs working at high voltage, the main reason affecting the breakdown voltage of the device is the junction surface bending or field limiting ring at the edge of the PN main junction. The actual breakdown voltage of these positions is only far less than the breakdown voltage at the existing PN main junction ground plate, that is, the breakdown voltage at the bottom flat area of ​​the PN main junction. In the embodiment of the present invention, by changing the bottom morphology of the PN main junction, the effective emission area of ​​the anode region is increased, but the reverse breakdown voltage of the entire device is not affected, which can significantly improve the forward characteristics of the fast recovery tube and improve the forward current passing capacity.

[0109] In addition, the process of the implantation region graphic structure is simple and completely compatible with existing processes, so the embodiment of the present invention also has the advantage of being easy to implement.

[0110] In summary, the embodiments of the present invention can improve the power density of power devices under existing process capability conditions, thereby increasing the application scenarios of the devices.

[0111] At the same time, the device structure of the embodiment of the present invention is relatively simple, and can adjust the area of ​​the junction interface of the PN main junction and adjust the emission area of ​​the second electrode region 203 such as the emission area of ​​the anode region, thereby improving the forward performance under the same chip area, including reducing the forward on-resistance, increasing the maximum on-current, etc.

[0112] In addition, the embodiment of the present invention can also reduce the chip area. Under the condition of the same voltage and current characteristics, a smaller chip area can be used for implementation.

[0113] The manufacturing process flow of the embodiment of the present invention is fully compatible with the existing general power device FRD process, and the solution is easy to implement.

[0114] The manufacturing method of the fast recovery diode according to the embodiment of the present invention comprises the following steps:

[0115] Step 1: Figure 2A As shown, a semiconductor substrate 201 heavily doped with a first conductivity type is provided. The semiconductor substrate 201 serves as a first electrode region. A first epitaxial layer 202 lightly doped with a first conductivity type is formed on the top surface of the semiconductor substrate 201 .

[0116] Step 2: The fast recovery diode is divided into an active area 201a and a terminal area 201b, and the terminal area 201b surrounds the active area 201a. A second conductive type heavily doped ion implantation process is used to form a plurality of implantation area graphic structures in the active area 201a. The implantation area graphic structures are arranged in two dimensions in the active area 201a, and the bottom surfaces of adjacent implantation area graphic structures are located at different depths in the first epitaxial layer 202.

[0117] In the method of the embodiment of the present invention, the injection region pattern structure is distinguished according to the depth position of the bottom surface, and the injection region pattern structure includes at least two types, that is, it can be set to two, three or even more types according to needs. In some preferred embodiments, the injection region pattern structure adopts two types, namely the first injection region pattern structure 203a and the second injection region pattern structure 203b.

[0118] like Figure 2B As shown, in the embodiment method of the present invention, in the top view, each first injection area graphic structure 203a and each second injection area graphic structure 203b are in the shape of strips; the two-dimensional arrangement structure of the first injection area graphic structure 203a and the second injection area graphic structure 203b is: along the width direction of each first injection area graphic structure 203a, each first injection area graphic structure 203a and each second injection area graphic structure 203b are arranged alternately in parallel.

[0119] In some embodiments, the method can also be: in the top view, each first injection region graphic structure 203a and each second injection region graphic structure 203b are polygonal. More preferably, the polygon of each first injection region graphic structure 203a includes a square, and the polygon of each second injection region graphic structure 203b includes a square. The two-dimensional arrangement structure of the first injection region graphic structure 203a and the second injection region graphic structure 203b is:

[0120] The first implantation region pattern structures 203 a and the second implantation region pattern structures 203 b are arranged in a row structure and a column structure.

[0121] In each row structure, each first implantation region pattern structure 203 a and each second implantation region pattern structure 203 b are aligned and arranged alternately.

[0122] In each column structure, each first implantation region pattern structure 203 a and each second implantation region pattern structure 203 b are aligned and arranged alternately.

[0123] Step three, perform annealing and diffusion to connect the graphic structures of the injection regions to form a second electrode region 203. A PN main junction is formed by the second electrode region 203 and the first epitaxial layer 202. The junction interface of the PN main junction is a two-dimensional periodically distributed curved surface, and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer 202 of the active region 201a, so as to increase the power density of the fast recovery diode.

[0124] The structure of the curved surface of the PN main junction interface ensures that the breakdown voltage at each position of the curved surface of the PN main junction interface is greater than the breakdown voltage of the PN main junction at the edge of the active region 201a and the terminal structure of the terminal region 201b.

[0125] like FIG. 3A to FIG. 3E , which is a schematic diagram of the device structure in each step of the method for manufacturing a fast recovery diode according to the first preferred embodiment of the present invention; the method for manufacturing a fast recovery diode according to the first preferred embodiment of the present invention comprises the following steps:

[0126] Step 1: Figure 3A As shown, a semiconductor substrate 201 heavily doped with a first conductivity type is provided. The semiconductor substrate 201 serves as a first electrode region. A first epitaxial layer 202 lightly doped with a first conductivity type is formed on the top surface of the semiconductor substrate 201 . Figure 3A Only Figure 2A A schematic diagram of the structure in the corresponding active area 201a.

[0127] In some embodiments, the resistivity of the first epitaxial layer 202 is 50 ohm·cm to 90 ohm·cm.

[0128] Step 2: The fast recovery diode is divided into an active area 201a and a terminal area 201b, and the terminal area 201b surrounds the active area 201a. A second conductive type heavily doped ion implantation process is used to form a plurality of implantation area graphic structures in the active area 201a. The implantation area graphic structures are arranged in two dimensions in the active area 201a, and the bottom surfaces of adjacent implantation area graphic structures are located at different depths in the first epitaxial layer 202.

[0129] In the method of the first preferred embodiment of the present invention, two types of implantation region pattern structures are used, namely, a first implantation region pattern structure 203a and a second implantation region pattern structure 203b.

[0130] In step 2, the first implantation region graphic structure 203 a and the second implantation region graphic structure 203 b are simultaneously formed using the same first ion implantation process 304 . The first ion implantation process 304 passes through the first implantation mask layer 301 and enters the surface region of the first epitaxial layer 202 .

[0131] Before performing the first ion implantation process 304, the method further includes:

[0132] The first injection mask layer 301 is subjected to a patterning definition process, so that the first injection mask layer 301 has different thicknesses in the first injection region pattern structure 203a and the second injection region pattern structure 203b, and the depth positions of the bottom surfaces of the first injection region pattern structure 203a and the second injection region pattern structure 203b are defined by the first injection mask layer 301 with different thicknesses. The step of performing the patterning definition process on the first injection mask layer 301 includes the following sub-steps:

[0133] like Figure 3A As shown, a first implantation mask sublayer 301a is grown.

[0134] like Figure 3A As shown, a first hard mask layer 302 is formed on the surface of the first implantation mask sublayer 301a.

[0135] like Figure 3B As shown, photolithography is performed to form a photoresist pattern 302 to open one of the formation regions of the first implantation region pattern structure 203a and the second implantation region pattern structure 203b and to cover the other of the formation regions of the first implantation region pattern structure 203a and the second implantation region pattern structure 203b.

[0136] like Figure 3C As shown, etching is performed to remove the first hard mask layer 302 in the open area and the first implantation mask sublayer 301 a at the bottom.

[0137] like Figure 3C As shown, a second implantation mask sublayer 301 b is grown in the opened region, and the thickness of the second implantation mask sublayer 301 b is different from the thickness of the first implantation mask sublayer 301 a .

[0138] like Figure 3D As shown, the first hard mask layer 302 is removed, and the first implantation mask layer 301 is composed of the first implantation mask sublayer 301a and the second implantation mask sublayer 301b.

[0139] In some embodiments, the materials of the first implantation mask sublayer 301a and the second implantation mask sublayer 301b are both oxide layers. The material of the first hard mask layer 302 is silicon nitride or silicon oxynitride.

[0140] In some embodiment methods, the thickness of the first implantation mask sublayer 301a is 40 nm to 60 nm; the thickness of the second implantation mask sublayer 301b is 10 nm to 30 nm.

[0141] Afterwards, if Figure 3D As shown, the first ion implantation process 304 is performed. Figure 3D As shown, the second injection region graphic structure 203b is formed by the first ion injection process 304 through the thicker first injection mask sublayer 301a, and the first injection region graphic structure 203a is formed by the first ion injection process 304 through the thinner second injection mask sublayer 301b, so the depth position of the bottom surface of the formed second injection region graphic structure 203b is higher than the depth position of the bottom surface of the first injection region graphic structure 203a.

[0142] In some example methods, the process conditions of the first ion implantation process 304 include:

[0143] The injection energy is 60keV~100keV, and the injection dose is 1E13cm -2 ~5E13cm -2 .

[0144] Then, proceed to step 3, such as Figure 3E As shown, annealing and diffusion are performed to connect the graphic structures of the injection regions to form a second electrode region 203. A PN main junction is formed by the second electrode region 203 and the first epitaxial layer 202. The junction interface of the PN main junction is a two-dimensional periodically distributed curved surface, and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer 202 of the active region 201a, so as to increase the power density of the fast recovery diode.

[0145] In some embodiments, the annealing diffusion temperature is 1000°C to 1200°C.

[0146] After that, it also includes:

[0147] The first implantation mask layer 301 is removed.

[0148] A second metal electrode 207 a composed of a front metal layer 207 is formed on the top surface of the second electrode region 203 .

[0149] like FIG. 4A to FIG. 4G , which is a schematic diagram of the device structure in each step of the method for manufacturing a fast recovery diode according to the second preferred embodiment of the present invention; the method for manufacturing a fast recovery diode according to the second preferred embodiment of the present invention comprises the following steps:

[0150] Step 1: Figure 4AAs shown, a semiconductor substrate 201 heavily doped with a first conductivity type is provided. The semiconductor substrate 201 serves as a first electrode region. A first epitaxial layer 202 lightly doped with a first conductivity type is formed on the top surface of the semiconductor substrate 201 . Figure 4A Only Figure 2A A schematic diagram of the structure in the corresponding active area 201a.

[0151] In some embodiments, the resistivity of the first epitaxial layer 202 is 50 ohm·cm to 90 ohm·cm.

[0152] Step 2: The fast recovery diode is divided into an active area 201a and a terminal area 201b, and the terminal area 201b surrounds the active area 201a. A second conductive type heavily doped ion implantation process is used to form a plurality of implantation area graphic structures in the active area 201a. The implantation area graphic structures are arranged in two dimensions in the active area 201a, and the bottom surfaces of adjacent implantation area graphic structures are located at different depths in the first epitaxial layer 202.

[0153] In the method of the second preferred embodiment of the present invention, two types of implantation region pattern structures are used, namely, a first implantation region pattern structure 203a and a second implantation region pattern structure 203b.

[0154] In step 2, the first implantation region graphic structure 203 a and the second implantation region graphic structure 203 b are simultaneously formed using the same first ion implantation process 404 . The first ion implantation process 404 passes through the first implantation mask layer 403 and enters the surface region of the first epitaxial layer 202 .

[0155] Before performing the first ion implantation process 404, the method further includes:

[0156] The top surface of the first epitaxial layer 202 of the active area 201a is subjected to a graphic definition process, so that the positions of the top surface of the first epitaxial layer 202 corresponding to the first injection region graphic structure 203a and the second injection region graphic structure 203b are different, and the depth positions of the bottom surfaces of the first injection region graphic structure 203a and the second injection region graphic structure 203b are defined by the different positions of the top surface of the first epitaxial layer 202. The step of performing a graphic definition process on the top surface of the first epitaxial layer 202 of the active area 201a includes the following sub-steps:

[0157] like Figure 4A As shown, a second hard mask layer 401 is formed on the top surface of the first epitaxial layer 202 .

[0158] like Figure 4BAs shown, photolithography is performed to form a photoresist pattern 402 to open one of the formation regions of the first implantation region pattern structure 203a and the second implantation region pattern structure 203b and to cover the other of the formation regions of the first implantation region pattern structure 203a and the second implantation region pattern structure 203b.

[0159] like Figure 4B As shown, etching is performed to remove the second hard mask layer 401 in the open area and to lower the top surface of the bottom first epitaxial layer 202 .

[0160] like Figure 4C As shown, the photoresist pattern 402 and the second hard mask layer 401 are removed.

[0161] like Figure 4C As shown, a first implantation mask layer 403 is formed. In some embodiments, the material of the first implantation mask layer 403 is an oxide layer. The material of the second hard mask layer 401 is an oxide layer or silicon nitride or silicon oxynitride.

[0162] Afterwards, if Figure 4D As shown, the first ion implantation process 404 is performed. Figure 4D As shown, the thickness of the first injection mask layer 403 passed through by the first ion injection process 404 is the same, and the depth at which the injected ions pass through the first epitaxial layer 202 is the same, that is, the injection depth is the same, but because the top surfaces of the first epitaxial layer 202 in different areas are different, the depth positions of the bottom surfaces of the injection area graphic structures in different areas are different. Figure 4D In the embodiment, the first implantation region pattern structure 203 a is located in a region where the top surface of the first epitaxial layer 202 is lower, and the second implantation region pattern structure 203 b is located in a region where the top surface of the first epitaxial layer 202 is higher.

[0163] Then, proceed to step 3, such as Figure 4E As shown, annealing and diffusion are performed to connect the graphic structures of the injection regions to form a second electrode region 203. A PN main junction is formed by the second electrode region 203 and the first epitaxial layer 202. The junction interface of the PN main junction is a two-dimensional periodically distributed curved surface, and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer 202 of the active region 201a, so as to increase the power density of the fast recovery diode.

[0164] In some embodiments, the annealing diffusion temperature is 1000°C to 1200°C.

[0165] After annealing and diffusion, it also includes:

[0166] like Figure 4EAs shown, photolithography is performed to form a photoresist pattern 405 to cover one of the formation regions of the first injection region pattern structure 203a and the second injection region pattern structure 203b and to open the other of the formation regions of the first injection region pattern structure 203a and the second injection region pattern structure 203b. Figure 4E and Figure 4B As shown, the covered areas and open areas of the photoresist patterns 405 and 402 are exactly opposite. In some embodiment methods, the mask corresponding to the photoresist pattern 405 can use the mask corresponding to the photoresist pattern 402, but the polarity of the photoresist materials of the photoresist pattern 405 and the photoresist pattern 402 is opposite, for example: the photoresist pattern 402 is a positive photoresist, and the photoresist pattern 405 is a negative photoresist; or, the photoresist pattern 402 is a negative photoresist, and the photoresist pattern 405 is a positive photoresist.

[0167] like Figure 4F As shown, etching is performed to lower the top surface of the first epitaxial layer 202 in the open area and adjust the positions of the top surfaces of the first epitaxial layer 202 corresponding to the first implantation region pattern structure 203a and the second implantation region pattern structure 203b to be the same.

[0168] After that, it also includes:

[0169] A sacrificial oxide layer 406 is formed and then removed.

[0170] A second metal electrode 207 a composed of a front metal layer 207 is formed on the top surface of the second electrode region 203 .

[0171] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A fast recovery diode, characterized in that: include: A semiconductor substrate heavily doped with a first conductivity type, the semiconductor substrate serving as a first electrode region; A first epitaxial layer lightly doped with a first conductivity type is formed on the top surface of the semiconductor substrate; The fast recovery diode is divided into an active region and a terminal region, and the terminal region surrounds the active region; A PN main junction formed by a second electrode region and the first epitaxial layer is formed in the active region; The second electrode region includes a plurality of heavily doped injection region graphic structures of the second conductivity type, wherein the injection region graphic structures are arranged two-dimensionally in the active region, each adjacent injection region graphic structure is laterally connected, and the bottom surface of each adjacent injection region graphic structure is located at a different depth in the first epitaxial layer, and the junction interface of the PN main junction is a two-dimensionally periodically distributed curved surface and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer in the active region, so as to increase the power density of the fast recovery diode.

2. The fast recovery diode according to claim 1, characterized in that: The structure of the curved surface of the junction interface of the PN main junction ensures that the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction is greater than the breakdown voltage of the PN main junction at the edge of the active region and the terminal structure of the terminal region.

3. The fast recovery diode according to claim 1, characterized in that: The injection region graphic structures include at least two types, namely a first injection region graphic structure and a second injection region graphic structure; In a top view, each of the first injection region graphic structures and each of the second injection region graphic structures are in a strip shape; the two-dimensional arrangement structure of the first injection region graphic structures and the second injection region graphic structures is: in a width direction of each of the first injection region graphic structures, each of the first injection region graphic structures and each of the second injection region graphic structures are arranged alternately in parallel; Alternatively, in a top view, each of the first injection region graphic structures and each of the second injection region graphic structures are polygonal; and the two-dimensional arrangement structure of the first injection region graphic structure and the second injection region graphic structure is: The first injection region pattern structures and the second injection region pattern structures are arranged in a row structure and a column structure; In each of the row structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately; In each of the column structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately.

4. The fast recovery diode according to claim 3, characterized in that: The polygon of each of the first injection region graphic structures includes a square, and the polygon of each of the second injection region graphic structures includes a square.

5. The fast recovery diode according to any one of claims 1 to 4, characterized in that: The first conductivity type is N type, the second conductivity type is P type, the first electrode region is a cathode region, and the second electrode region is an anode region; or, the first conductivity type is P type, the second conductivity type is N type, the first electrode region is an anode region, and the second electrode region is a cathode region.

6. A method for manufacturing a fast recovery diode, characterized in that: The steps include: Step 1: providing a semiconductor substrate heavily doped with a first conductivity type, the semiconductor substrate serving as a first electrode region, and forming a first epitaxial layer lightly doped with a first conductivity type on a top surface of the semiconductor substrate; Step 2, the fast recovery diode is divided into an active area and a terminal area, the terminal area surrounds the active area; a plurality of implantation area graphic structures are formed in the active area by a second conductivity type heavily doped ion implantation process, the implantation area graphic structures are arranged two-dimensionally in the active area, and the bottom surfaces of adjacent implantation area graphic structures are located at different depths in the first epitaxial layer; Step three, perform annealing and diffusion to connect the graphic structures of the injection regions to form a second electrode region, and a PN main junction formed by the second electrode region and the first epitaxial layer, wherein the junction interface of the PN main junction is a two-dimensional periodically distributed curved surface and the area of ​​the junction interface of the PN main junction is larger than the top surface area of ​​the first epitaxial layer of the active region, so as to increase the power density of the fast recovery diode.

7. The method for manufacturing a fast recovery diode according to claim 6, wherein: The structure of the curved surface of the junction interface of the PN main junction ensures that the breakdown voltage at each position of the curved surface of the junction interface of the PN main junction is greater than the breakdown voltage of the PN main junction at the edge of the active region and the terminal structure of the terminal region.

8. The method for manufacturing a fast recovery diode according to claim 6, wherein: The injection region graphic structures include at least two types, namely a first injection region graphic structure and a second injection region graphic structure; In step 2, the first implantation region pattern structure and the second implantation region pattern structure are simultaneously formed by using the same first ion implantation process, and the first ion implantation process passes through the first implantation mask layer and enters the surface area of ​​the first epitaxial layer; Before performing the first ion implantation process, the method further includes: Performing a graphic definition process on the first injection mask layer so that the first injection mask layer has different thicknesses in the first injection region graphic structure and the second injection region graphic structure, and the first injection mask layer with different thicknesses defines the depth positions of the bottom surfaces of the first injection region graphic structure and the second injection region graphic structure; Alternatively, before performing the first ion implantation process, the method further includes: A top surface of the first epitaxial layer of the active region is subjected to a graphic definition process, so that the positions of the top surface of the first epitaxial layer corresponding to the first implantation region graphic structure and the second implantation region graphic structure are different, and the depth positions of the bottom surfaces of the first implantation region graphic structure and the second implantation region graphic structure are defined by the different positions of the top surface of the first epitaxial layer; after the first ion implantation process, the method further includes: The positions of the top surfaces of the first epitaxial layer corresponding to the first implantation region pattern structure and the second implantation region pattern structure are adjusted to be the same.

9. The method for manufacturing a fast recovery diode according to claim 8, characterized in that: The step of performing a patterning process on the first implantation mask layer comprises the following sub-steps: growing a first implantation mask sublayer; forming a first hard mask layer on a surface of the first implantation mask sublayer; Performing photolithography to open one of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure and to cover the other of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure; Performing etching to remove the first hard mask layer in the open area and the first implantation mask sublayer at the bottom; growing a second implantation mask sublayer in the opened region, wherein the thickness of the second implantation mask sublayer is different from the thickness of the first implantation mask sublayer; The first hard mask layer is removed, and the first implantation mask layer is formed by the first implantation mask sublayer and the second implantation mask sublayer.

10. The method for manufacturing a fast recovery diode according to claim 8, wherein: The step of performing a patterning process on the top surface of the first epitaxial layer of the active region comprises the following sub-steps: forming a second hard mask layer on a top surface of the first epitaxial layer; Performing photolithography to open one of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure and to cover the other of the formation regions of the first implantation region pattern structure and the second implantation region pattern structure; Performing etching to remove the second hard mask layer in the open area and lower the top surface of the first epitaxial layer at the bottom; removing the second hard mask layer; forming the first implantation mask layer; After the annealing and diffusion, the method further comprises: Performing photolithography to cover one of the formation regions of the first injection region pattern structure and the second injection region pattern structure and to open the other of the formation regions of the first injection region pattern structure and the second injection region pattern structure; Etching is performed to lower the top surface of the first epitaxial layer in the open area and adjust the positions of the top surfaces of the first epitaxial layer corresponding to the first implantation region pattern structure and the second implantation region pattern structure to be the same.

11. The method for manufacturing a fast recovery diode according to claim 8, wherein: In a top view, each of the first injection region graphic structures and each of the second injection region graphic structures are in a strip shape; the two-dimensional arrangement structure of the first injection region graphic structures and the second injection region graphic structures is: in a width direction of each of the first injection region graphic structures, each of the first injection region graphic structures and each of the second injection region graphic structures are arranged alternately in parallel; Alternatively, in a top view, each of the first injection region graphic structures and each of the second injection region graphic structures are polygonal; and the two-dimensional arrangement structure of the first injection region graphic structure and the second injection region graphic structure is: The first injection region pattern structures and the second injection region pattern structures are arranged in a row structure and a column structure; In each of the row structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately; In each of the column structures, each of the first injection region pattern structures and each of the second injection region pattern structures are aligned and arranged alternately.

12. The method for manufacturing a fast recovery diode according to claim 11, characterized in that: The polygon of each of the first injection region graphic structures includes a square, and the polygon of each of the second injection region graphic structures includes a square.

13. The method for manufacturing a fast recovery diode according to claim 9, characterized in that: The thickness of the first injection mask sublayer is 40 nm to 60 nm; the thickness of the second injection mask sublayer is 10 nm to 30 nm.

14. The method for manufacturing a fast recovery diode according to claim 8, wherein: The process conditions of the first ion implantation process include: The injection energy is 60keV~100keV, and the injection dose is 1E13cm -2 ~5E13cm -2 .

15. The method for manufacturing a fast recovery diode according to claim 6, wherein: In step three, the annealing diffusion temperature is 1000°C to 1200°C.

16. The method for manufacturing a fast recovery diode according to claim 6, wherein: The resistivity of the first epitaxial layer is 50 ohm·cm to 90 ohm·cm.

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