SFSCR device, SFSCR device stacking serial connection structure and SFSCR device stacking packaging structure

Abstract

The invention provides an SFSCR device, an SFSCR device stacking series connection structure and an SFSCR device stacking packaging structure, and belongs to the technical field of stacking series connection and stacking packaging. The SFSCR device comprises a P-type substrate, a P-type deep well region, an N-type well region, a P-type well region, a first N + region, a second N + region, a first P + region, a second P + region, a floating N + region, a floating P + region, an anode ZP region and a cathode ZP region. The SFSCR device stacking series structure comprises two or more SFSCR devices and a P-type isolation deep well region, the SFSCR device stack packaging structure comprises two or more SFSCR device stack series connection structures, a substrate, an upper-layer adhesive, a lower-layer adhesive and a transition gasket. On the basis that the area is not increased, the performance of the SFSCR device structure is further improved in a smaller space, small occupied area, high maintaining voltage and high failure current are achieved, the performance of the device in unit area is improved, and excellent area performance efficiency is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of electronic science and technology, mainly to the field of stacking series technology and stacking packaging technology, and in particular to an SFSCR device, an SFSCR device stacking series structure and an SFSCR device stacking packaging structure, which have the characteristics of small area, high voltage and high current. Background Art

[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of people's daily life. However, such common electrical phenomena are a fatal threat to precision integrated circuits. Surge / transient voltage refers to the high voltage or current that suddenly appears in the circuit and exceeds the normal state. It is characterized by a short occurrence time and very large instantaneous energy. Surge is very destructive to electronic components and integrated circuits. It can induce malfunction of logic circuits at the least, and cause serious thermal effects such as secondary breakdown of transistors and latch effect of complementary metal oxide semiconductors (CMOS) to make devices or integrated circuits fail. Surge usually has two random sources. The first is the instability of the power grid, such as sudden switching, sudden startup of capacitive or inductive loads, hot plugging of related equipment, and unstable operation of related power supplies. The second is sudden interference from the outside, such as lightning and electrostatic discharge.

[0003] With the improvement of integrated circuit manufacturing technology, its minimum line width has dropped to the sub-micron or even nanometer level. While improving chip performance, its ability to resist ESD strikes has also been greatly reduced, so electrostatic damage is more serious. Most of the ESD can cause non-fatal damage to integrated circuits, thereby reducing the life and reliability of integrated circuits, and further causing degradation of system functions, which is a great obstacle to achieving large-scale high-reliability integration.

[0004] TVS devices are an important semiconductor protection device. When turned on, they have extremely low resistance values. They can absorb up to several kilowatts of transient pulse power and clamp the voltage of the port at a safer preset value, thereby protecting the corresponding circuit from damage or even irreversible damage caused by transient voltage pulses or current surges. TVS devices have the characteristics of fast response speed, low leakage, high transient power, and small size. They are currently widely used in overvoltage protection in various fields such as electromechanical systems, power supply equipment, electromagnetic interference suppression, input and output interfaces, communication equipment, and relays.

[0005] In traditional designs, to improve the holding voltage, failure current and specific on-resistance of SCR devices, it is often necessary to increase the area of ​​the device. However, in many practical applications, such as portable electronic devices and high-density integrated circuits, the available area of ​​the device is very limited, and increasing the area is not a feasible solution.

[0006] When improving the performance of SCR devices, existing technical means often fail to take into account multiple key characteristics such as maintenance voltage, failure current and specific on-resistance at the same time. Even if there are improvements in some aspects, other performance indicators may decline or the cost may increase significantly. Summary of the invention

[0007] The present invention aims to provide a SFSCR device, a stacked series structure of SFSCR devices, and a stacked packaging structure of SFSCR devices, which have the characteristics of small area, high voltage, and high current. Without increasing the device area, the stacked series technology and the stacked packaging technology are used to further improve the SFSCR device's maintenance voltage, failure current, and specific on-resistance characteristics under the same area, increase the performance of the SFSCR device under a unit area, and achieve excellent area performance efficiency. This is to solve the technical problem that it is often difficult to simultaneously take into account multiple key characteristics such as maintenance voltage, failure current, and specific on-resistance when improving the performance of SCR devices in the prior art, and it is often necessary to increase the device area.

[0008] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0009] An SFSCR device, the device comprising: a P-type substrate, a P-type deep well region, an N-type well region, a P-type well region, a first N+ region, a second N+ region, a first P+ region, a second P+ region, a floating N+ region, a floating P+ region, an anode ZP region, and a cathode ZP region;

[0010] The first N+ region and the first P+ region are interconnected by wires to form an anode of the device, and the second N+ region, the second P+ region and the cathode ZP region are interconnected by wires to form a cathode of the device.

[0011] Furthermore, the P-type deep well region is located inside the P-type substrate, the upper edge of the P-type deep well region is tangent to the upper edge of the P-type substrate, and the lower edge of the P-type deep well region is higher than the lower edge of the P-type substrate;

[0012] The N-type well region and the P-type well region are located inside the P-type deep well region, the upper edge of the N-type well region and the upper edge of the P-type well region are both tangent to the upper edge of the P-type deep well region, and the lower edge of the N-type well region and the lower edge of the P-type well region are both higher than the lower edge of the P-type deep well region; wherein the N-type well region and the P-type well region are adjacent, the N-type well region is located on the left side of the P-type well region, and the right edge of the N-type well region is tangent to the left edge of the P-type well region;

[0013] The first N+ region and the first P+ region are located inside the N-type well region, the upper edge of the first N+ region and the upper edge of the first P+ region are both tangent to the upper edge of the N-type well region, and the lower edge of the first N+ region and the lower edge of the first P+ region are both higher than the lower edge of the N-type well region; wherein the first N+ region is located on the left side of the first P+ region, and the right edge of the first N+ region is 2um to 5um away from the left edge of the first P+ region;

[0014] The second N+ region and the second P+ region are located inside the P-type well region, the upper edge of the second N+ region and the upper edge of the second P+ region are both tangent to the upper edge of the P-type well region, and the lower edge of the second N+ region and the lower edge of the second P+ region are both higher than the lower edge of the P-type well region; wherein the second N+ region is located on the left side of the second P+ region, and the right edge of the second N+ region is 2um to 5um away from the left edge of the second P+ region;

[0015] The floating N+ region straddles the boundary between the N-type well region and the P-type well region, is located inside the N-type well region and the P-type well region, the upper edge of the floating N+ region is tangent to the upper edge of the N-type well region and the upper edge of the P-type well region, and the lower edge of the floating N+ region is higher than the lower edge of the N-type well region and the lower edge of the P-type well region; the floating N+ region is adjacent to the first P+ region, is located on the right side of the first P+ region, and the left edge of the floating N+ region is tangent to the right edge of the first P+ region;

[0016] The floating P+ region is located inside the P-type well region, the upper edge of the floating P+ region is tangent to the upper edge of the P-type well region, and the lower edge of the floating P+ region is higher than the lower edge of the P-type well region; the floating P+ region is located on the left side of the second N+ region, and the right edge of the floating P+ region is not more than 10um away from the left edge of the second N+ region;

[0017] The anode ZP region is located inside the N-type well region, the upper edge of the anode ZP region is tangent to the upper edge of the N-type well region, and the lower edge is higher than the lower edge of the N-type well region; the anode ZP region wraps the first P+ region, the upper edge of the anode ZP region is tangent to the upper edge of the first P+ region, the right edge is tangent to the right edge of the first P+ region, and the left edge is tangent to the left edge of the first P+ region; the lower edge of the anode ZP region is lower than the lower edge of the first P+ region, exceeding a certain interval of 0.5um to 5um; the anode ZP region is adjacent to the floating N+ region, located on the left side of the floating N+ region, and the right edge of the anode ZP region is tangent to the left edge of the floating N+ region;

[0018] The cathode ZP region is located inside the P-type well region, the upper edge of the cathode ZP region is tangent to the upper edge of the P-type well region, and the lower edge is higher than the lower edge of the P-type well region; the cathode ZP region is adjacent to the second N+ region, located on the left side of the second N+ region, and the right edge of the cathode ZP region is tangent to the left edge of the second N+ region; the cathode ZP region wraps a part of the floating P+ region, and the left edge of the cathode ZP region is located inside the floating P+ region; the lower edge of the cathode ZP region is lower than the lower edges of the floating P+ region and the second N+ region, exceeding a certain interval of 0.5um to 5um.

[0019] The present invention also provides a SFSCR device stacked series structure, comprising two SFSCR devices and a P-type isolation deep well region; the two SFSCR devices constitute a basic structural unit of the SFSCR device stacked series structure.

[0020] Furthermore, the two SFSCR devices are a first SFSCR device and a second SFSCR device; the first SFSCR device and the second SFSCR device are located on the same P-type substrate; wherein the first SFSCR device is on the left side of the second SFSCR device, and the distance between them is 5um to 30um.

[0021] The P-type isolation deep well region is located inside the P-type substrate, the upper edge of the P-type isolation deep well region is tangent to the upper edge of the P-type substrate, and the lower edge is higher than the lower edge of the P-type substrate; the P-type isolation deep well region is located between the first SFSCR device and the second SFSCR device, the left edge is tangent to the right edge of the first SFSCR device, and the right edge is tangent to the left edge of the second SFSCR device.

[0022] The cathode of the first SFSCR device and the anode of the second SFSCR device are connected in series through wire interconnection.

[0023] Further, a P-type isolation deep well region is continuously added to the right side of the second SFSCR device, and an SFSCR device is continuously added to the right side of the P-type isolation deep well region, and the cathode of the second SFSCR device is connected to the anode of the newly added SFSCR device through a wire to realize the series connection of the first SFSCR device, the second SFSCR device and the newly added SFSCR device; and this is repeated to realize a stacked series structure of any number of SFSCR devices.

[0024] The present invention also provides a SFSCR device stacking packaging structure, comprising two SFSCR device stacking series structures, a substrate, an upper adhesive, a lower adhesive and a transition gasket; the two SFSCR device stacking series structures constitute the basic structural unit of the SFSCR device stacking packaging structure.

[0025] Furthermore, the two SFSCR device stacked series structures are a first SFSCR device stacked series structure and a second SFSCR device stacked series structure; the first SFSCR device stacked series structure and the second SFSCR device stacked series structure are located above the substrate; wherein the lower edge of the second SFSCR device stacked series structure is tangent to the upper edge of the substrate, and the whole is located in the middle of the substrate;

[0026] The upper adhesive, the lower adhesive and the transition gasket are located between the first SFSCR device stacked series structure and the second SFSCR device stacked series structure, and the order from top to bottom is the first SFSCR device stacked series structure, the upper adhesive, the transition gasket, the lower adhesive and the second SFSCR device stacked series structure.

[0027] The anode and the cathode of the first SFSCR device stacked series structure and the second SFSCR device stacked series structure are respectively connected to the substrate through metal wires.

[0028] Furthermore, a lower layer of adhesive is continuously applied on top of the second SFSCR device stacked series structure, a transition gasket is inserted, an upper layer of adhesive is applied, and then a new SFSCR device stacked series structure is placed thereon, and its anode and cathode are connected to the substrate through metal wires, thereby realizing the stacking packaging of the first SFSCR device stacked series structure, the second SFSCR device stacked series structure and the new SFSCR device stacked series structure; this process is repeated to realize any number of SFSCR device stacked packaging structures.

[0029] Compared with the prior art, the present invention has the following beneficial technical effects:

[0030] 1) The SFSCR device of the present invention introduces a floating N+ region and a floating P+ region, and introduces a Zener injection ZP region at the anode and cathode using a new Zener injection technology, thereby successfully suppressing the snapback phenomenon of the device.

[0031] 2) The present invention utilizes stacked series technology and stacked packaging technology. On the basis of not increasing the device area, by designing a stacked structure of SFSCR devices with an additional Zener injection ZP region, an SFSCR device stacking structure is proposed, which achieves excellent holding voltage, failure current and specific on-resistance characteristics in a small area, increases the performance of the device per unit area, and achieves excellent area-performance efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0033] Figure 1 The figure is a schematic diagram of the structure of the SFSCR device involved in the present invention.

[0034] Figure 2 This is a schematic diagram of the stacked series structure of the SFSCR devices proposed in the present invention.

[0035] Figure 3 This is a schematic diagram of the stacked packaging structure of the SFSCR device proposed in the present invention.

[0036] Figure 4 This is a schematic diagram of the structure of a bidirectional SFSCR device extended from the present invention.

[0037] Figure 5 This is a schematic diagram of a bidirectional SFSCR device stacked in series structure extended from the present invention.

[0038] Markings in the figure: 100-P-type substrate, 101-P-type deep well region, 111-N-type well region, 121-P-type well region, 131-first N+ region, 132-second N+ region, 141-first P+ region, 142-second P+ region, 151-floating N+ region, 161-floating P+ region, 171-anode ZP region, 172-cathode ZP region, 181-P-type isolation deep well region, 201-N-type deep well region , 211-first PW region, 212-second PW region, 251-NW region, 271-N-type isolation deep well region, 301-substrate, 311-upper layer adhesive, 312-lower layer adhesive, 321-transition gasket, 001-first SFSCR device, 002-second SFSCR device, 011-first SFSCR device stacked series structure, 012-second SFSCR device stacked series structure. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Embodiment 1:

[0041] Figure 1 The SFSCR device structure integrated in the SFSCR (Snapback Free Silicon Controlled Rectifier) ​​device stacking structure proposed in the present invention introduces a floating N+ region and a floating P+ region compared to a traditional structure, and introduces a P-type Zener injection ZP (Zener P-type) region at the anode and cathode using a new Zener injection technology, thereby successfully suppressing the snapback phenomenon of the device.

[0042] like Figure 1As shown, the present embodiment provides an SFSCR device, which includes: a P-type substrate 100, a P-type deep well region 101, an N-type well region 111, a P-type well region 121, a first N+ region 131, a second N+ region 132, a first P+ region 141, a second P+ region 142, a floating N+ region 151, a floating P+ region 161, an anode ZP region 171, and a cathode ZP region 172.

[0043] Specific:

[0044] The P-type deep well region 101 is located inside the P-type substrate 100 , the upper edge of the P-type deep well region 101 is tangent to the upper edge of the P-type substrate 100 , and the lower edge of the P-type deep well region 101 is higher than the lower edge of the P-type substrate 100 .

[0045] The N-type well region 111 and the P-type well region 121 are located inside the P-type deep well region 101, and the upper edges of the N-type well region 111 and the P-type well region 121 are both tangent to the upper edge of the P-type deep well region 101, and the lower edges of the N-type well region 111 and the P-type well region 121 are both higher than the lower edge of the P-type deep well region 101; wherein, the N-type well region 111 and the P-type well region 121 are adjacent, the N-type well region 111 is located on the left side of the P-type well region 121, and the right edge of the N-type well region 111 is tangent to the left edge of the P-type well region 121.

[0046] The first N+ region 131 and the first P+ region 141 are located inside the N-type well region 111, and the upper edge of the first N+ region 131 and the upper edge of the first P+ region 141 are both tangent to the upper edge of the N-type well region 111, and the lower edge of the first N+ region 131 and the lower edge of the first P+ region 141 are both higher than the lower edge of the N-type well region 111; wherein, the first N+ region 131 is located on the left side of the first P+ region 141, and the right edge of the first N+ region 131 is spaced 2um to 5um from the left edge of the first P+ region 141.

[0047] The second N+ region 132 and the second P+ region 142 are located inside the P-type well region 121, the upper edge of the second N+ region 132 and the upper edge of the second P+ region 142 are both tangent to the upper edge of the P-type well region 121, and the lower edge of the second N+ region 132 and the lower edge of the second P+ region 142 are both higher than the lower edge of the P-type well region 121; wherein, the second N+ region 132 is located on the left side of the second P+ region 142, and the right edge of the second N+ region 132 is 2um to 5um away from the left edge of the second P+ region 142.

[0048] The floating N+ region 151 spans the junction of the N-type well region 111 and the P-type well region 121, and is located inside the N-type well region 111 and the P-type well region 121. The upper edge of the floating N+ region 151 is tangent to the upper edge of the N-type well region 111 and the upper edge of the P-type well region 121, and the lower edge of the floating N+ region 151 is higher than the lower edge of the N-type well region 111 and the lower edge of the P-type well region 121. The floating N+ region 151 is adjacent to the first P+ region 141, and the floating N+ region 151 is located on the right side of the first P+ region 141. The left edge of the floating N+ region 151 is tangent to the right edge of the first P+ region 141.

[0049] The floating P+ region 161 is located inside the P-type well region 121, the upper edge of the floating P+ region 161 is tangent to the upper edge of the P-type well region 121, and the lower edge of the floating P+ region 161 is higher than the lower edge of the P-type well region 121; the floating P+ region 161 is located on the left side of the second N+ region 132, and the right edge of the floating P+ region 161 is no more than 10um away from the left edge of the second N+ region 132.

[0050] The anode ZP region 171 is located inside the N-type well region 111, the upper edge of the anode ZP region 171 is tangent to the upper edge of the N-type well region 111, and the lower edge of the anode ZP region 171 is higher than the lower edge of the N-type well region 111; the anode ZP region 171 wraps the first P+ region 141, the upper edge of the anode ZP region 171 is tangent to the upper edge of the first P+ region 141, the right edge of the anode ZP region 171 is tangent to the right edge of the first P+ region 141, and the left edge of the anode ZP region 171 is tangent to the left edge of the first P+ region 141; the lower edge of the anode ZP region 171 is lower than the lower edge of the first P+ region 141, exceeding a certain interval of 0.5um to 5um; the anode ZP region 171 is adjacent to the floating N+ region 151, the anode ZP region 171 is located on the left side of the floating N+ region 151, and the right edge of the anode ZP region 171 is tangent to the left edge of the floating N+ region 151.

[0051] The cathode ZP region 172 is located inside the P-type well region 121, the upper edge of the cathode ZP region 172 is tangent to the upper edge of the P-type well region 121, and the lower edge of the cathode ZP region 172 is higher than the lower edge of the P-type well region 121; the cathode ZP region 172 is adjacent to the second N+ region 132, the cathode ZP region 172 is located on the left side of the second N+ region 132, and the right edge of the cathode ZP region 172 is tangent to the left edge of the second N+ region 132; the cathode ZP region 172 wraps a portion of the floating P+ region 161, and the left edge of the cathode ZP region 172 is located inside the floating P+ region 161; the lower edge of the cathode ZP region 172 is lower than the lower edges of the floating P+ region 161 and the second N+ region 132, exceeding a certain interval of 0.5um to 5um.

[0052] The first N+ region 131 and the first P+ region 141 are interconnected by wires to form an anode of the device, and the second N+ region 132 , the second P+ region 142 and the cathode ZP region 172 are interconnected by wires to form a cathode of the device.

[0053] Figure 2 The stacked series structure of SFSCR devices proposed in the present invention utilizes stacked series technology to integrate two or more SFSCR devices on a silicon substrate and connect them in series, thereby realizing stacking of multiple devices and achieving better performance per unit area.

[0054] like Figure 2 As shown, this embodiment provides a method of combining two Figure 1 The SFSCR device stacked in series structure shown includes: a first SFSCR device 001, a second SFSCR device 002 and a P-type isolation deep well region 181; the first SFSCR device 001 and the second SFSCR device 002 are composed of a P-type substrate 100, a P-type deep well region 101, an N-type well region 111, a P-type well region 121, a first N+ region 131, a second N+ region 132, a first P+ region 141, a second P+ region 142, a floating N+ region 151, a floating P+ region 161, an anode ZP region 171, and a cathode ZP region 172.

[0055] The SFSCR device constitutes the basic structural unit of the SFSCR device stacked series structure.

[0056] Specific:

[0057] The first SFSCR device 001 and the second SFSCR device 002 are located on the same P-type substrate 100 ; wherein the first SFSCR device 001 is on the left side of the second SFSCR device 002 , and a certain distance is separated therebetween.

[0058] The P-type isolation deep well region 181 is located inside the P-type substrate 100, the upper edge of the P-type isolation deep well region 181 is tangent to the upper edge of the P-type substrate 100, and the lower edge of the P-type isolation deep well region 181 is higher than the lower edge of the P-type substrate 100; the P-type isolation deep well region 181 is located between the first SFSCR device 001 and the second SFSCR device 002, the left edge of the P-type isolation deep well region 181 is tangent to the right edge of the first SFSCR device 001, and the right edge of the P-type isolation deep well region 181 is tangent to the left edge of the second SFSCR device 002.

[0059] The cathode of the first SFSCR device 001 and the anode of the second SFSCR device 002 are connected in series through wire interconnection.

[0060] Figure 3 The stacked packaging structure of the SFSCR device proposed in the present invention can package two or even more SFSCR devices in series through stacked packaging technology, thereby achieving excellent chip area performance efficiency.

[0061] like Figure 3 As shown, this embodiment provides a method of combining two Figure 2 The SFSCR device stacking and packaging structure for stacking and packaging the SFSCR device stacking and series structure shown includes a first SFSCR device stacking and series structure 011 , a second SFSCR device stacking and series structure 012 , a substrate 301 , an upper adhesive 311 , a lower adhesive 312 and a transition gasket 321 .

[0062] The SFSCR device stacked series structure constitutes the basic structural unit of the SFSCR device stacked packaging structure.

[0063] Specific:

[0064] The first SFSCR device stacked series structure 011 and the second SFSCR device stacked series structure 012 are located above the substrate 301 ; wherein the lower edge of the second SFSCR device stacked series structure 012 is tangent to the upper edge of the substrate 301 , and the whole is located in the middle of the substrate 301 .

[0065] The upper adhesive 311, the lower adhesive 312 and the transition gasket 321 are located in the middle of the first SFSCR device stacked series structure 011 and the second SFSCR device stacked series structure 012, and the order from top to bottom is the first SFSCR device stacked series structure 011, the upper adhesive 311, the transition gasket 321, the lower adhesive 312 and the second SFSCR device stacked series structure 012.

[0066] The anodes and cathodes of the first SFSCR device stacked series structure 011 and the second SFSCR device stacked series structure 012 are respectively connected to the substrate 301 through metal wires.

[0067] Embodiment 2:

[0068] This embodiment provides a stacking and connecting of multiple Figure 1 The SFSCR device shown in Example 1 Figure 2In the figure, a structure of stacking two SFSCR devices in series is shown. In this embodiment, if higher device performance requirements are required, multiple SFSCR devices can be stacked in series by continuing to add a P-type isolation deep well region 181 to the right of the second SFSCR device 002, and continuing to add SFSCR devices to the right of the P-type isolation deep well region 181, and connecting the cathode of the former with the anode of the latter through a wire to achieve the series connection of the first SFSCR device 001, the second SFSCR device 002 and the newly added SFSCR device. Repeating this process can achieve any number of SFSCR device stacking and series connection structures to meet the performance requirements of different application scenarios.

[0069] Embodiment 3:

[0070] This embodiment provides a stacked package with multiple Figure 2 The SFSCR device stacking series structure shown in the embodiment 1 Figure 3 In the figure, a structure of stacking and packaging two SFSCR device stacked series structures is shown. In this embodiment, if higher chip performance requirements are required, multiple SFSCR device stacked series structures can be stacked and packaged, and the method is to continue to apply the lower layer of adhesive 312 on the second SFSCR device stacked series structure 012, insert the transition gasket 321, apply the upper layer of adhesive 311, and then place the new SFSCR device stacked series structure on it, and connect its anode and cathode to the substrate through metal wires, so as to achieve the stacking packaging of the first SFSCR device stacked series structure 011, the second SFSCR device stacked series structure 012 and the new SFSCR device stacked series structure. Repeating this process can achieve any number of SFSCR device stacked packaging structures to meet the performance requirements of different application scenarios.

[0071] Embodiment 4:

[0072] This embodiment provides a method for stacking and connecting multiple bidirectional SFSCR devices in series. Figure 5 As shown, the basic device structure unit stacked in series in this embodiment is Figure 1 Based on the SFSCR device structure shown in FIG. 1 , a bidirectional SFSCR device structure is obtained, and its structural schematic diagram is shown in FIG. Figure 4 shown.

[0073] The bidirectional SFSCR device structure includes a P-type substrate 100, an N-type deep well region 201, a first PW region 211, a second PW region 212, a first N+ region 131, a second N+ region 132, a first P+ region 141, a second P+ region 142, a floating N+ region 151, an NW region 251, an anode ZP region 171, and a cathode ZP region 172.

[0074] Specific:

[0075] The N-type deep well region 201 is located inside the P-type substrate 100 , the upper edge of the N-type deep well region 201 is tangent to the upper edge of the P-type substrate 100 , and the lower edge of the N-type deep well region 201 is higher than the lower edge of the P-type substrate 100 .

[0076] The first PW region 211 and the second PW region 212 are located inside the N-type deep well region 201, the upper edge of the first PW region 211 and the upper edge of the second PW region 212 are tangent to the upper edge of the N-type deep well region 201, and the lower edge of the first PW region 211 and the lower edge of the second PW region 212 are higher than the lower edge of the N-type deep well region 201; wherein the first PW region 211 is located on the left side of the second PW region 212.

[0077] The first P+ region 141 and the first N+ region 131 are located inside the first PW region 211, and the upper edge of the first P+ region 141 and the upper edge of the first N+ region 131 are both tangent to the upper edge of the first PW region 211, and the lower edge of the first P+ region 141 and the lower edge of the first N+ region 131 are both higher than the lower edge of the first PW region 211; wherein, the first P+ region 141 is located on the left side of the first N+ region 131, and the right edge of the first P+ region 141 is tangent to the left edge of the first N+ region 131.

[0078] The second P+ region 142 and the second N+ region 132 are located inside the second PW region 212, the upper edge of the second P+ region 142 and the upper edge of the second N+ region 132 are both tangent to the upper edge of the second PW region 212, and the lower edge of the second P+ region 142 and the lower edge of the second N+ region 132 are both higher than the lower edge of the second PW region 212; wherein, the second P+ region 142 is located on the right side of the second N+ region 132, and the left edge of the second P+ region 142 is tangent to the right edge of the second N+ region 132.

[0079] The NW region 251 is located inside the N-type deep well region 201 , and the left edge of the NW region 251 and the right edge of the NW region 251 are tangent to the right edge of the first PW region 211 and the left edge of the second PW region 212 respectively.

[0080] The floating N+ region 151 spans the junction of the NW region 251 and the first PW region 211 and the second PW region 212. The upper edge of the floating N+ region 151 is tangent to the upper edge of the first PW region 211 and the upper edge of the second PW region 212. The lower edge of the floating N+ region 151 is higher than the lower edge of the first PW region 211 and the lower edge of the second PW region 212.

[0081] Both anode ZP regions 171 are located inside the first PW region 211, the upper edge of the anode ZP region 171 is tangent to the upper edge of the first PW region 211, and the lower edge of the anode ZP region 171 is higher than the lower edge of the first PW region 211; the anode ZP region 171 on the left wraps the first P+ region 141, and the right edge of the anode ZP region 171 on the left is tangent to the right edge of the first P+ region 141; the left edge of the anode ZP region 171 on the right is tangent to the right edge of the first N+ region 131, and the right edge of the anode ZP region 171 on the right is located inside the floating N+ region 151.

[0082] Both cathode ZP regions 172 are located inside the second PW region 212, and the upper edges of the cathode ZP region 172 are tangent to the upper edges of the second PW region 212, and the lower edges of the cathode ZP region 172 are higher than the lower edge of the second PW region 212; the cathode ZP region 172 on the right wraps the second P+ region 142, and the left edge of the cathode ZP region 172 on the right is tangent to the left edge of the second P+ region 142; the right edge of the cathode ZP region 172 on the left is tangent to the left edge of the second N+ region 132, and the left edge of the cathode ZP region 172 on the left is located inside the floating N+ region 151.

[0083] The first P+ region 141 and the first N+ region 131 are interconnected by wires to form an anode of the device, and the second P+ region 142 and the second N+ region 132 are interconnected by wires to form a cathode of the device. Figure 5 In the embodiment of FIG. 1 , a structure of stacking two bidirectional SFSCR devices in series is shown. The bidirectional SFSCR device stacking structure is Figure 4 The bidirectional SFSCR device shown is a basic structural unit. Two bidirectional SFSCR devices are located relatively to the left and right and isolated by an N-type isolation deep well region 271 in the middle.

[0084] In this embodiment, if higher device performance requirements are required, multiple bidirectional SFSCR devices can be stacked and connected in series, by continuing to add an N-type isolation deep well region 271 to the right of the right bidirectional SFSCR device, and continuing to add a bidirectional SFSCR device to the right of the N-type isolation deep well region 271, and connecting the cathode of the former and the anode of the latter through a wire to achieve the series connection of the newly added bidirectional SFSCR device. Repeating this process can achieve any number of bidirectional SFSCR device stacking and series connection structures to meet the performance requirements of different application scenarios.

[0085] In Example 1, a method of combining two Figure 2The SFSCR device stacking and packaging structure is a stacked packaging structure of SFSCR devices. In this embodiment, the SFSCR device stacking and series structure can be arbitrarily replaced with a bidirectional SFSCR device stacking and series structure, that is, the packaging of any number and any order of SFSCR device stacking and series structure and bidirectional SFSCR device stacking and series structure can be realized to meet the performance requirements of different application scenarios.

[0086] Working principle:

[0087] The SFSCR device stacking structure proposed in the present invention improves the device's holding voltage, failure current, specific on-resistance characteristics, and performance per unit area without increasing the occupied area, thereby achieving excellent area-performance efficiency.

[0088] In the SFSCR device structure used in the present invention, a part of the N+ region emitter of the parasitic NPN is replaced by a new low-emission efficiency Zener junction, thereby weakening part of the NPN bipolar effect. This Zener junction with low emission efficiency and the ZP / NW / PW structure form a new PNPN path 1 with weak positive feedback. In addition, the N+ region and the ZP / NW / PW structure located in the PW region also form a regular path 2. As the distance between the floating P+ region and the N+ region in the PW region increases, the equivalent cathode resistance will increase due to the reduction in the area of ​​the effective N+ region, thereby causing the maintenance voltage of path 2 to increase. When the maintenance voltage of path 2 increases to the maintenance voltage of path 1, a snapback-free characteristic will be achieved. At this time, the current of path 2 will be approximately equal to the current of path 1.

[0089] The SFSCR device stacking structure proposed in the present invention can superimpose the performance of each integrated SFSCR device, and finally obtain an ESD protection chip with excellent performance. On the basis of not increasing the area, the performance of the SFSCR device structure is further improved in a smaller space, achieving a small occupied area, high holding voltage, and high failure current, improving the performance of the device per unit area, and achieving excellent area performance efficiency.

[0090] The device structure and drawings proposed in the present invention are only a display and explanation of the SFSCR device stacking structure. In addition to the structure in the drawings, anyone familiar with this technology can modify or change the above structure without violating the spirit and scope of the present invention, such as changing the SFSCR structure described above to a PNP structure, an NPN structure, a diode structure, a MOS structure, etc., or changing the number of stacked series or stacked packages according to different application scenarios, or a SFSCR device, an SFSCR device stacked series structure and an SFSCR device stacked package structure, a PNP device stacked series structure, a diode device stacked series structure, a bidirectional SFSCR device stacked series structure, etc., and these structures should obviously be within the protection scope of the present invention.

[0091] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A SFSCR device, characterized in that: The device comprises: a P-type substrate (100), a P-type deep well region (101), an N-type well region (111), a P-type well region (121), a first N+ region (131), a second N+ region (132), a first P+ region (141), a second P+ region (142), a floating N+ region (151), a floating P+ region (161), an anode ZP region (171), and a cathode ZP region (172); The first N+ region (131) and the first P+ region (141) are interconnected by wires to form an anode of the device, and the second N+ region (132), the second P+ region (142) and the cathode ZP region (172) are interconnected by wires to form a cathode of the device.

2. The SFSCR device according to claim 1, characterized in that: The P-type deep well region (101) is located inside the P-type substrate (100), the upper edge of the P-type deep well region (101) is tangent to the upper edge of the P-type substrate (100), and the lower edge of the P-type deep well region (101) is higher than the lower edge of the P-type substrate (100); The N-type well region (111) and the P-type well region (121) are located inside the P-type deep well region (101); the upper edge of the N-type well region (111) and the upper edge of the P-type well region (121) are both tangent to the upper edge of the P-type deep well region (101); the lower edge of the N-type well region (111) and the lower edge of the P-type well region (121) are both higher than the lower edge of the P-type deep well region (101); wherein the N-type well region (111) and the P-type well region (121) are adjacent, the N-type well region (111) is located on the left side of the P-type well region (121), and the right edge of the N-type well region (111) is tangent to the left edge of the P-type well region (121); The first N+ region (131) and the first P+ region (141) are located inside the N-type well region (111); the upper edge of the first N+ region (131) and the upper edge of the first P+ region (141) are both tangent to the upper edge of the N-type well region (111); the lower edge of the first N+ region (131) and the lower edge of the first P+ region (141) are both higher than the lower edge of the N-type well region (111); wherein the first N+ region (131) is located on the left side of the first P+ region (141); the right edge of the first N+ region (131) and the left edge of the first P+ region (141) are spaced 2um to 5um apart; The second N+ region (132) and the second P+ region (142) are located inside the P-type well region (121); the upper edge of the second N+ region (132) and the upper edge of the second P+ region (142) are both tangent to the upper edge of the P-type well region (121); the lower edge of the second N+ region (132) and the lower edge of the second P+ region (142) are both higher than the lower edge of the P-type well region (121); wherein the second N+ region (132) is located on the left side of the second P+ region (142); and the right edge of the second N+ region (132) and the left edge of the second P+ region (142) are spaced 2um to 5um apart; The floating N+ region (151) spans the junction of the N-type well region (111) and the P-type well region (121), the floating N+ region (151) is located inside the N-type well region (111) and the P-type well region (121), the upper edge of the floating N+ region (151) is tangent to the upper edge of the N-type well region (111) and the upper edge of the P-type well region (121), and the lower edge of the floating N+ region (151) is higher than the lower edge of the N-type well region (111) and the lower edge of the P-type well region (121); the floating N+ region (151) is adjacent to the first P+ region (141), the floating N+ region (151) is located on the right side of the first P+ region (141), and the left edge of the floating N+ region (151) is tangent to the right edge of the first P+ region (141); The floating P+ region (161) is located inside the P-type well region (121), the upper edge of the floating P+ region (161) is tangent to the upper edge of the P-type well region (121), and the lower edge of the floating P+ region (161) is higher than the lower edge of the P-type well region (121); the floating P+ region (161) is located on the left side of the second N+ region (132), and the right edge of the floating P+ region (161) and the left edge of the second N+ region (132) are spaced no more than 10 um; The anode ZP region (171) is located inside the N-type well region (111), the upper edge of the anode ZP region (171) is tangent to the upper edge of the N-type well region (111), and the lower edge of the anode ZP region (171) is higher than the lower edge of the N-type well region (111); the anode ZP region (171) wraps around the first P+ region (141), the upper edge of the anode ZP region (171) is tangent to the upper edge of the first P+ region (141), and the right edge of the anode ZP region (171) is tangent to the right edge of the first P+ region (141). The right edge of the anode ZP region (171) is tangent to the left edge of the first P+ region (141); the lower edge of the anode ZP region (171) is lower than the lower edge of the first P+ region (141), with an interval of 0.5um to 5um; the anode ZP region (171) is adjacent to the floating N+ region (151), the anode ZP region (171) is located on the left side of the floating N+ region (151), and the right edge of the anode ZP region (171) is tangent to the left edge of the floating N+ region (151); The cathode ZP region (172) is located inside the P-type well region (121), the upper edge of the cathode ZP region (172) is tangent to the upper edge of the P-type well region (121), and the lower edge of the cathode ZP region (172) is higher than the lower edge of the P-type well region (121); the cathode ZP region (172) is adjacent to the second N+ region (132), the cathode ZP region (172) is located on the left side of the second N+ region (132), and the right edge of the cathode ZP region (172) is tangent to the left edge of the second N+ region (132); the cathode ZP region (172) wraps a portion of the floating P+ region (161), and the left edge of the cathode ZP region (172) is located inside the floating P+ region (161); the lower edge of the cathode ZP region (172) is lower than the lower edges of the floating P+ region (161) and the second N+ region (132), and the interval is 0.5um to 5um.

3. A SFSCR device stacked series structure, characterized in that: It comprises two SFSCR devices as claimed in claim 1 or 2 and a P-type isolation deep well region (181); the SFSCR devices constitute a basic structural unit of a SFSCR device stacked in series structure.

4. The SFSCR device stacked series structure according to claim 3, characterized in that: The two SFSCR devices are a first SFSCR device (001) and a second SFSCR device (002); the first SFSCR device (001) and the second SFSCR device (002) are located on the same P-type substrate (100); the first SFSCR device (001) is on the left side of the second SFSCR device (002), with a distance of 5 um to 30 um between them; The P-type isolation deep well region (181) is located inside the P-type substrate (100), the upper edge of the P-type isolation deep well region (181) is tangent to the upper edge of the P-type substrate (100), and the lower edge of the P-type isolation deep well region (181) is higher than the lower edge of the P-type substrate (100); the P-type isolation deep well region (181) is located between the first SFSCR device (001) and the second SFSCR device (002), the left edge of the P-type isolation deep well region (181) is tangent to the right edge of the first SFSCR device (001), and the right edge of the P-type isolation deep well region (181) is tangent to the left edge of the second SFSCR device (002); The cathode of the first SFSCR device (001) and the anode of the second SFSCR device (002) are connected in series via wire interconnection.

5. The SFSCR device stacked series structure according to claim 4, characterized in that: A P-type isolation deep well region (181) is continuously added to the right side of the second SFSCR device (002), and SFSCR devices are continuously added to the right side of the P-type isolation deep well region (181), and the cathode of the second SFSCR device (002) is connected to the anode of the newly added SFSCR device through a wire to realize the series connection of the first SFSCR device (001), the second SFSCR device (002) and the newly added SFSCR device; and this is repeated to realize a stacked series structure of any number of SFSCR devices.

6. A SFSCR device stacking package structure, characterized in that: The invention comprises two SFSCR device stacked series structures as described in any one of claims 3 to 5, a substrate (301), an upper adhesive (311), a lower adhesive (312) and a transition gasket (321); the SFSCR device stacked series structure constitutes a basic structural unit of the SFSCR device stacked packaging structure.

7. The SFSCR device stacking package structure according to claim 6, characterized in that: The two SFSCR device stacked series structures are a first SFSCR device stacked series structure (011) and a second SFSCR device stacked series structure (012); the first SFSCR device stacked series structure (011) and the second SFSCR device stacked series structure (012) are located above the substrate (301); wherein the lower edge of the second SFSCR device stacked series structure (012) is tangent to the upper edge of the substrate (301), and the second SFSCR device stacked series structure (012) is located in the middle of the substrate (301); The upper adhesive (311), the lower adhesive (312) and the transition gasket (321) are located between the first SFSCR device stacked series structure (011) and the second SFSCR device stacked series structure (012), and the order from top to bottom is the first SFSCR device stacked series structure (011), the upper adhesive (311), the transition gasket (321), the lower adhesive (312) and the second SFSCR device stacked series structure (012); The anodes and cathodes of the first SFSCR device stacked series structure (011) and the second SFSCR device stacked series structure (012) are respectively connected to the substrate (301) through metal wires.

8. The SFSCR device stacking package structure according to claim 7, characterized in that: A lower layer of adhesive (312) is continuously applied on top of the first SFSCR device stacked series structure (011), a transition gasket (321) is inserted, and an upper layer of adhesive (311) is applied. Then, a new SFSCR device stacked series structure is placed on the upper layer of adhesive (311), and the anode and cathode of the new SFSCR device stacked series structure are connected to the substrate via metal wires, thereby realizing the stacking packaging of the first SFSCR device stacked series structure (011), the second SFSCR device stacked series structure (012), and the new SFSCR device stacked series structure; and this process is repeated to realize any number of SFSCR device stacked series packaging structures.

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