Transistor preparation method, transistor array and electronic equipment
By stacking multilayer films on the silicon substrate and etching to form a bilateral epitaxial silicon material, structural defects and high contact resistance problems caused by channel asymmetry are solved, and the performance of vertical gate fully surround transistors is improved.
Patent Information
- Application Number
- CN202310827127.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-06
- Publication Date
- 2025-01-10
Smart Images
Figure CN119300379A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor, a transistor array, and an electronic device. Background Art
[0002] The vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and an unlimited channel length.
[0003] In the related art, during the manufacturing process of the VGAA transistor array, epitaxial silicon on silicon germanium and silicon materials is generated through a single epitaxial growth on a silicon column, and the epitaxial silicon on the silicon material is annealed and diffused to retain the epitaxial silicon on the silicon germanium as a channel.
[0004] However, the channel formed based on a single epitaxial growth may cause structural defects due to the asymmetry of the channel within the transistor, and cause high contact resistance between the channel and the source and drain, thereby reducing the performance of the transistor. Summary of the invention
[0005] The embodiments of the present application provide a method for manufacturing a transistor, a transistor array, and an electronic device, which can improve the symmetry of the channel structure within the transistor. The technical solution is as follows:
[0006] In one aspect, a method for preparing a transistor is provided, the method comprising:
[0007] stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate, wherein the first silicon film layer is adjacent to the silicon substrate;
[0008] Etching a first etched groove along the bit line direction on the silicon substrate, the first silicon film layer, the germanium silicon film layer and the second silicon film layer, filling the first etched groove with metal material and annealing to generate a bit line;
[0009] Etching a second etched groove along the word line direction on the first silicon film layer and the silicon germanium film layer, and generating epitaxial silicon material on the surfaces of the first silicon film layer, the silicon germanium film layer, and the second silicon film layer based on silicon pillars formed by the first etched groove and the second etched groove;
[0010] Filling the first etching groove and the second etching groove with silicon dielectric material, and etching the silicon column into at least two sub-silicon columns;
[0011] The epitaxial silicon material is generated in the area of the at least two sub-silicon pillars not covered by the silicon dielectric material, and a vertical gate all-around transistor is obtained after the gate material is filled to form a word line.
[0012] In an optional embodiment, etching the silicon substrate, the first silicon film layer, the silicon germanium film layer and the second silicon film layer along the bit line direction to form a first etched groove includes:
[0013] forming a plurality of columns of first mask material on the second silicon film layer along the bit line direction;
[0014] Regions of the silicon substrate, the first silicon film layer, the silicon germanium film layer, and the second silicon film layer that are not covered by the first mask material are etched to form first etching grooves along the direction of the bit lines.
[0015] In an optional embodiment, etching the second silicon film layer and the silicon germanium film layer along the word line direction to form a second etched groove includes:
[0016] forming a plurality of columns of second mask material on the second silicon film layer along the word line direction;
[0017] The regions of the second silicon film layer and the silicon germanium film layer that are not covered by the second mask material are etched to form second etching grooves along the direction of the word lines.
[0018] In an optional embodiment, the step of filling the first etching groove and the second etching groove with a silicon dielectric material and etching the silicon column into at least two sub-silicon columns comprises:
[0019] Filling the first etching groove and the second etching groove with an oxide material;
[0020] Etching the oxide material not covered by the second mask material, and annealing and diffusing the epitaxial silicon material covering the second silicon film layer and not covered by the second mask material, to obtain a third etched groove;
[0021] The silicon dielectric material is filled in the third etching groove, and the silicon column is etched into at least two sub-silicon columns.
[0022] In an optional embodiment, the second mask material includes a mandrel material and a sidewall material distributed on both sides of the mandrel material;
[0023] The step of filling the silicon dielectric material in the third etching groove and etching the silicon column into at least two sub-silicon columns comprises:
[0024] The silicon dielectric material is filled in the third etching groove, and the mandrel material and the second silicon film layer and the part of the silicon germanium film layer covered by the mandrel material are etched to etch the silicon column into at least two sub-silicon columns.
[0025] In an optional embodiment, the step of generating the epitaxial silicon material in the regions of the at least two silicon sub-pillars that are not covered by the silicon dielectric material comprises:
[0026] removing the silicon germanium film layer in the at least two silicon sub-pillars;
[0027] The epitaxial silicon material is grown in the regions of the at least two silicon sub-pillars that are not covered by the silicon dielectric material.
[0028] In an optional embodiment, the method further includes:
[0029] Filling the oxide material between the at least two silicon sub-pillars and etching the oxide material between the at least two silicon sub-pillars;
[0030] The nitride material is filled between the at least two sub-silicon pillars and the epitaxial silicon material on the surfaces of the first silicon film layer and the second silicon film layer is annealed and diffused.
[0031] In an optional embodiment, the filling of the gate material to form a word line to obtain a vertical gate all-around transistor includes:
[0032] Etching the oxide material and depositing the gate material along the direction of the second etching groove;
[0033] The gate material within a first height range is etched to generate a word line within a second height range, thereby obtaining the vertical gate all-around transistor, wherein the first height range corresponds to the height range of the second silicon film layer.
[0034] In an optional embodiment, etching the gate material within a first height range to generate a word line within a second height range to obtain the vertical gate all-around transistor includes:
[0035] Etching the gate material within a first height range to generate a word line within a second height range;
[0036] A metal material is deposited on the silicon pillar to contact the second silicon film layer, thereby obtaining the vertical gate all-around transistor.
[0037] On the other hand, a transistor array is provided, wherein the transistor array comprises a plurality of transistor units arranged in an array;
[0038] The transistor unit comprises a first source / drain, a channel, a second source / drain, and a normally closed contact which are vertically distributed in sequence. The channel of the transistor unit is surrounded by a gate material. The channel is composed of epitaxial silicon generated by two epitaxies, and the two epitaxies are performed from opposite sides respectively.
[0039] The first sources / drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line;
[0040] Gate materials of a plurality of second transistor units in a second queue are connected, so that a word line is coupled to the plurality of second transistor units, wherein the first queue is a queue along a first array direction, and the second queue is a queue along a second array direction.
[0041] On the other hand, an electronic device is provided, wherein the electronic device comprises a logic device, and the logic device comprises the transistor array as described in the above embodiment.
[0042] In an optional embodiment, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0043] The beneficial effects brought by the technical solution provided in the embodiments of the present application include at least:
[0044] By forming epitaxial silicon material twice on both sides of the germanium silicon film layer as a channel, the symmetry of the channel formation relative to the transistor unit is improved, structural defects caused by channel asymmetry are avoided, the high contact resistance between the channel and the source / drain is reduced, and the performance of the transistor is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0046] Figure 1 is a schematic diagram of a vertical gate all-around transistor structure provided by one or more exemplary embodiments of the present application;
[0047] Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application;
[0048] Figure 3 is based on Figure 2 A schematic diagram of a process preparation flow on a silicon substrate provided by the illustrated embodiment;
[0049] Figure 4 is based on Figure 2 A schematic diagram of a process flow for forming a first mask material provided in the illustrated embodiment;
[0050] Figure 5 is based on Figure 2A schematic diagram of a process flow for preparing a first etching groove provided in the illustrated embodiment;
[0051] Figure 6 is based on Figure 2 A schematic diagram of a process flow for preparing a bit line provided by an embodiment is shown;
[0052] Figure 7 is based on Figure 2 A schematic diagram of a process flow for forming a second mask material provided in the illustrated embodiment;
[0053] Figure 8 is based on Figure 2 A schematic diagram of a process flow for forming a second mask material provided in the illustrated embodiment;
[0054] Fig. 9 is based on Figure 2 A schematic diagram of a process flow for epitaxial silicon generation provided by the illustrated embodiment;
[0055] Fig.10 is based on Figure 2 A schematic diagram of the process flow for preparing the etching mandrel material provided by the illustrated embodiment;
[0056] Fig.11 is a flow chart of a method for preparing a VGAA transistor provided by another exemplary embodiment of the present application;
[0057] Fig.12 is based on Fig.11 A schematic diagram of a process flow for preparing a secondary generated epitaxial silicon material provided by an embodiment shown;
[0058] Fig.13 is based on Fig.11 A schematic diagram of a process flow for annealing an epitaxial silicon material provided in the illustrated embodiment;
[0059] Fig.14 is based on Fig.11 A schematic diagram of a process flow for preparing a gate filling material provided by an embodiment is shown;
[0060] Fig.15 is based on Fig.11 A schematic diagram of a process flow for preparing metal material deposition provided by the illustrated embodiment;
[0061] Fig.16 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0062] Fig.17 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0063] Fig.18 is a schematic diagram of a process for forming a stacked structure provided by one or more exemplary embodiments of the present application;
[0064] Fig.19 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0065] Fig. 20 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0066] Fig.21 It is a schematic diagram of a formation process of a stacking structure provided by one or more other exemplary embodiments of the present application.
[0067] Silicon substrate-00;
[0068] A first silicon film layer-11, a germanium silicon film layer-12, and a second silicon film layer-13;
[0069] Metal material - 20, epitaxial silicon material 30, silicon dielectric material - 40, gate material - 50;
[0070] The first mask material is 60, the second mask material is 70, and the oxide material is 80;
[0071] Mandrel material-71, side wall material-72. DETAILED DESCRIPTION
[0072] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0073] A gate-all-around FET is a transistor structure in which the gate material wraps around the periphery of the channel. Compared with planar GAA transistors, vertical GAA transistors have a small projected area, unlimited channel length, no contacted gate pitch (CGP) restrictions, good parasitic capacitance control, and are suitable for 3D integration.
[0074] In the related art, when manufacturing a VGAA transistor, the following processes are usually included:
[0075] First, a silicon film layer is provided as a source, and a silicon nanocolumn perpendicular to the silicon film layer is formed on the silicon film layer. After an isolation layer is deposited on the silicon film layer, a gate dielectric is deposited on the silicon nanocolumn and the silicon film layer, and a gate material is deposited on the surface of the gate dielectric. The coverage of the gate material on the upper surface of the silicon nanocolumn is etched, and the height of the silicon nanocolumn exceeds the coverage height of the gate material, and then an isolation layer is deposited to a height lower than the silicon nanocolumn. After silicon is deposited on the silicon nanocolumn as a drain, the source is set to contact with the lower source silicon film layer, the drain is set to contact with the drain silicon deposited on the upper layer, and the ring gate material is set to contact along the word line.
[0076] In the related art, when generating a channel, epitaxial silicon is generated by a single epitaxy on a nano silicon pillar, so that the epitaxial silicon is used as a channel. However, the channel formed based on a single epitaxy plus annealing may cause structural defects due to the asymmetry of the channel in the transistor, and cause high contact resistance between the channel and the source and drain, thereby reducing the performance of the transistor.
[0077] In an embodiment of the present application, a method for preparing a transistor is provided. Optionally, the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
[0078] First, the structure of the VGAA transistor in the embodiment of the present application is introduced.
[0079] In an embodiment of the present application, a transistor array is provided. The transistor array includes a plurality of transistor units arranged in an array; the transistor unit includes a first source / drain, a channel, a second source / drain, and a normally closed contact that are vertically distributed in sequence; the channel of the transistor unit is surrounded by a gate material, and the channel is composed of epitaxial silicon generated by two epitaxies, and the two epitaxies are performed from opposite sides respectively; the first sources / drains of the plurality of first transistor units in the first queue are connected by coupling buried bit lines; the gate materials of the plurality of second transistor units in the second queue are connected, so that the word lines are coupled to the plurality of second transistor units, wherein the first queue is a queue along the first array direction, and the second queue is a queue along the second array direction.
[0080] like Figure 1 As shown, the transistor array 100 includes a plurality of transistor cells 110 .
[0081] Each transistor unit 110 is connected to a bit line (BL) 111 through a source / drain 113 and a word line (WL) 112 through a gate 114. The gate 114 surrounds a channel 115, and a normally closed contact (NC) 116 contacts the source / drain 113. The source / drain 113 is a heavily doped material, and the channel is a lightly doped material or an undoped material.
[0082] Among them, multiple transistor units 110 in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units 110 in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
[0083] The word line WL112 is connected to the gate 114 as a gate line to turn on the transistor unit 110 ; the bit line BL111 is connected to the source / drain 113 as a data signal writing line. The gate 114 surrounds the channel 115 .
[0084] The normally open contact or normally closed contact 116 refers to the natural state without any external effect (such as power on), at which time the normally open contact is disconnected and the normally closed contact 116 is connected. In the embodiment of the present application, the source / drain 113 of the transistor unit 110 is connected to the normally closed contact as an example for explanation. If the source is connected to the bit line 111, the drain is connected to the normally closed contact 116; if the drain is connected to the bit line 111, the source is connected to the normally closed contact 116.
[0085] Combined with the above introduction to VGAA transistors, Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes the following steps.
[0086] Step 201 : stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate.
[0087] The first silicon film layer 11 is adjacent to the silicon substrate 00 .
[0088] That is, the stacking sequence is to first deposit the first silicon film layer 11 on the silicon substrate 00 , deposit the silicon germanium film layer 12 on the first silicon film layer 11 , and then deposit the second silicon film layer 13 on the silicon germanium film layer 12 .
[0089] The first silicon film layer 11 and the second silicon film layer 13 are used as the source / drain in the transistor, and doping is performed during the in-situ growth process of the first silicon film layer 11 and the second silicon film layer 13. The first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are deposited by in-situ growth, and the duration of the in-situ growth is controlled to control the thickness of the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13; and during the doping process, the ion implantation concentration of the first silicon film layer 11 and the second silicon film layer 13 is controlled.
[0090] Indicatively, Figure 3As shown, a first silicon film layer 11 , a germanium silicon film layer 12 , and a second silicon film layer 13 are sequentially deposited on a silicon substrate 00 from bottom to top.
[0091] Step 202, etching along the bit line direction to form a first etched groove on the silicon substrate, the first silicon film layer, the germanium silicon film layer and the second silicon film layer, filling the first etched groove with metal material and annealing to generate a bit line.
[0092] In some embodiments, multiple columns of first mask material 60 are formed on the second silicon film layer 13 along the bit line direction, and areas of the silicon substrate 00, the first silicon film layer 11, the germanium silicon film layer 12, and the second silicon film layer 13 that are not covered by the first mask material 60 are etched to form a first etching groove along the bit line direction.
[0093] In some embodiments, photoresist (PR) is used as the first mask material 60, or other materials can be selected as the first mask material 60, and there is a certain etching selectivity between the first mask material 60 and silicon and silicon germanium. Optionally, a self-aligned double patterning technology (SADP) or a self-aligned quadruple patterning technology (SAQP) or other self-aligned multiple patterning (SAMP) technology is used to form multiple columns of the first mask material 60 on the first silicon film layer 11.
[0094] Among them, SADP is used as an example for explanation in this embodiment. SADP refers to the process of using non-photolithography process steps (thin film deposition, etching, etc.) to achieve spatial frequency doubling of the photolithography pattern after one photolithography is completed. Finally, another photolithography and etching are used to remove the redundant pattern, thereby realizing the process of forming a patterned mask material. In some embodiments, the SADP process includes: providing a material layer to be etched; forming a sacrificial photoresist layer on the material layer to be etched; curing the photoresist on the top and side walls of the sacrificial photoresist layer to form a cured photoresist shell; etching back the cured photoresist shell on the top of the sacrificial photoresist layer until the uncured internal sacrificial photoresist layer is exposed, and the cured photoresist shell located on the side walls of the internal sacrificial photoresist layer forms the pattern of the first mask material 60; removing the uncured internal sacrificial photoresist layer to obtain a plurality of columns of first mask materials 60 formed on the first silicon film layer 11.
[0095] Indicatively, Figure 4 As shown, a plurality of columns of first mask material 60 are formed on the second silicon film layer 13 along the bit line direction.
[0096] In some embodiments, when etching the area of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 that is not covered by the first mask material 60, the etching rate of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 is greater than the etching rate of the first mask material 60, so that the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are etched while maintaining a small amount of sacrifice of the first mask material 60. The first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are penetrated during the etching process, and the silicon substrate 00 with a partial thickness is etched by controlling the etching time, without penetrating the silicon substrate 00.
[0097] In some embodiments, in order to prevent the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 from being affected by the metal material 20 during the process of generating the bit line, the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are isolated by oxide.
[0098] Optionally, first, the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 60 are etched to form candidate etching grooves along the bit line direction; oxide material 80 is deposited to cover the inner and outer surfaces of the candidate etching grooves with the oxide material 80, and the oxide material 80 is used to isolate the reaction between the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 and the metal material 20; on the basis of the candidate etching grooves, the areas in the silicon substrate 00 that are not covered by the first mask material 60 are etched to form a first etching groove along the bit line direction.
[0099] Indicatively, Figure 5 As shown, first, the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 60 are etched by controlling the etching time to obtain candidate etching grooves, and then an oxide material 80, such as silicon dioxide (SiO2), is deposited by atomic layer deposition (ALD). The oxide material 80 covers the inner and outer surfaces of the candidate etching grooves, and the oxide and silicon substrate 00 are continuously etched. By controlling the etching time, the silicon substrate 00 with a preset thickness requirement is etched to obtain a first etching groove.
[0100] In some embodiments, a metal material 20, such as tungsten (W) material, is deposited at the bottom of the first etched groove, and the silicon substrate 00 is annealed to form a metal silicide as a bit line through annealing. Annealing refers to the process of diffusing metal into the silicon substrate 00 through ohmic contact to form a metal silicide.
[0101] In some embodiments, a silicon dielectric material 40 with a first height is firstly filled in the first etched groove. In some embodiments, the silicon dielectric material 40 can be implemented as a nitride material or an oxide material, which is not limited in this embodiment. Taking the nitride material as an example, the silicon dielectric material 40 can be implemented as silicon nitride (SiN), and the first height is less than the depth of the first etched groove in the silicon substrate 00. The metal material 20 is filled on the silicon dielectric material 40 and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material 40.
[0102] Optionally, a silicon dielectric material 40 is deposited in the first etching groove by atomic layer deposition ALD or chemical vapor deposition (CVD) and then polished, and then the silicon dielectric material 40 is etched to a first height by controlling the etching time. The etching rate of the silicon dielectric material 40 is greater than the etching rate of the first mask material 60.
[0103] Indicatively, Figure 6 As shown, first, the silicon dielectric material 40 is filled in the first etched groove and ground flat, and then the silicon dielectric material 40 of a first height in the first etched groove is retained by etching, and the first height is less than the depth of the first etched groove of the silicon substrate 00, that is, the upper plane of the silicon dielectric material 40 after etching is below the upper plane of the silicon substrate 00. After the metal material 20 is deposited on the silicon dielectric material 40, a metal silicide is generated by annealing as a bit line.
[0104] Optionally, excess metal material 20 is removed by wet etching.
[0105] Step 203, etching along the word line direction to form a second etched groove on the second silicon film layer and the germanium silicon film layer, and generating epitaxial silicon material on the surfaces of the first silicon film layer, the germanium silicon film layer and the second silicon film layer based on silicon pillars formed by the first etched groove and the second etched groove.
[0106] In some embodiments, the silicon dielectric material 40 of the second height is filled in the first etching groove, wherein the upper plane of the silicon dielectric material 40 of the second height meets the plane distance requirement with the upper plane of the first silicon film layer 11, such as: the upper plane of the silicon dielectric material 40 and the upper plane of the first silicon film layer 11 are in the same plane or the distance is less than the distance threshold. The oxide material 80 is filled in the first etching groove, and a plurality of columns of the second mask material 70 are formed on the first silicon film layer 11 after the oxide material 80 is filled along the word line direction.
[0107] In some embodiments, when the silicon dielectric material 40 of the second height is filled in the first etching groove, the silicon dielectric material 40 exceeding the height of the second silicon film layer 13 is first filled and polished, and then the silicon dielectric material 40 is etched to the second height by controlling the etching time.
[0108] In some embodiments, since oxide is deposited on the surfaces of the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 in the above step 202, optionally, the silicon dielectric material 40 can be filled after etching away the oxide, or the silicon dielectric material 40 can be directly filled without removing the oxide. This embodiment is not limited to this.
[0109] Among them, the silicon dielectric material 40 is used as an etching stop line when etching along the word line direction, that is, when the second silicon film layer 13 and the germanium silicon film layer 12 are etched along the word line direction, the etching time is controlled until the upper surface of the silicon dielectric material 40 is etched and the etching is stopped.
[0110] In some embodiments, after depositing the silicon dielectric material 40 of the second height, the oxide material 80 is continuously deposited on the silicon dielectric material 40 to a height exceeding the second silicon film layer 13 and then ground flat. A plurality of columns of the second mask material 70 are formed on the oxide and the second silicon film layer 13, and the areas of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 80 that are not covered by the second mask material 70 are etched to form a second etched groove along the word line direction.
[0111] In some embodiments, the first mask material 60 is first etched away, and then the second mask material 70 is formed on the first silicon film layer 11 .
[0112] Optionally, the second mask material 70 is used to control the direction of word line generation. After the second mask material 70 is formed along the word line direction, the second silicon film layer 13 and the germanium silicon film layer 12 are etched. In some embodiments, the etching time is controlled so that the germanium silicon film layer 12 is etched, while the first silicon film layer 11 is not etched or is less etched.
[0113] Indicatively, Figure 7 As shown, after the word line is generated, the silicon dielectric material 40 is filled in the first etching groove to a level higher than the second silicon film layer 13 and then ground by ALD / CVD / furnace method, and the ground silicon dielectric material 40 is etched until the upper plane corresponding to the silicon dielectric material 40 is flush with the contact surface of the first silicon film layer 11 and the germanium silicon film layer 12.
[0114] like Figure 8As shown, the oxide material 80 is continuously deposited on the silicon dielectric material 40 to a level higher than the second silicon film layer 13 and then ground flat, and multiple rows of the second mask material 70 are formed on the oxide material 80 and the second silicon film layer 13 by SADP or SAQP. On the basis of the second mask material 70, the second silicon film layer 13, the silicon germanium film layer 12, and the area of the oxide material 80 not covered by the second mask material 70 are etched to form a second etched groove, wherein the etching rate of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 80 is greater than the etching rate of the second mask material 70.
[0115] In some embodiments, the second silicon film layer 13 , the germanium silicon film layer 12 , and the oxide material 80 are etched by dry etching or wet etching.
[0116] In some embodiments, silicon pillars are formed based on the first etching grooves and the second etching grooves, wherein the grooves within the height range where the first silicon film layer 11 is located are filled with silicon dielectric material 40, and the grooves within the height range where the second silicon film layer 13 and the germanium silicon film layer 12 are located are not filled with silicon dielectric material 40.
[0117] Therefore, firstly, the surface of the germanium silicon film layer 12 is lateral etched to a first thickness on the silicon pillar by a lateral atomic layer etching process (ALE) or lateral wet etching or lateral dry etching, etc. Then, an epitaxial silicon material 30 is formed on the side surfaces of the second silicon film layer 13, the germanium silicon film layer 12, and the upper surface of the first silicon film layer 11 by selective epitaxy.
[0118] Indicatively, Fig. 9 As shown, first, the germanium-silicon material on the silicon pillar is laterally etched, and the germanium-silicon material is etched inward to a first thickness, and then an epitaxial silicon material 30 is formed on the silicon material and the germanium-silicon material surface of the silicon pillar by selective epitaxy, that is, the epitaxial silicon material 30 is formed on the side surfaces of the second silicon film layer 13 and the germanium-silicon film layer 12 and the upper surface of the first silicon film layer 11. The process growth rate of the epitaxial silicon material is selective, that is, the epitaxial silicon rate on the surface of the silicon pillar and the germanium-silicon material is faster, and the rate on the dielectric material is very low, so the main epitaxial silicon exists on the silicon pillar and the germanium-silicon material.
[0119] In some embodiments, an epitaxial silicon material 30 with a second thickness is generated on the etched surface of the silicon germanium film layer 12 , wherein the second thickness is less than the first thickness.
[0120] In some embodiments, intrinsic silicon, i.e., epitaxial silicon material 30, is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 by selective epitaxy. The selective epitaxy is to generate epitaxial silicon material 30 by depositing a precursor and then reacting the precursor on the silicon / silicon germanium material, while other materials will not adsorb the precursor, and thus will not generate epitaxial silicon material 30. By controlling the adsorption amount of the precursor or the duration of epitaxial growth, epitaxial silicon material 30 is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13, wherein the epitaxial silicon material 30 of the second thickness is generated on the surface of the silicon germanium film layer 12.
[0121] Step 204: Fill the first etching groove and the second etching groove with silicon dielectric material, and etch the silicon column into at least two sub-silicon columns.
[0122] By filling the silicon dielectric material 40 , the thickness of the epitaxial silicon material 30 on one side where the epitaxial silicon material 30 has been formed is controlled not to increase further, but the epitaxial silicon material 30 is formed from the etched side, thereby obtaining a symmetrical channel structure based on the epitaxial silicon formed twice.
[0123] In some embodiments, oxide material 80 is first filled between multiple silicon pillars, and the area not covered by the second mask material 70 is etched. At this time, the second silicon film layer 13 is laterally covered with epitaxial silicon material 30, and the germanium silicon film layer 12 is laterally covered with epitaxial silicon material 30 and oxide material 80; silicon dielectric material 40 is filled between the silicon pillars, and the silicon pillars are etched into at least two sub-silicon pillars.
[0124] Optionally, fill the first etching groove and the second etching groove with oxide material 80; etch the oxide material 80 not covered by the second mask material 70, and anneal and diffuse the epitaxial silicon material 30 covering the first silicon film layer 11 and not covered by the second mask material 70 to obtain a third etching groove; fill the third etching groove with silicon dielectric material 40, and etch the silicon column into at least two sub-silicon columns.
[0125] In some embodiments, the second mask material 70 includes a mandrel material 71 and a sidewall material 72 distributed on both sides of the mandrel material 71, and the silicon pillar is etched into at least two sub-silicon pillars by etching the mandrel material 71 and the area covered by the mandrel material 71. Schematically, the silicon dielectric material 40 is filled in the third etching groove, and the mandrel material 71 and the portion of the second silicon film layer 13 and the silicon germanium film layer 12 covered by the mandrel material 71 are etched to etch the silicon pillar into at least two sub-silicon pillars.
[0126] In some embodiments, the mandrel material 71 and the spacer material 72 correspond to a certain etching selectivity ratio, so that during the etching process of the mandrel material 71 , only a small amount of sacrificial etching occurs on the spacer material 72 .
[0127] Indicatively, Fig.10 As shown, after forming epitaxial silicon material 30 on the silicon pillar, oxide material 80 is filled between the silicon pillars, and the portion not covered by the second mask material 70 (including: oxide material 80 not covered by the second mask material 70 and epitaxial silicon material 30 on the upper surface of the first silicon film layer 11 not covered by the second mask material 70) is etched to form a third etched groove, and silicon dielectric material 40 is filled in the third etched groove to be higher than the second mask material 70 and then ground, and the mandrel material 71 and the second silicon film layer 13 and the germanium silicon film layer 12 covered by the mandrel material 71 are etched to obtain a plurality of sub-silicon pillars. The oxide material 80 remaining when etching the third etched groove is used to replace the gate material 50 in the subsequent process.
[0128] Step 205 , generating epitaxial silicon material in the areas of at least two silicon sub-pillars that are not covered by the silicon dielectric material, and filling the areas with gate material to form word lines to obtain a vertical gate all-around transistor.
[0129] In some embodiments, the duration of selective epitaxy to form the epitaxial silicon material 30 in step 203 is the same as the duration of selective epitaxy to form the epitaxial silicon material 30 in step 205 , or the difference in duration is less than the difference requirement.
[0130] In some embodiments, the epitaxial silicon material on the surface of the first silicon film layer and the second silicon film layer is annealed and diffused, and the gate material is filled as a word line to obtain a vertical gate full-surround transistor. Optionally, the epitaxial silicon material 30 on the surface of the first silicon film layer 11 and the second silicon film layer 13 is diffused into the silicon material through annealing, and is integrated with the source / drain, and the epitaxial silicon material 30 generated on the surface of the germanium silicon film layer 12 is retained.
[0131] In some embodiments, after the channel is generated, the gate material 50 (Gate) is filled along the word line direction by replacing the oxide material 80 to obtain a gate surrounding the channel and generate a word line, thereby obtaining a vertical all-around gate transistor.
[0132] To summarize, the method provided in this embodiment forms epitaxial silicon material twice on both sides of the germanium silicon film layer as a channel, so that the symmetry of the channel formation relative to the transistor unit is improved, the structural defects caused by channel asymmetry are avoided, the high contact resistance between the channel and the source / drain is reduced, and the performance of the transistor is improved.
[0133] The method provided in this embodiment, through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source / drain, on the basis of forming a bit line on the silicon substrate through a first mask material, and forming a channel and a word line and a ring gate through a second mask material, thereby improving the alignment between the bit line, the channel, the source / drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0134] In some embodiments, during the selective epitaxial deposition process, the epitaxial region of the selective epitaxial growth is controlled by a nitride material. Fig.11 is a flow chart of a method for preparing a transistor provided by another exemplary embodiment of the present application, such as Fig.11 As shown, the above step 205 can also be implemented as the following steps 2051 to 2056.
[0135] Step 2051, removing the silicon germanium film layer in at least two sub-silicon pillars.
[0136] Optionally, after the germanium silicon film layer 12 in at least two sub-silicon pillars is removed, the epitaxial silicon material 30 formed by selective epitaxy in the above step 203 is in contact with air.
[0137] Step 2052: Generate epitaxial silicon material in the regions of at least two sub-silicon pillars that are not covered by the silicon dielectric material.
[0138] Optionally, epitaxial silicon material 30 is further grown on the surface of the generated epitaxial silicon material 30 by selective epitaxy, so as to form epitaxial silicon material 30 of a certain thickness from both sides, so that the epitaxial silicon material 30 forms a symmetrical structure in the transistor unit.
[0139] Step 2053: Filling an oxide material between at least two silicon sub-pillars and etching the oxide material between at least two silicon sub-pillars.
[0140] Optionally, an oxide material 80 is filled between at least two sub-silicon pillars, and the oxide material 80 not covered by the spacer material 72 is etched. The spacer material 72 may also be referred to as a spacer material.
[0141] In some embodiments, after etching the oxide material 80 not covered by the spacer material 72 , the spacer material 72 is etched.
[0142] Indicatively, Fig.12As shown, after forming a plurality of sub-silicon pillars, the germanium silicon film layer 12 on the sub-silicon pillars is removed to expose the generated epitaxial silicon material 30, and after continuing to generate epitaxial silicon material 30 by selective epitaxy on the epitaxial silicon material 30, oxide material 80 is filled between the plurality of sub-silicon pillars, and the oxide material 80 not covered by the sidewall material 72 is etched, and the material within the height range where the sidewall material 72 is located is etched.
[0143] Step 2054: Fill the silicon dielectric material between at least two sub-silicon pillars and perform annealing and diffusion on the epitaxial silicon material on the surfaces of the first silicon film layer and the second silicon film layer.
[0144] After the silicon dielectric material 40 is filled between the multiple sub-silicon pillars, the epitaxial silicon material 30 on the first silicon film layer 11 and the second silicon film layer 13 in the transistor that is not covered by the oxide material 80 is annealed and diffused, so that the epitaxial silicon material 30 is diffused into the silicon film layer and integrated with the source / drain, and the epitaxial silicon material 30 covered by the oxide material 80 is retained as a channel.
[0145] Indicatively, Fig.13 As shown, a silicon dielectric material 40 is filled between the sub-silicon pillars, and the epitaxial silicon material 30 on the first silicon film layer 11 and the second silicon film layer 13 is annealed.
[0146] Step 2055, etching the oxide material and filling the gate material along the direction of the second etched groove.
[0147] In some embodiments, the oxide material 80 retained in the structure is etched by wet etching, and the oxide is replaced by the gate material 50 by utilizing the selectivity between oxide and nitride.
[0148] Step 2056, etching the gate material within the first height range, retaining the gate material within the second height range, and obtaining a vertical all-around gate transistor.
[0149] The first height range corresponds to the height range of the second silicon film layer 13 , that is, the gate material 50 on the surface of the source / drain is removed by etching, and the gate material 50 on the surface of the channel is retained.
[0150] Indicatively, Fig.14 As shown, after etching the oxide material 80 on the sub-silicon pillar, the gate material 50 is generated along the word line direction, and the gate material 50 within the height range corresponding to the second silicon film layer 13 is etched, and the gate material 50 within the height range corresponding to the channel is retained.
[0151] In some embodiments, after etching the gate material 50 within the first height range and retaining the gate material 50 within the second height range, a metal material 20 is deposited on the silicon pillar to contact the first silicon film layer 11 to obtain a vertical surrounding gate transistor.
[0152] like Fig.15 As shown, after the metal material 20 is deposited on the surface of the second silicon film layer 13, a silicon dielectric material 40 is filled to obtain a vertical surrounding gate transistor.
[0153] To summarize, the method provided in this embodiment forms epitaxial silicon material twice on both sides of the germanium silicon film layer as a channel, so that the symmetry of the channel formation relative to the transistor unit is improved, the structural defects caused by channel asymmetry are avoided, the high contact resistance between the channel and the source / drain is reduced, and the performance of the transistor is improved.
[0154] The method provided in this embodiment, through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source / drain, on the basis of forming a bit line on the silicon substrate through a first mask material, and forming a channel and a word line and a ring gate through a second mask material, thereby improving the alignment between the bit line, the channel, the source / drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0155] The method provided in this embodiment is based on the epitaxial VGAA transistor process flow, generates epitaxial silicon material as a channel and fills the gate material to surround it, thereby improving the alignment between the channel and the word line and the gate and improving the process accuracy.
[0156] The method provided in this embodiment utilizes oxide to perform a self-aligned replacement metal gate process, thereby improving the accuracy of generating gate materials.
[0157] based on Figure 2 In the method embodiment shown, when executing step 201 , well isolation is also formed in the stack structure.
[0158] In one embodiment, in conjunction with reference Fig.16 , Fig.16 Part (A1) shows the stack structure after well isolation is formed. Fig.16 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 00, a first silicon film layer 11, a germanium silicon film layer 12 and a second silicon film layer 13. Further, the silicon substrate 00 includes an upper silicon substrate 00-1 and a lower silicon substrate 00-2. Optionally, the lower silicon substrate 00-2 is doped to N type, the upper silicon substrate 00-1 is doped to P type, and the first silicon film layer 11 is doped to P type. Optionally, the lower silicon substrate 00-2 is doped to P type, the upper silicon substrate 00-1 is doped to N type, and the first silicon film layer 11 is doped to N type.
[0159] It can be noted that Fig.16 Part (B1) shows the three-dimensional structure of multiple first silicon pillars 1601 obtained after considering well isolation. Fig.16 Part (B2) shows a plan view corresponding to the three-dimensional structure. At this time, the longitudinal etching depth of the first silicon pillar 1601 only reaches the upper part of the silicon substrate 00-1, and multiple first silicon pillars 1601 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
[0160] In one embodiment, in conjunction with reference Fig.17 , Fig.17 Part (A1) shows the stack structure after well isolation is formed. Fig.17 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 00, a first silicon film layer 11, a germanium silicon film layer 12, a second silicon film layer 13, and a third silicon film layer 14 located between the silicon substrate 00 and the first silicon film layer. Optionally, the silicon substrate 00 is doped to P type, and the first silicon film layer 11 and the third silicon film layer 14 are doped to N type.
[0161] It can be noted that Fig.17 Part (B1) shows the three-dimensional structure of multiple first silicon pillars 1601 obtained after considering well isolation. Fig.17 At this time, the longitudinal etching depth of the first silicon pillar 1601 only reaches the third silicon film layer 14, and the plurality of first silicon pillars 1601 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
[0162] Illustratively, the following four possible implementations are provided for the above step 201.
[0163] A first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type, and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into P-type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0164] Combined with reference Fig.18 , Fig.18 Part (A) shows a silicon substrate 00; Fig.18 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 00 - 1 doped with N type and an upper portion of the silicon substrate 00 - 2 doped with P type. Fig.18 Part (C) shows the stacked first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13, and the first silicon film layer 11 is doped to P type.
[0165] A second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into N type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0166] Combined with reference Fig.19 , Fig.19 Part (A) shows a silicon substrate 00; Fig.19 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 00 - 1 doped to a P type and an upper portion of the silicon substrate 00 - 2 doped to an N type. Fig.19 Part (C) shows the stacked first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13, and the first silicon film layer 11 is doped to N type.
[0167] A third possible implementation method is to obtain a silicon substrate; dope the silicon substrate to N-type; sequentially stack a third silicon layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon layer and the first silicon film layer to P-type.
[0168] Combined with reference Fig. 20 , Fig. 20 Part (A) shows a silicon substrate 00; Fig. 20 Part (B) shows a silicon substrate 00 doped to N type. Fig. 20 Part (C) shows the stacked third silicon film layer 14, the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13. The third silicon film layer 14 is doped to P type, and the first silicon film layer 11 is doped to P type.
[0169] A fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon film layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon film layer and the first silicon film layer into N type.
[0170] Combined with reference Fig.21 , Fig.21 Part (A) shows a silicon substrate 00; Fig.21 Part (B) shows a silicon substrate 00 doped to a P type. Fig.21 Part (C) shows the stacked third silicon film layer 14, the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13. The third silicon film layer 14 is doped to N type, and the first silicon film layer 11 is doped to N type.
[0171] The embodiment of the present application provides an electronic device, which includes a logic device, and the logic device includes a transistor array as provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc. The transistor array is prepared by the process preparation method of the transistor provided in the above embodiment.
[0172] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0173] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.
[0174] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0175] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a transistor, characterized in that: The method comprises: A first silicon film layer (11), a germanium silicon film layer (12), and a second silicon film layer (13) are sequentially stacked on a silicon substrate (00), wherein the first silicon film layer (11) is adjacent to the silicon substrate (00); Etching a first etching groove along the direction of the bit line on the silicon substrate (00), the first silicon film layer (11), the germanium silicon film layer (12) and the second silicon film layer (13), filling the first etching groove with a metal material (20) and annealing to generate a bit line; Etching a second etched groove along the word line direction on the second silicon film layer (13) and the silicon germanium film layer (12), and generating an epitaxial silicon material (30) on the surfaces of the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) based on silicon pillars formed by the first etched groove and the second etched groove; Filling the first etching groove and the second etching groove with a silicon dielectric material (40), and etching the silicon column into at least two sub-silicon columns; The epitaxial silicon material (30) is generated in the area of the at least two sub-silicon pillars not covered by the silicon dielectric material (40), and a gate material (50) is filled to form a word line to obtain a vertical gate all-around transistor.
2. The method according to claim 1, characterized in that The step of etching the silicon substrate (00), the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) along the bit line direction to form a first etching groove comprises: forming a plurality of columns of first mask material (60) on the second silicon film layer (13) along the bit line direction; Areas not covered by the first mask material (60) in the silicon substrate (00), the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) are etched to form a first etching groove along the bit line direction.
3. The method according to claim 1, characterized in that The step of etching the second silicon film layer (13) and the germanium silicon film layer (12) along the word line direction to form a second etching groove comprises: forming a plurality of columns of second mask material (70) on the second silicon film layer (13) along the word line direction; Areas in the second silicon film layer (13) and the germanium silicon film layer (12) that are not covered by the second mask material (70) are etched to form a second etching groove along the word line direction.
4. The method according to claim 3, characterized in that The step of filling the first etching groove and the second etching groove with a silicon dielectric material (40) and etching the silicon column into at least two sub-silicon columns comprises: Filling the first etching groove and the second etching groove with an oxide material (80); Etching the oxide material (80) not covered by the second mask material (70), and annealing and diffusing the epitaxial silicon material (30) covering the second silicon film layer (13) and not covered by the second mask material (70), to obtain a third etched groove; The silicon dielectric material (40) is filled in the third etching groove, and the silicon column is etched into at least two sub-silicon columns.
5. The method according to claim 4, characterized in that The second mask material (70) comprises a mandrel material (71) and sidewall materials (72) distributed on both sides of the mandrel material (71); The step of filling the silicon dielectric material (40) in the third etching groove and etching the silicon column into at least two sub-silicon columns comprises: The silicon dielectric material (40) is filled in the third etching groove, and the mandrel material (71) and the second silicon film layer (13) and the portion of the germanium silicon film layer (12) covered by the mandrel material (71) are etched to etch the silicon column into at least two sub-silicon columns.
6. The method according to claim 1, characterized in that The step of generating the epitaxial silicon material (30) in the region of the at least two silicon sub-pillars that is not covered by the silicon dielectric material (40) comprises: removing the germanium silicon film layer (12) in the at least two silicon sub-pillars; The epitaxial silicon material (30) is grown in the regions of the at least two silicon sub-pillars that are not covered by the silicon dielectric material (40).
7. The method according to claim 6, characterized in that The method further comprises: Filling the oxide material (80) between the at least two silicon sub-pillars and etching the oxide material (80) between the at least two silicon sub-pillars; The nitride material (40) is filled between the at least two sub-silicon pillars, and the epitaxial silicon material (30) on the surface of the first silicon film layer (11) and the second silicon film layer (13) is annealed and diffused.
8. The method according to claim 6, characterized in that The filling gate material (50) forms a word line to obtain a vertical gate all-around transistor, comprising: Etching the oxide material (80) and depositing the gate material (50) along the direction of the second etching groove; The gate material (50) within a first height range is etched to generate a word line within a second height range, thereby obtaining the vertical gate all-around transistor, wherein the first height range corresponds to the height range of the second silicon film layer (13).
9. The method according to claim 8, characterized in that The etching of the gate material (50) within the first height range generates a word line within the second height range to obtain the vertical gate all-around transistor, comprising: Etching the gate material (50) within a first height range to generate a word line within a second height range; A metal material (20) is deposited on the silicon pillar to contact the second silicon film layer (13), thereby obtaining the vertical gate all-around transistor.
10. A transistor array, characterized in that: The transistor array includes a plurality of transistor units arranged in an array; The transistor unit comprises a first source / drain, a channel, a second source / drain, and a normally closed contact which are vertically distributed in sequence. The channel of the transistor unit is surrounded by a gate material. The channel is composed of epitaxial silicon generated by two epitaxies, and the two epitaxies are performed from opposite sides respectively. The first sources / drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line; Gate materials of a plurality of second transistor units in a second queue are connected, so that a word line is coupled to the plurality of second transistor units, wherein the first queue is a queue along a first array direction, and the second queue is a queue along a second array direction.
11. An electronic device, characterized in that: The electronic device comprises a logic device, and the logic device comprises the transistor array as claimed in claim 10.
12. The electronic device according to claim 11, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.