Transistor preparation method, transistor array and electronic equipment
By stacking multilayer films on a silicon substrate and using mask material to form bit lines and channels, the problem of low alignment in VGAA transistor preparation is solved, which improves the preparation accuracy and device performance and reduces complexity.
Patent Information
- Application Number
- CN202310827129.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-06
- Publication Date
- 2025-01-10
AI Technical Summary
In the preparation of vertical gate fully surround transistors (VGAA), ensuring accurate alignment of structures such as bit lines, source and drain areas, gate areas and channels is a technical problem, resulting in low preparation accuracy and success.
By sequentially stacking the first silicon film layer, the germanium film layer and the second silicon film layer on a silicon substrate, a bit line and a channel are formed using a mask material, and a gate filling groove is formed on the outer peripheral wall of the channel, by Self-aligning fill gate material to form a surrounding gate structure to improve alignment.
It improves the preparation accuracy and success rate of VGAA transistors, improves device performance, and reduces the preparation complexity.
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Figure CN119300380A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor, a transistor array, and an electronic device. Background Art
[0002] The vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and an unlimited channel length.
[0003] In the related art, when forming a VGAA transistor, a bit line is formed by using vertical etching on a single crystal silicon substrate, and then a source and drain region, a channel region, a gate region, etc. are formed by dielectric filling and back etching, and the VGAA transistor is formed by ion implantation with different doping degrees in each region.
[0004] However, in the above solution, how to ensure that structures such as the bit line, source and drain regions, gate region and channel can be accurately aligned is a technical problem. Summary of the invention
[0005] The embodiments of the present application provide a method for manufacturing a transistor, a transistor array, and an electronic device, which can improve the process accuracy of a VGAA transistor. The technical solution is as follows:
[0006] In one aspect, a method for preparing a transistor is provided, the method comprising:
[0007] stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate, wherein the first silicon film layer is adjacent to the silicon substrate;
[0008] forming a plurality of columns of first mask material on the second silicon film layer along the bit line direction, and etching the silicon substrate, the first silicon film layer, the silicon germanium film layer and the second silicon film layer in areas not covered by the first mask material to form first etching grooves along the bit line direction;
[0009] Filling the first etched groove with metal material and annealing to generate a bit line;
[0010] forming a plurality of columns of second mask material on the second silicon film layer along the word line direction, and etching the areas of the second silicon film layer and the silicon germanium film layer that are not covered by the second mask material to form second etching grooves along the word line direction;
[0011] After a channel is generated based on the germanium silicon film layer, a gate filling groove is formed on the peripheral wall of the channel, and a gate is formed in the gate filling groove by self-aligning and filling the gate material to obtain a vertical full-surround gate transistor.
[0012] In an optional embodiment, the step of filling the first etched groove with a metal material and annealing to generate a bit line includes:
[0013] Filling the first etching groove with the silicon dielectric material to obtain a target height, wherein the target height is less than a depth of the first etching groove in the silicon substrate;
[0014] The metal material is filled on the silicon dielectric material and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material.
[0015] In an optional embodiment, etching the areas of the silicon substrate, the first silicon film layer, the silicon germanium film layer, and the second silicon film layer that are not covered by the first mask material to form a first etching groove along the bit line direction includes:
[0016] Etching the regions of the first silicon film layer, the silicon germanium film layer and the second silicon film layer that are not covered by the first mask material to form candidate etching grooves along the bit line direction;
[0017] Depositing an oxide material, wherein the oxide material covers the inner surface and the outer surface of the candidate etching groove, and the oxide material is used to isolate the reaction between the first silicon film layer, the silicon germanium film layer, and the second silicon film layer and the metal material;
[0018] Based on the candidate etching groove, the area in the silicon substrate not covered by the first mask material is etched to form the first etching groove along the direction of the bit line.
[0019] In an optional embodiment, forming a plurality of columns of second mask material on the second silicon film layer along the word line direction includes:
[0020] forming the silicon dielectric material of a second height in the first etching groove, wherein an upper plane of the silicon dielectric material of the second height and an upper plane of the second silicon film layer meet a plane distance requirement;
[0021] The first etching groove is filled with an oxide material, and a plurality of columns of a second mask material are formed along the word line direction on the second silicon film layer filled with the oxide material.
[0022] In an optional embodiment, the second mask material includes a mandrel material and a spacer material distributed on both sides of the mandrel material;
[0023] The step of generating a channel based on the germanium silicon film layer comprises:
[0024] On the silicon pillars obtained by etching the first etching grooves and the second etching grooves, performing lateral etching of a first thickness on the surface of the germanium silicon film layer;
[0025] generating an epitaxial silicon material with a second thickness on the etched surface of the germanium silicon film layer, wherein the second thickness is less than the first thickness;
[0026] Etching the second silicon film layer and the germanium silicon film layer at portions covered by the mandrel material to split the silicon column into at least two sub-silicon columns;
[0027] The silicon germanium film layer in the at least two silicon sub-pillars is removed, and an oxide material is filled to obtain an oxide material surrounding the epitaxial silicon material, and the epitaxial silicon material forms a channel of the transistor.
[0028] In an optional embodiment, the step of generating an epitaxial silicon material with a second thickness on the etched surface of the germanium silicon film layer comprises:
[0029] epitaxially growing the epitaxial silicon material on the silicon pillar and the silicon dielectric material;
[0030] The second silicon film layer and the epitaxial silicon material on the surface of the silicon dielectric material are etched to obtain an epitaxial silicon material with a second thickness generated on the surface of the germanium silicon film layer.
[0031] In an optional embodiment, a gate filling groove is formed on the peripheral wall of the channel, and a gate is formed in the gate filling groove by self-aligning and filling a gate material to obtain a vertical all-around gate transistor, including:
[0032] Filling the second etching groove with silicon dielectric material;
[0033] Etching the oxide material to form the gate filling groove, and filling the gate material into the gate filling groove along the direction of the second etched groove;
[0034] The gate material within a first height range is etched to retain the gate material within a second height range, thereby obtaining the vertical all-around gate transistor, wherein the first height range corresponds to the height range of the second silicon film layer.
[0035] In an optional embodiment, after etching the gate material within the first height range to retain the gate material within the second height range, the process further includes:
[0036] A metal material is deposited on the silicon pillar to contact the second silicon film layer.
[0037] On the other hand, a transistor array is provided, wherein the transistor array includes a plurality of transistor units arranged in an array;
[0038] The transistor unit comprises a first source / drain, a channel, a second source / drain, and a normally closed contact which are vertically distributed in sequence, and the channel of the transistor unit is surrounded by a gate material;
[0039] The first sources / drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line;
[0040] Gate materials of a plurality of second transistor units in a second queue are connected to form a word line, wherein the first queue is a queue along a first array direction, and the second queue is a queue along a second array direction, and the first array direction intersects with the second array direction.
[0041] On the other hand, an electronic device is provided, wherein the electronic device comprises a logic device, and the logic device comprises the transistor array as described in the above embodiment.
[0042] In an optional embodiment, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0043] The beneficial effects brought by the technical solution provided in the embodiments of the present application include at least:
[0044] By stacking a silicon substrate, a first silicon film layer, a germanium silicon film layer and a second silicon film layer in sequence, based on the first silicon film layer and the second silicon film layer as the source / drain, a bit line is formed on the silicon substrate through a first mask material, a channel is formed through a second mask material, and a gate filling groove is formed on the outer wall of the channel to form a ring gate structure and a word line, thereby improving the alignment between the bit line, the channel, the source / drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0046] Figure 1 is a schematic diagram of a vertical gate all-around transistor structure provided by one or more exemplary embodiments of the present application;
[0047] Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application;
[0048] Figure 3is based on Figure 2 A schematic diagram of a process preparation flow on a silicon substrate provided by the illustrated embodiment;
[0049] Figure 4 is based on Figure 2 A schematic diagram of a process flow for forming a first mask material provided in the illustrated embodiment;
[0050] Figure 5 is based on Figure 2 A schematic diagram of a process flow for preparing a first etching groove provided in the illustrated embodiment;
[0051] Figure 6 is based on Figure 2 A schematic diagram of a process flow for preparing a bit line provided by an embodiment is shown;
[0052] Figure 7 is based on Figure 2 A schematic diagram of a process flow for forming a second mask material provided in the illustrated embodiment;
[0053] Figure 8 is based on Figure 2 A schematic diagram of a process flow for forming a second mask material provided in the illustrated embodiment;
[0054] Fig. 9 is a flow chart of a method for preparing a VGAA transistor provided by another exemplary embodiment of the present application;
[0055] Fig.10 is based on Fig. 9 The illustrated embodiment provides a schematic diagram of a process flow for lateral etching of a germanium silicon film layer;
[0056] Fig.11 is based on Fig. 9 A schematic diagram of a process flow for selectively epitaxially growing epitaxial silicon material provided by the illustrated embodiment;
[0057] Fig.12 is based on Fig. 9 A schematic diagram of a process flow for preparing mandrel etching provided by the illustrated embodiment;
[0058] Fig.13 is based on Fig. 9 A schematic diagram of the process flow of oxide filling provided by the illustrated embodiment;
[0059] Fig.14 is based on Fig. 9 A schematic diagram of a process flow for preparing a word line provided by an embodiment is shown;
[0060] Fig.15 is based on Fig. 9A schematic diagram of a process flow for preparing metal material deposition provided by the illustrated embodiment;
[0061] Fig.16 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0062] Fig.17 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0063] Fig.18 is a schematic diagram of a process for forming a stacked structure provided by one or more exemplary embodiments of the present application;
[0064] Fig.19 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0065] Fig. 20 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0066] Fig.21 It is a schematic diagram of a forming process of a stacking structure provided by one or more other exemplary embodiments of the present application.
[0067] Silicon substrate-00;
[0068] A first silicon film layer-11, a germanium silicon film layer-12, and a second silicon film layer-13;
[0069] First mask material -20, metal material -30, second mask material -40, gate material -50,
[0070] Silicon dielectric material -60, oxide material -70, epitaxial silicon material -80;
[0071] Mandrel material-41, side wall material-42. DETAILED DESCRIPTION
[0072] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0073] A gate-all-around FET is a transistor structure in which the gate material wraps around the periphery of the channel. Compared with planar GAA transistors, vertical GAA transistors have a small projected area, unlimited channel length, no contacted gate pitch (CGP) restrictions, good parasitic capacitance control, and are suitable for 3D integration.
[0074] In the related art, when manufacturing a VGAA transistor, the following processes are usually included:
[0075] First, a silicon film layer is provided as a source, and a silicon nanocolumn perpendicular to the silicon film layer is formed on the silicon film layer. After an isolation layer is deposited on the silicon film layer, a gate dielectric is deposited on the silicon nanocolumn and the silicon film layer, and a gate material is deposited on the surface of the gate dielectric. The coverage of the gate material on the upper surface of the silicon nanocolumn is etched, and the height of the silicon nanocolumn exceeds the coverage height of the gate material, and then an isolation layer is deposited to a height lower than the silicon nanocolumn. After silicon is deposited on the silicon nanocolumn as a drain, the source is set to contact with the lower source silicon film layer, the drain is set to contact with the drain silicon deposited on the upper layer, and the ring gate material is set to contact along the word line.
[0076] However, in the above-mentioned method, when materials such as bit lines and word lines are arranged, it is impossible to ensure accurate alignment of positions of the bit lines, source and drain regions, gate regions, channels, etc.
[0077] In an embodiment of the present application, a method for preparing a transistor is provided. Optionally, the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
[0078] First, the structure of the VGAA transistor in the embodiment of the present application is introduced.
[0079] In an embodiment of the present application, a transistor array is provided. The transistor array includes a plurality of transistor units arranged in an array; the transistor unit includes a first source / drain, a channel, a second source / drain, and a normally closed contact that are vertically distributed in sequence, and a gate material is wrapped around the channel of the transistor unit; the first source / drain of a plurality of first transistor units in a first queue is connected by coupling to an embedded bit line; the gate materials of a plurality of second transistor units in a second queue are connected, so that a word line is coupled to a plurality of second transistor units, wherein the first queue is a queue along a first array direction, and the second queue is a queue along a second array direction.
[0080] like Figure 1 As shown, the transistor array 100 includes a plurality of transistor cells 110 .
[0081] Each transistor unit 110 is connected to a bit line (BL) 111 through a source / drain 113 and a word line (WL) 112 through a gate 114. The gate 114 surrounds a channel 115, and a normally closed contact (NC) 116 contacts the source / drain 113. The source / drain 113 is a heavily doped material, and the channel is a lightly doped material or an undoped material.
[0082] Among them, multiple transistor units 110 in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units 110 in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
[0083] The word line WL112 is connected to the gate 114 as a gate line to turn on the transistor unit 110 ; the bit line BL111 is connected to the source / drain 113 as a data signal writing line. The gate 114 surrounds the channel 115 .
[0084] The normally open contact or normally closed contact 116 refers to the natural state without any external effect (such as power on), at which time the normally open contact is disconnected and the normally closed contact 116 is connected. In the embodiment of the present application, the source / drain 113 of the transistor unit 110 is connected to the normally closed contact as an example for explanation. If the source is connected to the bit line 111, the drain is connected to the normally closed contact 116; if the drain is connected to the bit line 111, the source is connected to the normally closed contact 116.
[0085] Combined with the above introduction to VGAA transistors, Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes the following steps.
[0086] Step 201 : stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate.
[0087] The first silicon film layer 11 is adjacent to the silicon substrate 00 .
[0088] That is, the stacking sequence is to first deposit the first silicon film layer 11 on the silicon substrate 00 , deposit the silicon germanium film layer 12 on the first silicon film layer 11 , and then deposit the second silicon film layer 13 on the silicon germanium film layer 12 .
[0089] The first silicon film layer 11 and the second silicon film layer 13 are used as the source / drain in the transistor, and doping is performed during the in-situ growth process of the first silicon film layer 11 and the second silicon film layer 13. The first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are deposited by in-situ growth, and the duration of the in-situ growth is controlled to control the thickness of the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13; and during the doping process, the ion implantation concentration of the first silicon film layer 11 and the second silicon film layer 13 is controlled.
[0090] Indicatively, Figure 3As shown, a first silicon film layer 11 , a germanium silicon film layer 12 , and a second silicon film layer 13 are sequentially deposited on a silicon substrate 00 from bottom to top.
[0091] Step 202, forming a plurality of columns of first mask material on the second silicon film layer along the bit line direction, and etching the areas of the silicon substrate, the first silicon film layer, the silicon germanium film layer and the second silicon film layer not covered by the first mask material to form a first etching groove along the bit line direction.
[0092] In some embodiments, photoresist (PR) is used as the first mask material 20, or other material combinations can be selected as the first mask material 20, and there is a certain etching selectivity between the first mask material 20 and silicon and silicon germanium. Optionally, a self-aligned double patterning technology (SADP) or a self-aligned quadruple patterning technology (SAQP) or other self-aligned multiple patterning (SAMP) technology is used to form multiple columns of the first mask material 20 on the second silicon film layer 13.
[0093] Among them, SADP is used as an example for explanation in this embodiment. SADP refers to the process of using non-photolithography process steps (thin film deposition, etching, etc.) to achieve spatial frequency doubling of the photolithography pattern after one photolithography is completed. Finally, another photolithography and etching are used to remove the redundant pattern, thereby realizing the process of forming a patterned mask material. In some embodiments, the SADP process includes: providing a material layer to be etched; forming a sacrificial photoresist layer on the material layer to be etched; curing the photoresist on the top and side walls of the sacrificial photoresist layer to form a cured photoresist shell; etching back the cured photoresist shell on the top of the sacrificial photoresist layer until the uncured internal sacrificial photoresist layer is exposed, and the cured photoresist shell located on the side walls of the internal sacrificial photoresist layer forms the pattern of the first mask material 20; removing the uncured internal sacrificial photoresist layer to obtain a plurality of columns of first mask materials 20 formed on the first silicon film layer 11.
[0094] Indicatively, Figure 4 As shown, a plurality of columns of first mask material 20 are formed on the second silicon film layer 13 along the bit line direction.
[0095] In some embodiments, when etching the area of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 that is not covered by the first mask material 20, the etching rate of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 is greater than the etching rate of the first mask material 20, so that the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are etched while sacrificing a small amount of the first mask material 20. The first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are penetrated during the etching process, and the silicon substrate 00 with a partial thickness is etched by controlling the etching time, without penetrating the silicon substrate 00.
[0096] In some embodiments, in order to prevent the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 from being affected by the metal material 30 during the process of generating the bit line, the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are isolated by oxide.
[0097] Optionally, first, the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 20 are etched to form candidate etching grooves along the bit line direction; an oxide material 70 is deposited to cover the inner and outer surfaces of the candidate etching grooves with the oxide material 70, and the oxide material 70 is used to isolate the reaction between the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 and the metal material 30; based on the candidate etching grooves, the areas in the silicon substrate 00 that are not covered by the first mask material 20 are etched to form a first etching groove along the bit line direction.
[0098] Indicatively, Figure 5 As shown, firstly, the regions not covered by the first mask material 20 in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 are etched by controlling the etching time to obtain candidate etching grooves, and then an oxide material 70, such as silicon dioxide (SiO 2 ), the oxide material 70 covers the inner and outer surfaces of the candidate etching groove, and the oxide and the silicon substrate 00 are continuously etched. By controlling the etching time, the silicon substrate 00 with a preset thickness requirement is etched to obtain a first etching groove.
[0099] Step 203: Fill the first etched groove with metal material and anneal to generate a bit line.
[0100] In some embodiments, a metal material 30, such as tungsten (W) material, is deposited at the bottom of the first etched groove, and the silicon substrate 00 is annealed to form a metal silicide as a bit line through annealing. Annealing refers to the process of diffusing metal into the silicon substrate 00 through ohmic contact to form a metal silicide.
[0101] In some embodiments, a silicon dielectric material 60 with a target height is first filled in the first etching groove. In some embodiments, the silicon dielectric material 60 can be implemented as a nitride material or an oxide material, which is not limited in this embodiment. Taking the nitride material as an example, the silicon dielectric material 60 can be implemented as silicon nitride (SiN), and the target height is less than the depth of the first etching groove in the silicon substrate 00. The metal material 30 is filled on the silicon dielectric material 60 and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material 60.
[0102] Optionally, a silicon dielectric material 60 is deposited in the first etching groove by ALD or chemical vapor deposition (CVD) and then polished, and then the silicon dielectric material 60 is etched to a target height by controlling the etching time. The etching rate of the silicon dielectric material 60 is greater than the etching rate of the first mask material 20.
[0103] Indicatively, Figure 6 As shown, first, the silicon dielectric material 60 is filled in the first etched groove and ground, and then the silicon dielectric material 60 of the target height in the first etched groove is retained by etching, and the target height is less than the depth of the first etched groove of the silicon substrate 00, that is, the upper plane of the silicon dielectric material 60 after etching is below the upper plane of the silicon substrate 00. Subsequently, the metal material 30 can be deposited on the silicon dielectric material 60 and ground, and then the metal material 30 in the first etched groove is retained by etching, and metal silicide is generated by annealing as a bit line.
[0104] Optionally, excess metal material 30 is removed by wet etching.
[0105] Step 204, forming a plurality of columns of second mask material on the second silicon film layer along the word line direction, and etching the areas of the second silicon film layer and the silicon germanium film layer not covered by the second mask material to form second etching grooves along the word line direction.
[0106] In some embodiments, the first mask material 20 is first etched away, and then the second mask material 40 is formed on the second silicon film layer 13 .
[0107] Optionally, the second mask material 40 is used to control the direction of word line generation. After the second mask material 40 is formed along the word line direction, the second silicon film layer 13 and the germanium silicon film layer 12 are etched. In some embodiments, the etching time is controlled so that the germanium silicon film layer 12 is etched, while the first silicon film layer 11 is not etched or is less etched.
[0108] In some embodiments, the silicon dielectric material 60 of the second height is filled in the first etching groove, wherein the upper plane of the silicon dielectric material 60 of the second height meets the plane distance requirement with the upper plane of the second silicon film layer 13, such as: the upper plane of the silicon dielectric material 60 and the upper plane of the first silicon film layer 11 are in the same plane or the distance is less than the distance threshold. The oxide material 70 is filled in the first etching groove, and a plurality of columns of the second mask material 40 are formed on the second silicon film layer 13 after the oxide material 70 is filled along the word line direction.
[0109] In some embodiments, when the silicon dielectric material 60 of the second height is filled in the first etching groove, the silicon dielectric material 60 exceeding the height of the second silicon film layer 13 is first filled and polished, and then the silicon dielectric material 60 is etched to the second height by controlling the etching time.
[0110] In some embodiments, since oxide is deposited on the surfaces of the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 in the above step 203, optionally, the silicon dielectric material 60 can be filled after etching away the oxide, or the silicon dielectric material 60 can be directly filled without removing the oxide. This embodiment is not limited to this.
[0111] Among them, the silicon dielectric material 60 is used as an etching stop line when etching along the word line direction, that is, when the second silicon film layer 13 and the germanium silicon film layer 12 are etched along the word line direction, the etching time is controlled until the upper surface of the silicon dielectric material 60 is etched and the etching is stopped.
[0112] In some embodiments, after depositing the silicon dielectric material 60 of the second height, the oxide material 70 is continuously deposited on the silicon dielectric material 60 to a height exceeding the second silicon film layer 13 and then ground flat. A plurality of columns of the second mask material 40 are formed on the oxide and second silicon film layer 13, and the areas of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 70 that are not covered by the second mask material 40 are etched to form a second etched groove along the word line direction.
[0113] Indicatively, Figure 7As shown, after the word line is generated, the silicon dielectric material 60 is filled in the first etched groove to a level higher than the second silicon film layer 13 by ALD / CVD / furnace method and the like, and then ground flat. In this embodiment, the silicon dielectric material 60 is filled after etching the oxide material 70 as an example for description. The ground silicon dielectric material 60 is etched until the upper plane corresponding to the silicon dielectric material 60 is flush with the contact surface of the first silicon film layer 11 and the silicon germanium film layer 12.
[0114] like Figure 8 As shown, the oxide material 70 is continuously deposited on the silicon dielectric material 60 to a level higher than the second silicon film layer 13 and then ground flat, and multiple rows of the second mask material 40 are formed on the oxide material 70 and the second silicon film layer 13 by SADP or SAQP. On the basis of the second mask material 40, the second silicon film layer 13, the silicon germanium film layer 12, and the area of the oxide material 70 not covered by the second mask material 40 are etched to form a second etched groove, wherein the etching rate of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 70 is greater than the etching rate of the second mask material 40.
[0115] In some embodiments, the second silicon film layer 13 , the germanium silicon film layer 12 , and the oxide material 70 are etched by dry etching or wet etching.
[0116] Step 205 , after a channel is generated based on the germanium silicon film layer, a gate filling groove is formed on the peripheral wall of the channel, and a gate material is filled in the gate filling groove by self-alignment to form a gate, thereby obtaining a vertical all-around gate transistor.
[0117] In some embodiments, after a channel is generated in the germanium silicon film layer 12 based on the second mask material 40, a gate material 50 (Gate) is filled in the second etched groove to obtain a gate surrounding the channel and generate a word line to obtain a vertical all-around gate transistor. Optionally, the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and other dielectric materials, as well as polysilicon, tantalum, aluminum, tungsten and other conductive materials.
[0118] To summarize, the method provided in this embodiment is to sequentially stack a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, with the first silicon film layer and the second silicon film layer as source / drain, to form a bit line on the silicon substrate through a first mask material, to form a channel through a second mask material, to form a gate filling groove on the outer wall of the channel, to form a ring gate structure and a word line by filling the gate filling groove with a gate material, thereby improving the alignment between the bit line, the channel, the source / drain, the word line, and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0119] In some embodiments, the second mask material 40 includes a mandrel material 41 and spacer materials 42 distributed on both sides of the mandrel material 41 , and a channel of the transistor is generated based on the mandrel material 41 and the spacer materials 42 distributed on both sides of the mandrel material 41 . Fig. 9 is a flow chart of a method for preparing a transistor provided by another exemplary embodiment of the present application, such as Fig. 9 As shown, the above step 205 can also be implemented as the following steps 2051 to 2057.
[0120] Step 2051, performing a lateral etching of a first thickness on the surface of the silicon germanium film layer on the silicon pillars obtained by etching the first etching groove and the second etching groove.
[0121] In some embodiments, the surface of the germanium silicon film layer 12 is laterally etched to a first thickness on the silicon pillar by a lateral atomic layer etching (ALE) process or a lateral wet etching or a lateral dry etching.
[0122] In some embodiments, the germanium silicon film layer 12 is firstly etched separately by lateral ALE, wherein in the etching process, there is a certain selectivity between the etching of the second silicon film layer 13 and the germanium silicon film layer 12, so that the etching rate of the germanium silicon film layer 12 is greater than the etching rate of the second silicon film layer 13. Then, the second silicon film layer 13 and the germanium silicon film layer 12 are etched by silicon etching to achieve lateral etching of a first thickness on the surface of the germanium silicon film layer 12.
[0123] Indicatively, Fig.10 As shown, the surface of the silicon germanium film layer 12 in the silicon pillar is initially etched by lateral etching, and then the second silicon film layer 13 and the silicon germanium film layer 12 are etched by silicon etching to achieve lateral etching of the first thickness on the surface of the silicon germanium film layer 12.
[0124] Step 2052: generating an epitaxial silicon material of a second thickness on the etched surface of the silicon germanium film layer.
[0125] The second thickness is smaller than the first thickness.
[0126] Epitaxial silicon material 80 is generated on silicon pillars and silicon dielectric material 60 by epitaxy; epitaxial silicon material 80 on the surface of first silicon film layer 11, second silicon film layer 13 and silicon dielectric material 60 is annealed to obtain epitaxial silicon material 80 of second thickness generated on the surface of silicon germanium film layer 12. The process growth rate of epitaxial silicon material is selective, that is, the epitaxial silicon rate on the surface of silicon pillars and silicon germanium material is faster, and the rate on dielectric material is very low, so the main epitaxial silicon exists on silicon pillars and silicon germanium material.
[0127] In some embodiments, intrinsic silicon, i.e., epitaxial silicon material 80, is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 by selective epitaxy. The selective epitaxy is to generate epitaxial silicon material 80 by reacting the precursor adsorbed on the silicon / silicon germanium material after depositing the precursor, while other materials will not adsorb the precursor, so epitaxial silicon material 80 will not be generated. By controlling the adsorption amount of the precursor or the duration of epitaxial growth, epitaxial silicon material 80 is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13, wherein the epitaxial silicon material 80 of the second thickness is generated on the surface of the silicon germanium film layer 12, and the epitaxial silicon material 80 on the surface of the first silicon film layer 11 and the second silicon film layer 13 is diffused into the silicon material by annealing, and is integrated with the source / drain, and the epitaxial silicon material 80 generated on the surface of the silicon germanium film layer 12 is retained.
[0128] Indicatively, Fig.11 As shown, epitaxial silicon material 80 is generated on the surfaces of the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 by selective epitaxy, and the epitaxial silicon material 80 on the surfaces of the first silicon film layer 11 and the second silicon film layer 13 is diffused by annealing, and the epitaxial silicon material 80 on the surface of the silicon germanium film layer 12 is retained to obtain the epitaxial silicon material 80 of the second thickness on the surface of the silicon germanium film layer 12. Fig.11 It can be seen that the second thickness is smaller than the first thickness.
[0129] The epitaxial silicon material 80 forms a channel of the transistor.
[0130] Step 2053, etching the portions of the second silicon film layer and the silicon germanium film layer covered by the mandrel material to split the silicon column into at least two sub-silicon columns.
[0131] In some embodiments, the mandrel material 41 and the spacer material 42 correspond to a certain etching selectivity ratio, so that during the etching process of the mandrel material 41 , only a small amount of sacrificial etching occurs on the spacer material 42 .
[0132] Optionally, the oxide material 70 is first filled between the silicon pillars, and the oxide material 70 not covered by the second mask material 40 is etched, and then the silicon dielectric material 60 is filled between the silicon pillars. It is worth noting that the silicon dielectric material 60 can be filled on the basis of etching the oxide material 70, or can be filled directly, or can be directly filled with the silicon dielectric material 60 without filling the oxide material 70, which is not limited in this embodiment.
[0133] After filling the silicon dielectric material 60, the portions of the second silicon film layer 13 and the silicon germanium film layer 12 covered by the mandrel material 41 are etched to expose the second silicon film layer 13 and the silicon germanium film layer 12 on the etched side surfaces of the sub-silicon pillars.
[0134] Indicatively, Fig.12As shown, firstly, oxide material 70 is filled between silicon pillars, and the oxide material 70 not covered by the second mask material 40 is etched, then silicon dielectric material 60 is filled, and the second silicon film layer 13 and silicon germanium film layer 12 covered by the mandrel material 41 are etched.
[0135] Step 2054, removing the silicon germanium film layer in at least two sub-silicon pillars, and filling with oxide material to obtain oxide material surrounding the epitaxial silicon material.
[0136] After the core shaft material 41 is etched, the germanium silicon film layer 12 on one side of the channel is exposed, and the other side of the channel is the oxide material 70. Therefore, the germanium silicon film layer 12 is etched and filled with the oxide material 70, so that the oxide material 70 can surround the epitaxial silicon material 80 and use the epitaxial silicon material 80 as a channel.
[0137] Indicatively, Fig.13 As shown, after etching the second silicon film layer 13 and the germanium silicon film layer 12 covered by the core shaft material 41, the germanium silicon film layer 12 in the sub-silicon pillars is removed by lateral etching, and the etched areas between the sub-silicon pillars are filled with oxide material 70, and the oxide material 70 not covered by the side wall material 42 is etched, thereby obtaining the oxide material 70 surrounding the epitaxial silicon material 80.
[0138] Step 2055, filling the second etched groove with silicon dielectric material.
[0139] In some embodiments, after etching the spacer material 42 , the area between the sub-silicon pillars that is not filled with the silicon dielectric material 60 is filled with the silicon dielectric material 60 to a level higher than the second silicon film layer 13 and then ground flat.
[0140] Step 2056, etching the oxide material to form a gate filling groove, and filling the gate material into the gate filling groove along the direction of the second etched groove.
[0141] In some embodiments, the silicon dielectric material 60 may be nitride, and the selectivity between oxide and nitride may be utilized to wet etch the oxide material 70 retained in the structure to form a gate filling groove, thereby replacing the oxide with the gate material 50 .
[0142] Step 2057, etching the gate material within the first height range, retaining the gate material within the second height range, and obtaining a vertical all-around gate transistor.
[0143] The first height range corresponds to the height range of the second silicon film layer 13 , that is, the gate material 50 on the surface of the source / drain is removed by etching, and the gate material 50 on the surface of the channel is retained.
[0144] Indicatively, Fig.14As shown, after etching the sidewall material 42 and the silicon dielectric material 60 in the same height range as the sidewall material 42, the silicon dielectric material 60 is filled between each sub-silicon pillar, and after etching the oxide material 70 on the sub-silicon pillar, the gate material 50 is filled along the word line direction, and the gate material 50 in the height range corresponding to the second silicon film layer 13 is etched, and the gate material 50 in the height range corresponding to the channel is retained.
[0145] In some embodiments, after etching the gate material 50 within the first height range and retaining the gate material 50 within the second height range, a metal material 30 is deposited on the silicon pillar to contact the second silicon film layer 13 to obtain a vertical surrounding gate transistor.
[0146] like Fig.15 As shown, after the metal material 30 is deposited on the surface of the second silicon film layer 13, a silicon dielectric material 60 is filled to obtain a vertical surrounding gate transistor.
[0147] To summarize, the method provided in this embodiment, through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source / drain, on the basis of forming a bit line on the silicon substrate through a first mask material, a channel is formed through a second mask material, and a gate filling groove is formed on the outer wall of the channel to form a ring gate structure and a word line, thereby improving the alignment between the bit line, the channel, the source / drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0148] The method provided in this embodiment is based on the epitaxial VGAA transistor process flow, generates epitaxial silicon material as a channel and fills the gate material to surround it, thereby improving the alignment between the channel and the word line and the gate and improving the process accuracy.
[0149] The method provided in this embodiment utilizes oxide to perform a self-aligned replacement metal gate process, thereby improving the accuracy of generating gate materials.
[0150] based on Figure 2 In the method embodiment shown, when executing step 201 , well isolation is also formed in the stack structure.
[0151] In one embodiment, in conjunction with reference Fig.16 , Fig.16 Part (A1) shows the stack structure after well isolation is formed. Fig.16Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 00, a first silicon film layer 11, a germanium silicon film layer 12 and a second silicon film layer 13. Further, the silicon substrate 00 includes an upper silicon substrate 00-1 and a lower silicon substrate 00-2. Optionally, the lower silicon substrate 00-2 is doped to N type, the upper silicon substrate 00-1 is doped to P type, and the first silicon film layer 11 is doped to P type. Optionally, the lower silicon substrate 00-2 is doped to P type, the upper silicon substrate 00-1 is doped to N type, and the first silicon film layer 11 is doped to N type.
[0152] It can be noted that Fig.16 Part (B1) shows the three-dimensional structure of multiple first silicon pillars 1601 obtained after considering well isolation. Fig.16 Part (B2) shows a plan view corresponding to the three-dimensional structure. At this time, the longitudinal etching depth of the first silicon pillar 1601 only reaches the upper part of the silicon substrate 00-1, and multiple first silicon pillars 1601 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
[0153] In one embodiment, in conjunction with reference Fig.17 , Fig.17 Part (A1) shows the stack structure after well isolation is formed. Fig.17 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 00, a first silicon film layer 11, a germanium silicon film layer 12, a second silicon film layer 13, and a third silicon film layer 14 located between the silicon substrate 00 and the first silicon film layer. Optionally, the silicon substrate 00 is doped to P type, and the first silicon film layer 11 and the third silicon film layer 14 are doped to N type.
[0154] It can be noted that Fig.17 Part (B1) shows the three-dimensional structure of multiple first silicon pillars 1601 obtained after considering well isolation. Fig.17 At this time, the longitudinal etching depth of the first silicon pillar 1601 only reaches the third silicon film layer 14, and the plurality of first silicon pillars 1601 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
[0155] Illustratively, the following four possible implementations are provided for the above step 201.
[0156] A first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type, and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into P-type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0157] Combined with reference Fig.18 , Fig.18 Part (A) shows a silicon substrate 00; Fig.18 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 00 - 1 doped with N type and an upper portion of the silicon substrate 00 - 2 doped with P type. Fig.18 Part (C) shows the stacked first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13, and the first silicon film layer 11 is doped to P type.
[0158] A second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into N type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0159] Combined with reference Fig.19 , Fig.19 Part (A) shows a silicon substrate 00; Fig.19 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 00 - 1 doped with a P type and an upper portion of the silicon substrate 00 - 2 doped with an N type. Fig.19 Part (C) shows the stacked first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13, and the first silicon film layer 11 is doped to N type.
[0160] A third possible implementation method is to obtain a silicon substrate; dope the silicon substrate to N-type; sequentially stack a third silicon layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon layer and the first silicon film layer to P-type.
[0161] Combined with reference Fig. 20 , Fig. 20 Part (A) shows a silicon substrate 00; Fig. 20 Part (B) shows a silicon substrate 00 doped to N type. Fig. 20 Part (C) shows the stacked third silicon film layer 14, the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13. The third silicon film layer 14 is doped to P type, and the first silicon film layer 11 is doped to P type.
[0162] A fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon film layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon film layer and the first silicon film layer into N type.
[0163] Combined with reference Fig.21 , Fig.21 Part (A) shows a silicon substrate 00; Fig.21 Part (B) shows a silicon substrate 00 doped to a P type. Fig.21 Part (C) shows the stacked third silicon film layer 14, the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13. The third silicon film layer 14 is doped to N type, and the first silicon film layer 11 is doped to N type.
[0164] The embodiment of the present application provides an electronic device, which includes a logic device, and the logic device includes a transistor array as provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc. The transistor array is prepared by the process preparation method of the transistor provided in the above embodiment.
[0165] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0166] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.
[0167] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0168] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a transistor, characterized in that: The method comprises: A first silicon film layer (11), a germanium silicon film layer (12), and a second silicon film layer (13) are sequentially stacked on a silicon substrate (00), wherein the first silicon film layer (11) is adjacent to the silicon substrate (00); Forming a plurality of columns of first mask material (20) on the second silicon film layer (13) along the bit line direction, and etching the silicon substrate (00), the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) in areas not covered by the first mask material (20) to form a first etching groove along the bit line direction; Filling the first etching groove with a metal material (30) and annealing to generate a bit line; Forming a plurality of columns of second mask material (40) on the second silicon film layer (13) along the word line direction, and etching the second silicon film layer (13) and the region of the silicon germanium film layer (12) not covered by the second mask material (40) to form a second etching groove along the word line direction; After a channel is generated based on the germanium silicon film layer (12), a gate filling groove is formed on the peripheral wall of the channel, and a gate is formed in the gate filling groove by self-aligning and filling a gate material (50) to obtain a vertical all-around gate transistor.
2. The method according to claim 1, characterized in that The step of filling the first etching groove with a metal material (30) and annealing to generate a bit line comprises: Filling the first etching groove with the silicon dielectric material (60) to obtain a target height, wherein the target height is less than the depth of the first etching groove in the silicon substrate (00); The metal material (30) is filled on the silicon dielectric material (60) and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material (60).
3. The method according to claim 1, characterized in that The etching of the areas of the silicon substrate (00), the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) that are not covered by the first mask material (20) to form a first etching groove along the bit line direction comprises: Etching the areas of the first silicon film layer (11), the germanium silicon film layer (12) and the second silicon film layer (13) that are not covered by the first mask material (20) to form candidate etching grooves along the bit line direction; Depositing an oxide material (70), wherein the oxide material (70) covers the inner surface and the outer surface of the candidate etching groove, and the oxide material (70) is used to isolate the reaction between the first silicon film layer (11), the germanium silicon film layer (12), and the second silicon film layer (13) and the metal material (30); Based on the candidate etching groove, an area in the silicon substrate (00) not covered by the first mask material (20) is etched to form the first etching groove along the bit line direction.
4. The method according to claim 1, characterized in that: The step of forming a plurality of columns of second mask material (40) on the second silicon film layer (13) along the word line direction comprises: forming the silicon dielectric material (60) at a second height in the first etching groove, wherein the upper plane of the silicon dielectric material (60) at the second height and the upper plane of the first silicon film layer (11) meet the plane requirement; An oxide material (70) is filled in the first etching groove, and a plurality of columns of second mask material (40) are formed along the word line direction on the second silicon film layer (13) filled with the oxide material (70).
5. The method according to claim 4, characterized in that The second mask material (40) comprises a mandrel material (41) and sidewall materials (42) distributed on both sides of the mandrel material (41); The step of generating a channel based on the germanium silicon film layer (12) comprises: On the silicon pillars obtained by etching the first etching grooves and the second etching grooves, performing lateral etching of a first thickness on the surface of the germanium silicon film layer (12); generating an epitaxial silicon material (80) of a second thickness on the etched surface of the germanium silicon film layer (12), wherein the second thickness is less than the first thickness; Etching the second silicon film layer (13) and the portion of the silicon germanium film layer (12) covered by the mandrel material (41) to split the silicon column into at least two sub-silicon columns; The germanium silicon film layer (12) in the at least two sub-silicon pillars is removed and filled with an oxide material (70) to obtain the oxide material (70) surrounding the epitaxial silicon material (80), and the epitaxial silicon material (80) forms a channel of the transistor.
6. The method according to claim 5, characterized in that The step of generating an epitaxial silicon material (80) of a second thickness on the etched surface of the germanium silicon film layer (12) comprises: epitaxially growing the epitaxial silicon material (80) on the silicon pillar and the silicon dielectric material (60); The epitaxial silicon material (80) on the surface of the second silicon film layer (13) and the silicon dielectric material (60) is etched to obtain an epitaxial silicon material (80) of a second thickness generated on the surface of the germanium silicon film layer (12).
7. The method according to claim 5, characterized in that The method comprises forming a gate filling groove on the outer peripheral wall of the channel, and forming a gate in the gate filling groove by self-aligning and filling a gate material (50) to obtain a vertical all-around gate transistor, comprising: Filling the second etching groove with a silicon dielectric material (60); Etching the oxide material (70) to form the gate filling groove, and filling the gate material (50) into the gate filling groove along the direction of the second etched groove; The gate material (50) within a first height range is etched to retain the gate material (50) within a second height range, thereby obtaining the vertical all-around gate transistor, wherein the first height range corresponds to the height range of the second silicon film layer (13).
8. The method according to claim 7, characterized in that After etching the gate material (50) within the first height range to leave the gate material (50) within the second height range, the method further comprises: A metal material (30) is deposited on the silicon pillar in contact with the second silicon film layer (13).
9. A transistor array, characterized in that: The transistor array includes a plurality of transistor units arranged in an array; The transistor unit comprises a first source / drain, a channel, a second source / drain, and a normally closed contact which are vertically distributed in sequence, and the channel of the transistor unit is surrounded by a gate material; The first sources / drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line; Gate materials of a plurality of second transistor units in a second queue are connected to form a word line, wherein the first queue is a queue along a first array direction, and the second queue is a queue along a second array direction, and the first array direction intersects with the second array direction.
10. An electronic device, characterized in that: The electronic device comprises a logic device, and the logic device comprises the transistor array as claimed in claim 9.
11. The electronic device according to claim 10, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.