Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a p-type semiconductor body, an n-type buried layer on the p-type semiconductor body, and a p-type semiconductor layer on the n-type buried layer. The DTI region penetrates the p-type semiconductor layer and the n-type buried layer and reaches the p-type semiconductor body. An n-type semiconductor region as a cathode region of the Zener diode and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed below the n-type semiconductor region and a p-type second semiconductor region formed below the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. The impurity concentration of the p-type second semiconductor region is higher than that of the p-type first semiconductor region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-110639 filed on July 5, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be applied to a semiconductor device including a Zener diode and a method for manufacturing the same, for example.

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-183039

[0006] Patent Document 1 discloses a semiconductor device including a Zener diode. Summary of the invention

[0007] Improved performance is desirable in semiconductor devices including Zener diodes.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] According to one embodiment, a semiconductor device includes a semiconductor substrate and an element isolation region. The semiconductor substrate includes a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type formed on the substrate region, and a second semiconductor layer of a first conductivity type formed on the first semiconductor layer. The element isolation region penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region. A cathode region of a second conductivity type and an anode region of a first conductivity type of a Zener diode are formed in the second semiconductor layer. The anode region includes a first semiconductor region of a first conductivity type formed below the cathode region and a second semiconductor region of a first conductivity type formed below the first semiconductor region. A first PN junction is formed between the first semiconductor region and the cathode region. The impurity concentration of the second semiconductor region is higher than the impurity concentration of the first semiconductor region.

[0010] According to one embodiment, the performance of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a main portion cross-sectional view of the semiconductor device in the first embodiment.

[0012] Figure 2 1 is a main portion cross-sectional view showing manufacturing steps of the semiconductor device in the first embodiment.

[0013] Figure 3 yes Figure 2 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0014] Figure 4 yes Figure 3 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0015] Figure 5 yes Figure 6 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0016] Figure 6 yes Figure 5 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0017] Figure 7 yes Figure 6 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0018] Figure 8 yes Figure 7 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0019] Fig. 9 yes Figure 8 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0020] Fig.10 yes Fig. 9 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0021] Fig.11 yes Fig.10 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0022] Fig.12 yes Fig.11 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0023] Fig.13 yes Fig.12 A cross-sectional view of essential parts of a subsequent manufacturing step of a semiconductor device.

[0024] Fig.14 is a main portion cross-sectional view of the semiconductor device in the first inspection example.

[0025] Fig.15 is a main portion cross-sectional view of a semiconductor device in a second inspection example.

[0026] Fig.16is a main portion cross-sectional view of a semiconductor device in a third inspection example.

[0027] Fig.17 is an explanatory diagram of the semiconductor device in the first embodiment.

[0028] Fig.18 is a graph showing the operating characteristics of the Zener diode in the first inspection example.

[0029] Fig.19 is a graph showing the operating characteristics of the Zener diode in the first embodiment.

[0030] Fig. 20 is a main portion cross-sectional view of the semiconductor device in the second embodiment.

[0031] Fig.21 is a main portion cross-sectional view of the semiconductor device in the third embodiment.

[0032] Fig. 22 is a main portion cross-sectional view of a semiconductor device in a fourth embodiment.

[0033] Fig.23 is an explanatory diagram showing an example of use of a semiconductor device.

[0034] Fig.24 is an explanatory diagram showing an example of use of a semiconductor device.

[0035] Fig.25 is an explanatory diagram showing an example of use of a semiconductor device.

[0036] Fig.26 is an explanatory diagram showing an example of use of a semiconductor device. DETAILED DESCRIPTION

[0037] In the following embodiments, when it is convenient to require, it will be described by being divided into multiple parts or embodiments, but unless otherwise specified, they are not independent of each other, and one is related to the example, details, supplementary description, etc. of the modification of other parts or all. In the following embodiments, the number of elements, etc. (including the number of elements, numerical value, quantity, scope, etc.) is not limited to a specific number, but may be not less than or equal to a specific number, unless in principle the number is particularly indicated or clearly limited to the case of a specific number. In addition, in the following embodiments, it is needless to say that, unless they are particularly indicated and in principle considered to be obviously indispensable, the constituent elements (including element steps, etc.) are not necessarily indispensable. Similarly, in the following embodiments, when referring to shape, positional relationship and similar elements, etc., unless they are particularly indicated and in principle considered to be obvious, etc., it is assumed that the shape, etc. are substantially similar to or similar to the shape, etc. The same content applies to the numerical value and scope above.

[0038] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In all the drawings for explaining the embodiments, components having the same function are represented by the same reference numerals, and their repeated descriptions are omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary.

[0039] In the drawings used in the embodiments, in order to make the drawings easier to see, the hatching lines may be omitted even in the case of the cross-sectional views. Even in the case of the plan views, the hatching lines may be used to make the drawings easier to see.

[0040] The plan view also corresponds to a view viewed from a plane substantially parallel to the main surface or back surface of the semiconductor substrate SUB. Bottom surface and lower surface also have the same meaning. The height position also corresponds to the distance from the back surface of the semiconductor substrate SUB. The depth position also corresponds to the distance from the main surface of the semiconductor substrate SUB.

[0041] In this application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) includes not only MOSFET using an oxide film as a gate dielectric film, but also MOSFET using a dielectric film other than an oxide film as a gate dielectric film. LDMOSFET may also be referred to as HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor).

[0042] First embodiment

[0043] The structure of semiconductor devices

[0044] The semiconductor device of the present embodiment will be described with reference to the drawings. Figure 1 is a cross-sectional view of a main portion of the semiconductor device according to the present embodiment.

[0045] like Figure 1 As shown in , the semiconductor device of the present embodiment includes a semiconductor substrate SUB, an STI region 3, a DTI region 5, a p-type well PW1, a p-type semiconductor region AD1, a p-type semiconductor region AD2, a p-type semiconductor region PR, and an n-type semiconductor region CD.

[0046] like Figure 1 As shown in FIG. 1 , the semiconductor substrate SUB includes a p-type substrate body SB, an n-type buried layer NBL formed on the p-type substrate body SB, and a p-type semiconductor layer EP formed on the n-type buried layer NBL.

[0047] The p-type substrate body SB is made of, for example, p-type single crystal silicon into which p-type impurities such as boron (B) are introduced. The n-type buried layer NBL is an n-type semiconductor layer. The n-type buried layer NBL is formed in a layer in the upper part of the p-type substrate body SB. The p-type substrate body SB below the n-type buried layer NBL is a p-type substrate region. The p-type semiconductor layer EP is made of, for example, p-type single crystal silicon formed by epitaxial growth on the n-type buried layer NBL.

[0048] Here, the semiconductor substrate SUB includes a Zener diode forming region 1A and a transistor forming region 1B. The Zener diode forming region 1A includes a Zener diode. The transistor forming region 1B includes a transistor element. The Zener diode forming region 1A and the transistor forming region 1B are provided at different positions on the main surface of the semiconductor substrate SUB. A cross-sectional view of the Zener diode forming region 1A is shown in FIG. Figure 1 A cross-sectional view of the Zener diode forming region 1A and the transistor forming region 1B is shown in FIG. Figures 2 to 13 These drawings will be described below.

[0049] The main surface of the semiconductor substrate SUB corresponds to the main surface of the semiconductor layer EP. The back surface of the semiconductor substrate SUB also corresponds to the back surface of the p-type substrate body SB. The main surface of the semiconductor substrate SUB and the back surface of the semiconductor substrate SUB are located on opposite sides of each other.

[0050] At the main surface of the semiconductor substrate SUB, there is formed an STI (Shallow Trench Isolation) region 3. The STI region 3 is formed of a dielectric film such as a silicon oxide film embedded in the trench 2 formed in the semiconductor layer EP.

[0051] At the main surface of the semiconductor substrate SUB, there is also formed a DTI (deep trench isolation) region 5. The DTI region 5 is formed of a dielectric film such as a silicon oxide film embedded in a dielectric film IL formed on the semiconductor substrate SUB, and is formed in the semiconductor substrate SUB. The DTI region 5 serves as an element isolation region.

[0052] The depth of the DTI region 5 is greater than the depth of the STI region 3. That is, the height position of the bottom surface of the DTI region 5 is lower than the height position of the bottom surface of the STI region 3. The STI region 3 does not reach the n-type buried layer NBL. The DTI region 5 penetrates the semiconductor layer EP and the n-type buried layer NBL and reaches the p-type substrate body SB. The bottom surface of the DTI region 5 is located in the middle of the thickness of the p-type substrate body SB.

[0053] In the present embodiment, the trench 4 and the DTI region 5 penetrate the dielectric film IL, and part of the DTI region 5 is located in the trench 4 of the dielectric film IL. The trench 4 may be formed in the semiconductor substrate SUB without penetrating the dielectric film IL. In that case, the DTI region 5 is embedded in the trench 4 of the semiconductor substrate SUB, and the height position of the upper surface of the DTI region 5 is approximately the same as the height position of the main surface of the semiconductor substrate SUB.

[0054] In a plan view, the DTI region 5 is provided so as to surround the Zener diode formation region 1A. That is, in a plan view, the semiconductor layer EP and the n-type buried layer NBL in the Zener diode formation region 1A are surrounded by the DTI region 5. The DTI region 5 electrically isolates the semiconductor layer EP and the n-type buried layer NBL in the Zener diode formation region 1A from the semiconductor layer EP and the n-type buried layer NBL located outside the Zener diode formation region 1A.

[0055] A p-type well region PW1, a p-type semiconductor region AD1, a p-type semiconductor region AD2, a p-type semiconductor region PR, and an n-type semiconductor region CD are formed in the semiconductor substrate SUB. Specifically, in the Zener diode formation region 1A, the p-type well region PW1 is formed in the semiconductor layer EP. The p-type semiconductor region AD1, the p-type semiconductor region AD2, the p-type semiconductor region PR, and the n-type semiconductor region CD are formed in the p-type well region PW1.

[0056] The p type well region PW1 is formed at an upper portion of the semiconductor layer EP. The p type semiconductor layer EP disposed between the bottom surface of the p type well region PW1 and the upper surface of the n type buried layer NBL is the p type semiconductor region EP1.

[0057] The n-type semiconductor region CD is formed in the upper portion of the p-type well region PW1. The n-type semiconductor region CD is in contact with the main surface of the semiconductor substrate SUB and is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. The n-type semiconductor region CD serves as an n-type cathode region of the Zener diode.

[0058] The p-type semiconductor region AD1 is formed below the n-type semiconductor region CD. The p-type semiconductor region AD2 is formed below the p-type semiconductor region AD1. The p-type impurity concentration of the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type semiconductor region AD1. The p-type impurity concentration of the p-type semiconductor region AD1 is higher than the p-type impurity concentration of the p-type well region PW1. The p-type impurity concentration of the p-type well region PW1 is higher than the p-type impurity concentration of the p-type semiconductor layer EP below the p-type well region PW1. In other words, the p-type impurity concentration of the p-type well region PW1 is higher than the p-type impurity concentration of the p-type semiconductor layer EP1. The p-type semiconductor region AD1, the p-type semiconductor region AD2, and the p-type well region PW1 are electrically connected to each other.

[0059] The n-type semiconductor region CD and the p-type semiconductor region AD1 are adjacent to each other in a direction from the main surface to the back surface of the semiconductor substrate SUB, and a PN junction is formed between the n-type semiconductor region CD and the p-type semiconductor region AD1.

[0060] In the direction from the main surface of the semiconductor substrate SUB to the back surface, the p-type semiconductor region AD1 and the p-type semiconductor region AD2 are adjacent to each other. The planar dimensions (areas) of the p-type semiconductor region AD1 and the p-type semiconductor region AD2 may be approximately the same, but may also be different. In a plan view, the p-type semiconductor region AD1 and the p-type semiconductor region AD2 overlap each other.

[0061] In a plan view, the n-type semiconductor region CD also includes a p-type semiconductor region AD1, and the planar size of the p-type semiconductor region AD1 is smaller than the planar size of the n-type semiconductor region CD. Therefore, the central portion of the bottom surface of the n-type semiconductor region CD contacts the p-type semiconductor region AD1, and the peripheral portion of the bottom surface of the n-type semiconductor region CD contacts the p-type well region PW1. In other words, the central portion of the bottom surface of the n-type semiconductor region CD is covered by the p-type semiconductor region AD1, and the peripheral portion of the bottom surface of the n-type semiconductor region CD is covered by the p-type well region PW1. A PN junction is also formed between the n-type semiconductor region CD and the p-type well region PW1.

[0062] The depth of the bottom surface of the p-type semiconductor region AD2 is shallower than the depth of the bottom surface of the p-type well region PW1. The side surface of the p-type semiconductor region AD1, the side surface of the p-type semiconductor region AD2, and the bottom surface of the p-type semiconductor region AD2 are covered by the p-type well region PW1.

[0063] The p-type semiconductor region formed by the p-type semiconductor region AD1, the p-type semiconductor region AD2, and the p-type well region PW1 serves as a p-type anode region of the Zener diode. The PN junction surface formed at the interface between the n-type cathode region and the p-type anode region is configured by the PN junction surface between the n-type semiconductor region CD and the p-type semiconductor region AD1 and the PN junction surface between the n-type semiconductor region CD and the p-type well region PW1. In a plan view, the PN junction surface between the n-type semiconductor region CD and the p-type semiconductor region AD1 is surrounded by the PN junction surface between the n-type semiconductor region CD and the p-type well region PW1.

[0064] Since the p-type impurity concentration of the p-type semiconductor region AD1 is higher than the p-type impurity concentration of the p-type well region PW1, the breakdown of the Zener diode occurs at the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD1. Therefore, the withstand voltage of the Zener diode is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD1.

[0065] The p-type semiconductor region PR is formed in the upper portion of the p-type well region PW1. The p-type semiconductor region PR contacts the main surface of the semiconductor substrate SUB and is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. In a plan view, the p-type semiconductor region PR is formed, for example, so as to surround the n-type semiconductor region CD. The p-type semiconductor region PR and the n-type semiconductor region CD are arranged so as not to overlap each other in a plan view. The depth of the bottom surface of the p-type semiconductor region PR is shallower than the depth of the bottom surface of the p-type well region PW1. The bottom surface of the p-type semiconductor region PR is covered by the p-type well region PW1. The p-type impurity concentration of the p-type semiconductor region PR is higher than the p-type impurity concentration of the p-type well region PW1.

[0066] The STI region 3 is also provided between the n-type semiconductor region CD and the p-type semiconductor region PR in a plan view. Therefore, the side surface of the n-type semiconductor region CD and the side surface of the p-type semiconductor region PR are covered by the STI region 3.

[0067] A back surface electrode (not shown) may also be formed on the back surface of the semiconductor substrate SUB. The back surface electrode may supply, for example, a ground potential to the substrate body SB.

[0068] like Figure 1As shown in , the semiconductor device of the present embodiment further includes a dielectric film IL, a plurality of plugs PG, and a plurality of wirings M1.

[0069] A dielectric film IL is formed on a main surface of a semiconductor substrate SUB. The dielectric film IL1 is formed of, for example, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film. A plurality of contact holes are formed in the dielectric film IL, and a plurality of conductive plugs PG are formed in the plurality of contact holes. The plurality of conductive plugs PG include plugs PGA and plugs PGC. Plug PGA is disposed on a p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR. Plug PGC is disposed on an n-type semiconductor region CD and is electrically connected to the n-type semiconductor region CD.

[0070] In addition, a metal silicide layer (not shown) may be formed on the n-type semiconductor region CD and the p-type semiconductor region PR. In this case, the plug PGC contacts the metal silicide layer on the n-type semiconductor region CD and is electrically connected to the n-type semiconductor region CD via the metal silicide layer. The plug PGA also contacts the metal silicide layer on the p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR via the metal silicide layer.

[0071] A plurality of wirings M1 are formed on the dielectric film IL. The plurality of wirings M1 include an anode wiring M1A and a cathode wiring M1C. The cathode wiring M1C is electrically connected to the n-type semiconductor region CD via a plug PGC. The cathode potential is supplied from the cathode wiring M1C to the n-type cathode region of the Zener diode via the plug PGC. The anode wiring M1A is electrically connected to the p-type semiconductor region PR via the plug PGA, and is also electrically connected to the p-type well region PW1 via the p-type semiconductor region PR. The anode potential is supplied from the anode wiring M1A to the p-type anode region of the Zener diode via the plug PGA.

[0072] Illustration and description of the structures over the dielectric film IL and the wiring M1 are omitted.

[0073] In the present embodiment, the n-type cathode region and the p-type anode region of the Zener diode are formed in the semiconductor layer EP in the Zener diode formation region 1A surrounded by the DTI region 5 and the n-type buried layer NBL. Therefore, the Zener diode formed in the semiconductor substrate SUB can be electrically isolated from other semiconductor elements formed in the semiconductor substrate SUB. The other semiconductor elements formed in the semiconductor substrate SUB are, for example, transistor elements formed in the transistor formation region 1B.

[0074] Semiconductor device manufacturing steps

[0075] The manufacturing steps of the semiconductor device of the present embodiment will be described with reference to the drawings. Figures 2 to 131 is a main portion cross-sectional view in a manufacturing step of the semiconductor device of this embodiment.

[0076] First, if Figure 2 As shown in FIG. 1 , a semiconductor substrate SUB having a p-type substrate body SB, an n-type buried layer NBL on the p-type substrate body SB, and a p-type semiconductor layer EP on the n-type buried layer NBL is prepared. The p-type substrate body SB is formed of, for example, p-type single crystal silicon.

[0077] like Figure 2 As shown in FIG. 1 , the n-type buried layer NBL is formed adjacent to the interface between the substrate body SB and the semiconductor layer EP. The n-type buried layer NBL may be formed before the formation of the semiconductor layer EP. For example, after forming the n-type buried layer NBL in the surface layer of the p-type substrate body SB by ion implantation, the p-type semiconductor layer EP may be formed on the n-type buried layer NBL by a peripheral growth method.

[0078] Next, if Figure 3 As shown in FIG. 1 , the n-type drift region DF is formed in the semiconductor layer EP in the transistor formation region 1B using a method such as ion implantation. The n-type drift region DF is an n-type semiconductor region.

[0079] Next, if Figure 4 As shown in FIG. 1 , a photoresist pattern RP1 is formed on a main surface of a semiconductor substrate SUB.

[0080] Next, by using the photoresist pattern RP1 as a mask layer and performing the step of implanting p-type impurity ions into the semiconductor layer EP in the Zener diode formation region 1A twice, the p-type semiconductor region AD1 and the p-type semiconductor region AD2 are formed.

[0081] By the first ion implantation step, the p-type semiconductor region AD2 is formed, and by the second ion implantation step, the p-type semiconductor region AD1 is formed. The implantation energy of the first ion implantation step is greater than the implantation energy of the second ion implantation step. For example, the implantation energy of the first ion implantation step is, for example, 200 keV, and the implantation energy of the second ion implantation step is, for example, 50 keV. The dose of the first ion implantation step is also greater than the dose of the second ion implantation step.

[0082] The p-type impurity concentration of the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type semiconductor region AD1 , and the p-type semiconductor region AD2 is located below the p-type semiconductor region AD1 .

[0083] In the present embodiment, the p-type semiconductor region AD2 is formed by the first ion implantation step, and the p-type semiconductor region AD1 is formed by the second ion implantation step, but the p-type semiconductor region AD1 may be formed by the first ion implantation step, and the p-type semiconductor region AD2 may be formed by the second ion implantation step. In that case, the implantation energy of the second ion implantation step is greater than the implantation energy of the first ion implantation step, and the dose of the second ion implantation step is greater than the dose of the first ion implantation step.

[0084] In this way, the p-type semiconductor region AD2 is formed by ion implantation having greater implantation energy and dose than the ion implantation forming the p-type semiconductor region AD1. This allows the p-type semiconductor region AD2 having a higher p-type impurity concentration than the p-type semiconductor region AD1 to be formed at a deeper position than the p-type semiconductor region AD1. Therefore, the p-type semiconductor region AD2 having a higher p-type impurity concentration than the p-type semiconductor region AD1 is located below the p-type semiconductor region AD1.

[0085] Each of the p-type semiconductor region AD1 and the p-type semiconductor region AD2 is also formed by ion implantation using the photoresist pattern RP1 as a mask layer. Therefore, the planar dimensions (areas) of the p-type semiconductor region AD1 and the p-type semiconductor region AD2 are almost the same, but may be different. In a plan view, the p-type semiconductor region AD1 and the p-type semiconductor region AD2 overlap each other.

[0086] Subsequently, the photoresist pattern RP1 is removed by ashing or the like.

[0087] Next, if Figure 5 As shown in FIG. 1 , the STI region 3 is formed using an STI method.

[0088] After the trench 2 is formed at the main surface of the semiconductor substrate SUB, a dielectric film made of silicon oxide or the like is formed on the main surface of the semiconductor substrate SUB to fill the trench 2. Subsequently, using a method such as CMP (chemical mechanical polishing), the dielectric film located outside the trench 2 is removed. This allows the formation of the STI region 3 made of the dielectric film embedded in the trench 2.

[0089] Next, if Figure 6 As shown in FIG. 1 , an n-type semiconductor region NW1 is formed in the semiconductor layer EP in the transistor formation region 1B using a method such as ion implantation.

[0090] Next, if Figure 6As shown in FIG. 1 , using a method such as ion implantation, a p-type well region PW1 and a p-type well region PW2 are formed. The p-type well region PW1 and the p-type well region PW2 are each a p-type semiconductor region. In the Zener diode formation region 1A, the p-type well region PW1 is formed in the semiconductor layer EP. In the transistor formation region 1B, the p-type well region PW2 is formed in the semiconductor layer EP.

[0091] The p-type well region PW1 is formed above a predetermined depth from the main surface of the semiconductor substrate SUB. The p-type well region PW1 is also formed so as to include the p-type semiconductor region AD1 and the p-type semiconductor region AD2 in a plan view. The depth of the bottom surface of the p-type well region PW1 is deeper than the depth of the bottom surface of the p-type semiconductor region AD2. Therefore, each side surface of the p-type semiconductor region AD1, each side surface of the p-type semiconductor region AD2, and the bottom surface of the p-type semiconductor region AD2 are covered by the p-type well region PW1. The p-type impurity concentration of each region in the p-type semiconductor region AD1 and the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type well region PW1.

[0092] The p-type well region PW1 and the p-type well region PW2 may be formed by the same ion implantation step to reduce the number of manufacturing steps, but they may also be formed by separate ion implantation steps.

[0093] In the present embodiment, the p-type well region PW1 and the p-type well region PW2 are formed after the n-type semiconductor region NW1 is formed, but the n-type semiconductor region NW1 may be formed after the p-type well region PW1 and the p-type well region PW2 are formed.

[0094] Next, if Figure 7 As shown in FIG. 1 , the gate electrode GE is formed on the main surface of the semiconductor layer EP in the transistor formation region 1B via the gate dielectric film GF.

[0095] The gate electrode GE is formed of, for example, a polysilicon film, and the gate dielectric film GF is formed of, for example, a silicon oxide film.

[0096] Next, if Figure 8 As shown in FIG. 1 , an n-type semiconductor region CD, an n-type source region SR, and an n-type drain region DR are formed using a method such as ion implantation. The n-type source region SR serves as a source region of the LDMOSFET. The n-type drain region DR serves as a drain region of the LDMOSFET.

[0097] In the Zener diode forming region 1A, an n-type semiconductor region CD is formed in the semiconductor layer EP. The n-type semiconductor region CD is formed at a predetermined depth from the main surface of the semiconductor substrate SUB. By forming the n-type semiconductor region CD, the p-type semiconductor region AD1 is located below the n-type semiconductor region CD.

[0098] In the transistor formation region 1B, an n-type drain region DR is formed in the semiconductor layer EP, more specifically, in the n-type drift region DF. The n-type impurity concentration of the n-type drain region DR is higher than the n-type impurity concentration of the n-type drift region DF. In the transistor formation region 1B, an n-type source region SR is formed in the semiconductor layer EP, more specifically, in the p-type well region PW2. The n-type semiconductor region CD, the n-type source region SR, and the n-type drain region DR may be formed by the same ion implantation step to reduce the number of manufacturing steps, but they may also be formed by separate ion implantation steps.

[0099] Next, if Figure 8 As shown in FIG. 1 , a p-type semiconductor region PR and a p-type semiconductor region PC are formed using a method such as ion implantation. The p-type semiconductor region PR is formed in the semiconductor layer EP in the Zener diode formation region 1A, more specifically, in the p-type well region PW1. In the transistor formation region 1B, the p-type semiconductor region PC is formed in the semiconductor layer EP, more specifically, in the p-type well region PW2. The p-type semiconductor region PR and the p-type semiconductor region PC may be formed by the same ion implantation step to reduce the number of manufacturing steps, but they may also be formed by separate ion implantation steps.

[0100] In the present embodiment, the p-type semiconductor region PC and the p-type semiconductor region PR are formed after forming the n-type source region SR and the n-type drain region DR, but the n-type source region SR and the n-type drain region DR may be formed after forming the p-type semiconductor region PC and the p-type semiconductor region PR.

[0101] The n-type source region SR may also have an LDD (lightly doped drain) structure. In that case, after forming an n-type semiconductor region (not shown) for the LDD structure using ion implantation, a sidewall dielectric film (not shown) is formed on the sidewall of the gate dielectric film GF. Then, the n-type source region SR and the n-type drain region DR are formed using ion implantation. The n-type impurity concentration of the n-type semiconductor region for the LDD structure is lower than the n-type impurity concentration of the n-type source region SR and the n-type drain region DR, respectively.

[0102] In addition, after forming the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PR, and the p-type semiconductor region PC, a metal silicide layer (not shown) may be formed on the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PC, the gate electrode GE, the p-type semiconductor region PR, and the n-type semiconductor region CD. The metal silicide layer SL is formed using a silicide (self-aligned silicide) technique.

[0103] Next, if Figure 8 As shown in FIG. 1 , a dielectric film IL is formed on the main surface of the semiconductor substrate SUB to cover the gate electrode GE using a method such as CVD (Chemical Vapor Deposition). After the dielectric film IL is formed, the upper surface of the dielectric film IL may also be polished and planarized using a method such as CMP.

[0104] Next, if Fig.10 As shown in FIG. 1 , a photoresist pattern (not shown) is used as an etching mask and the dielectric film IL, the STI region 3 and the semiconductor substrate SUB are etched to form a trench 4. The trench 4 penetrates the dielectric film IL, the STI region 3, the semiconductor layer EP and the n-type buried layer NBL, and reaches the p-type substrate body SB.

[0105] Next, if Fig.11 As shown in FIG. 4 , the DTI region 5 is formed in the trench 4 .

[0106] After the trench 4 is formed, a dielectric film such as a silicon oxide film is formed on the dielectric film IL to fill the trench 4. Then, the dielectric film located outside the trench 4 is removed using a method such as CMP. This allows the formation of a DTI region 5 formed of a dielectric film embedded in the trench 4. A void can be formed in the DTI region 5. In the present embodiment, although the step of removing the dielectric film located outside the trench 4 using a method such as CMP is performed, this step is not necessary. In that case, the dielectric film formed integrally with the DTI region 5 remains on the dielectric film IL.

[0107] Next, if Fig.12 As shown in FIG. 1 , a plurality of contact holes penetrating the dielectric film IL are formed by using a photoresist pattern (not shown) formed on the dielectric film IL as an etching mask and etching the dielectric film IL. Subsequently, a plurality of conductive plugs PG are formed in the plurality of contact holes, respectively.

[0108] For example, a barrier conductor film is formed on the bottom surface of the contact hole, on the side surface of the contact hole, and on the upper surface of the insulating film IL. A main conductor film made of tungsten or the like is formed on the barrier conductor film to fill the contact hole. Subsequently, the main conductor film and the barrier conductor film located outside the contact hole are removed by a method such as CMP. This allows the formation of a plurality of plugs PG.

[0109] Next, if Fig.13 As shown in FIG. 1 , a plurality of wirings M1 are formed on the insulating film IL. For example, a conductive film is formed on the insulating film IL. Subsequently, by patterning the conductive film using a photolithography technique and an etching technique, a plurality of wirings M1 made of the conductive film can be formed. The plurality of wirings M1 are preferably aluminum wirings, but other metal material wirings, such as tungsten wirings, can also be applied. In addition, copper wirings formed using a damascene technique can also be used as the plurality of wirings M1.

[0110] The plurality of wirings M1 include an anode wiring M1A, a cathode wiring M1C, a source wiring M1S, and a drain wiring M1D.

[0111] The drain wiring M1D is electrically connected to the n-type drain region DR via the plug PG located on the n-type drain region DR. The source wiring M1S is electrically connected to the n-type source region SR via the plug PG located on the n-type source region SR, and is also electrically connected to the p-type semiconductor region PC via the plug PG located on the p-type semiconductor region PC. Therefore, the source potential supplied from the source wiring M1S to the n-type source region SR via the plug PG is supplied from the source wiring M1S to the p-type semiconductor region PC via the plug PG, and is also supplied from the p-type semiconductor region PC to the p-type well region PW2. The source wiring M1S, the drain wiring M1D, the cathode wiring M1C, and the anode wiring M1A are not connected to each other and are separated from each other.

[0112] Illustration and explanation of the steps of forming an upper insulating film and wirings are omitted.

[0113] Background Considerations

[0114] Fig.14 1 is a cross-sectional view of a main part of a semiconductor device of a first inspection example studied by the inventors. Figure 1 A cross section is shown at Fig.14 middle. Fig.14 Also shown are a parasitic NPN bipolar transistor TR101 and a parasitic PNP bipolar transistor TR102 formed in the semiconductor device of the first inspection example.

[0115] Fig.14 The semiconductor device of the first inspection example shown in FIG. 1 has a p-type semiconductor region AD101 instead of the above Figure 1The p-type semiconductor region AD1 and the p-type semiconductor region AD2 are shown in FIG. Fig.14 As shown in FIG. 1 , the p-type semiconductor region AD101 is formed below the n-type semiconductor region CD in the p-type well region PW1 . The p-type impurity concentration of the p-type semiconductor region AD101 is higher than the p-type impurity concentration of the p-type well region PW1 .

[0116] In the case of the first inspection example, the ion implantation step of the p type impurity using the above photoresist pattern RP1 as a mask layer is performed only once, and the p type semiconductor region AD101 is formed by this one ion implantation step.

[0117] exist Fig.14 In the first inspection example shown in , the n-type semiconductor region CD is used as the n-type cathode region of the Zener diode, and the p-type semiconductor region formed by the p-type semiconductor region AD101 and the p-type well region PW1 is used as the p-type anode region of the Zener diode. The withstand voltage of the Zener diode is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD101.

[0118] According to the study by the present inventors, it was found that the following problem occurs in the case of the first inspection example.

[0119] exist Fig.14 In the semiconductor device of the first inspection example shown in , a parasitic thyristor formed of a parasitic NPN bipolar transistor TR101 and a parasitic PNP bipolar transistor TR102 is formed.

[0120] The n-type buried layer NBL serves as an n-type collector region of the parasitic NPN bipolar transistor TR101. The p-type semiconductor region formed by the p-type semiconductor region AD101 and the p-type well region PW1 serves as a p-type base region of the parasitic NPN bipolar transistor TR101. The N-type semiconductor region CD serves as an n-type emitter region of the parasitic NPN bipolar transistor TR101.

[0121] The p-type substrate body SB also serves as a p-type collector region of the parasitic PNP bipolar transistor TR102. The n-type buried layer NBL serves as an n-type base region of the parasitic PNP bipolar transistor TR102. The p-type semiconductor region formed by the p-type semiconductor region AD101, the p-type well region PW1, and the p-type semiconductor region PR serves as a p-type emitter region of the parasitic PNP bipolar transistor TR102.

[0122] If a potential lower than the potential of the p-type substrate body SB is supplied to the n-type cathode region of the Zener diode as the n-type semiconductor region CD and the p-type anode region as the p-type well region PW1, there is a danger that the aforementioned parasitic thyristor will operate. This is because if such a potential is supplied to the n-type semiconductor region CD and the p-type well region PW1, the parasitic NPN bipolar transistor TR101 will be enabled first, and along with it, the parasitic PNP bipolar transistor TR102 will also operate.

[0123] When the parasitic thyristor is working, electrons flow from the semiconductor layer EP to the p-type substrate body SB in the Zener diode formation region 1A. From another perspective, the current flows from the p-type substrate body SB to the semiconductor layer EP in the Zener diode formation region 1A. Some electrons flowing from the semiconductor layer EP to the p-type substrate body SB recombine with holes in the p-type substrate body SB. The other part of the electrons flowing from the semiconductor layer EP to the p-type substrate body SB moves in the p-type substrate body SB, affecting other semiconductor elements formed on the semiconductor substrate SB, causing the performance of the semiconductor device to deteriorate. In order to improve the performance of the semiconductor device, it is expected to prevent the operation of the parasitic thyristor.

[0124] exist Fig.14 In the case of the first inspection example shown in FIG. 1 , it is considered that the operation of the parasitic thyristor can be suppressed by increasing the p-type impurity concentration of the p-type semiconductor region AD101. This is because if the p-type impurity concentration of the p-type semiconductor region AD101 is increased, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR101 will increase, making it difficult for the parasitic NPN bipolar transistor TR101 to operate.

[0125] The withstand voltage of the Zener diode is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD101. And by adjusting the p-type impurity concentration of the p-type semiconductor region AD101 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101, the withstand voltage of the Zener diode can be controlled. Therefore, the p-type impurity concentration of the p-type semiconductor region AD101 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 needs to be set according to the required withstand voltage of the Zener diode. The required withstand voltage of the Zener diode is the design value of the withstand voltage of the Zener diode. Therefore, since the p-type impurity concentration of the p-type semiconductor region AD101 needs to be set according to the required withstand voltage of the Zener diode, it is difficult to suppress the operation of the parasitic thyristor by increasing the p-type impurity concentration of the p-type semiconductor region AD101.

[0126] Fig.15 1 is a cross-sectional view of a main part of a semiconductor device of a second inspection example studied by the inventors. Fig.13 A cross section is shown at Fig.15 middle.

[0127] Fig.15 The semiconductor device of the second inspection example shown in has an n-type semiconductor region NC1 , an n-type semiconductor region NC2 , and a plug PGN.

[0128] The n-type semiconductor region NC1 and the n-type semiconductor region NC2 are formed in the semiconductor layer EP. The n-type semiconductor region NC1 and the n-type semiconductor region NC2 are in contact with each other. The n-type semiconductor region NC1 and the n-type buried layer NBL are in contact with each other. The plug PGN is formed on the n-type semiconductor region NC2. The n-type impurity concentration of the n-type semiconductor region NC2 is higher than the n-type impurity concentration of the n-type semiconductor region NC1. The plug PGN is electrically connected to the n-type buried layer NBL via the n-type semiconductor region NC2 and the n-type semiconductor region NC1.

[0129] exist Fig.15 In the second inspection example shown in , the same potential as that of the p-type semiconductor body SB can be supplied from the wiring M1N to the n-type buried layer NBL via the plug PGN and the n-type semiconductor region NC2 and the n-type semiconductor region NC1. Therefore, since the potential of the p-type semiconductor body SB and the potential of the n-type buried layer NBL are the same, the operation of the parasitic PNP bipolar transistor TR102 can be prevented. This can prevent the operation of the parasitic thyristor.

[0130] However, in Fig.15 In the second inspection example shown in , it is necessary to form the n-type semiconductor region NC1 and the n-type semiconductor region NC2 in the semiconductor layer EP. Therefore, the planar size of the Zener diode formation region 1A in the second inspection example becomes larger than the planar size of the Zener diode formation region 1A in the first inspection example, resulting in an increase in the planar size of the semiconductor device. For the miniaturization of the semiconductor device, it is not desirable to form the n-type semiconductor region NC1 and the n-type semiconductor region NC2 in the semiconductor layer EP in the Zener diode formation region 1A.

[0131] Fig.16 1 is a cross-sectional view of a main part of a semiconductor device of a third inspection example studied by the present inventors. Fig.16 In, corresponding to Fig.14 A cross section is shown.

[0132] exist Fig.16In the third inspection example shown in , the p-type semiconductor region AD101 is formed deeper than the p-type semiconductor region AD101 in the first inspection example. That is, the depth of the bottom surface of the p-type semiconductor region AD101 in the third inspection example is deeper than the depth of the bottom surface of the p-type semiconductor region AD101 in the first inspection example. The ion implantation energy used to form the p-type semiconductor region AD101 in the third inspection example is greater than the ion implantation energy used to form the p-type semiconductor region AD101 in the first inspection example.

[0133] exist Fig.16 In the case of the third inspection example shown in , the thickness of the p-type semiconductor region AD101 is greater than that of the p-type semiconductor region AD101 in the first inspection example. Therefore, in the case of the third inspection example, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR101 becomes higher than that of the first inspection example, making it difficult for the parasitic NPN bipolar transistor TR101 to operate. Therefore, in the case of the third inspection example, it is easier to suppress the operation of the parasitic thyristor in the first inspection example.

[0134] However, in Fig.16 In the case of the third inspection example shown in , it is difficult to control the p-type impurity concentration of the p-type semiconductor region AD101 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 as compared with the first inspection example. The reason is as follows.

[0135] When the p-type semiconductor region AD101 is formed by ion implantation, the p-type impurity concentration of the p-type semiconductor region AD101 near the bottom surface of the p-type semiconductor region AD101 can be simply controlled by adjusting the dose of the ion implantation. On the contrary, the p-type impurity concentration of the p-type semiconductor region AD101 at a position far from the bottom surface of the p-type semiconductor region AD101 may fluctuate, and it is difficult to control it to a desired concentration. In the case of the third inspection example, compared with the first inspection example, the distance from the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 to the bottom surface of the p-type semiconductor region AD101 is larger, making it difficult to control the p-type impurity concentration of the p-type semiconductor region AD101 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101. Therefore, in the case of the third inspection example, the withstand voltage of the Zener diode may fluctuate compared with the first inspection example. In order to improve the reliability of the semiconductor device, it is necessary to prevent the withstand voltage fluctuation of the Zener diode.

[0136] Main features and effects

[0137] The semiconductor device of the present embodiment has a semiconductor substrate SUB, which includes a p-type substrate region (p-type substrate body SB), an n-type buried layer (n-type semiconductor layer) NBL formed on the p-type substrate region, and a p-type semiconductor layer EP formed on the n-type buried layer NBL. The semiconductor of the present embodiment also includes a DTI region (element isolation region) 5 that penetrates the semiconductor layer EP and the n-type buried layer NBL and reaches the p-type substrate body SB, an n-type cathode region (n-type semiconductor region CD) of a Zener diode formed in the semiconductor layer EP, and a p-type anode region of a Zener diode formed in the semiconductor layer EP.

[0138] One of the main features of this embodiment is that the p-type anode region of the Zener diode includes a p-type semiconductor region AD1 formed below the n-type semiconductor region CD and a p-type semiconductor region AD2 formed below the p-type semiconductor region AD1. The PN junction of the Zener diode is formed between the p-type semiconductor region AD1 and the n-type semiconductor region CD. The p-type impurity concentration of the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type semiconductor region AD1.

[0139] Fig.17 is an explanatory diagram of the semiconductor device of this embodiment. Figure 1 The same cross section is shown in Fig.17 In. Fig.17 The hatching is omitted. Fig.17 Also shown are a parasitic NPN bipolar transistor TR1 and a parasitic PNP bipolar transistor TR2 formed in the semiconductor device of the present embodiment.

[0140] In the semiconductor device of the present embodiment, a parasitic thyristor formed of a parasitic NPN bipolar transistor TR1 and a parasitic PNP bipolar transistor TR2 is formed.

[0141] The n-type buried layer NBL serves as an n-type collector region of the parasitic NPN bipolar transistor TR1. The p-type semiconductor region formed by the p-type semiconductor region AD1, the p-type semiconductor region AD2, and the p-type well region PW1 serves as a p-type base region of the parasitic NPN bipolar transistor TR1. The N-type semiconductor region CD serves as an n-type emitter region of the parasitic NPN bipolar transistor TR1.

[0142] The p-type substrate body SB also serves as a p-type collector region of the parasitic PNP bipolar transistor TR2. The n-type buried layer NBL serves as an n-type base region of the parasitic PNP bipolar transistor TR2. The p-type semiconductor region formed by the p-type semiconductor region AD1, the p-type semiconductor region AD2, the p-type well region PW1, and the p-type semiconductor region PR serves as a p-type emitter region of the parasitic PNP bipolar transistor TR2.

[0143] In this embodiment, the p-type semiconductor region AD1 is formed to set the p-type impurity concentration of the p-type semiconductor region AD1 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 to a predetermined design concentration. Here, the design concentration is a concentration that can achieve the required withstand voltage of the Zener diode.

[0144] Since the depth of the bottom surface of the p-type semiconductor region AD1 is shallower than the depth of the bottom surface of the p-type semiconductor region AD2, the distance from the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 to the bottom surface of the p-type semiconductor region AD1 is small. Therefore, by adjusting the dose of ion implantation to form the p-type semiconductor region AD1, the p-type impurity concentration of the p-type semiconductor region AD1 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 can be simply set to a predetermined design concentration. Therefore, the withstand voltage of the Zener diode can be set to the required withstand voltage, and the fluctuation of the withstand voltage of the Zener diode can be suppressed.

[0145] Then, by forming a p-type semiconductor region AD2 having a higher p-type impurity concentration than the p-type semiconductor region AD1 below the p-type semiconductor region AD1, the p-type impurity concentration of the p-type anode region below the n-type semiconductor region CD becomes higher. This results in an increase in the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1, making it difficult for the parasitic NPN bipolar transistor TR1 to operate. Therefore, the operation of the parasitic NPN bipolar transistor TR1 can be suppressed or prevented.

[0146] That is, in the present embodiment, by forming the p-type semiconductor region AD1 below the n-type semiconductor region CD, the withstand voltage of the Zener diode can be set to the required withstand voltage. By forming the p-type semiconductor region AD2 having a higher p-type impurity concentration than the p-type semiconductor region AD1 below the p-type semiconductor region AD1, the parasitic thyristor can be suppressed. Therefore, the performance of the semiconductor device including the Zener diode can be improved. In addition, the reliability of the semiconductor device including the Zener diode can be improved.

[0147] Also, when ion implantation is performed on the semiconductor substrate SUB, if the dose of the ion implantation is large, there is a risk of damaging the semiconductor substrate SUB. The dose of the ion implantation for forming the p-type semiconductor region AD2 in the present embodiment is less than the dose of the ion implantation for forming the p-type semiconductor region AD101 in the third inspection example. This is because, in the third inspection example, the p-type impurity concentration near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 needs to be set to a predetermined design concentration, so it is necessary to increase the dose of the ion implantation for forming the p-type semiconductor region AD101. On the other hand, in the present embodiment, the p-type impurity concentration near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 is adjusted by the dose of the ion implantation for forming the p-type semiconductor region AD1. Therefore, in the present embodiment, the dose of the ion implantation for forming the p-type semiconductor region AD1 and the dose of the ion implantation for forming the p-type semiconductor region AD2 can be made smaller than the dose of the ion implantation for forming the p-type semiconductor region AD101 in the third inspection example. Therefore, damage to the semiconductor substrate SUB can be suppressed or prevented by the ion implantation for forming the p-type semiconductor region AD1 and the ion implantation for forming the p-type semiconductor region AD2. This can improve the reliability of the semiconductor device.

[0148] In the present embodiment, the potential of the n-type buried layer NBL is also a floating potential. The structure for supplying the power wiring M1 and the plug PG to the n-type buried layer NBL is not formed on the semiconductor substrate SUB. That is, Fig.15 The n-type semiconductor region NC1 and the n-type semiconductor region NC2 of the second inspection example in the embodiment are not formed in the Zener diode formation region 1A in the present embodiment. Therefore, in the case of the present embodiment, the plane size of the Zener diode formation region 1A can be made smaller than that in the second inspection example. Therefore, the semiconductor device can be miniaturized.

[0149] There is also a risk that when a potential lower than the potential of the P-type substrate body SB is applied to the n-type semiconductor region CD as the n-type cathode region of the Zener diode and the p-type well region PW1 as the p-type anode region, the parasitic thyristor will operate. In the present embodiment, by forming the p-type semiconductor region AD1 below the n-type semiconductor region CD and forming the p-type semiconductor region AD2 below the p-type semiconductor region AD1, the operation of the parasitic thyristor can be suppressed or prevented. Therefore, when the potential supplied from the plug PGC to the n-type semiconductor region CD and the potential supplied from the plug PGA to the p-type well region PW1 during the operation of the Zener diode are lower than the potential of the P-type substrate body SB, the semiconductor device of the present embodiment can be applied, and the effect is significant.

[0150] The potential of the P-type substrate body SB is generally still the ground potential. Therefore, when the Zener diode is working, if the potential supplied from the plug PGC to the n-type semiconductor region CD and the potential supplied from the plug PGA to the p-type well region PW1 are both negative, the semiconductor device of this embodiment can be applied and the effect is significant.

[0151] Also, when the Zener diode operates in the forward direction, the parasitic thyristor is more likely to operate than when the Zener diode operates in the reverse direction. Therefore, when the Zener diode operates, if the potential supplied from the plug PGA to the p-type well region PW1 is higher than the potential supplied from the plug PGC to the n-type semiconductor region CD, the semiconductor device of the present embodiment can be applied and the effect is significant.

[0152] Fig.18 is a graph showing the operating characteristics of the Zener diode of the first inspection example. Fig.19 is a graph showing the operating characteristics of the Zener diode of this embodiment. Fig.18 and Fig.19 In each of the graphs in FIG. 1 , a voltage VKA on a horizontal axis of the graph represents a difference between an anode voltage and a cathode voltage, and a vertical axis of the graph represents a current value. Fig.18 and Fig.19 The operating characteristics are shown when both the anode potential and the cathode potential are negative and the anode potential is higher than the cathode potential. Fig.18 and Fig.19 In each of the figures, the anode current of the Zener diode is shown by a dotted line, and the substrate current is shown by a dotted line. The anode current is the forward current of the Zener diode. The substrate current flows from the p-type substrate body SB to the semiconductor layer EP.

[0153] exist Fig.18 In the case of the first inspection example shown in FIG. 1 , the parasitic thyristor starts to operate at the operating point P1 shown in the diagram. When the voltage VKA is greater than the operating point P1, the substrate current flowing from the p-type substrate body SB to the semiconductor layer EP increases rapidly due to the operation of the parasitic thyristor. Therefore, the anode current of the Zener diode flows backward, and the current no longer flows from the anode region to the cathode region. Therefore, the normal operation of the Zener diode is constrained.

[0154] On the other hand, Fig.19 In the case of the present embodiment shown in FIG. 1 , the parasitic thyristor does not operate. That is, Fig.18 The operating point P1 shown in the diagram does not exist Fig.19 Therefore, the Zener diode is working properly.

[0155] Second embodiment

[0156] Fig. 20is a cross-sectional view of an essential part of a semiconductor device of a second embodiment. Fig. 20 The corresponding Fig.13 cross section.

[0157] like Fig. 20 As shown in , the semiconductor device of the second embodiment has a p-type semiconductor region PS1 and a p-type resurf layer RE.

[0158] like Fig. 20 As shown in FIG. 1 , in the Zener diode formation region 1A, a p-type semiconductor region PS1 is formed in the semiconductor layer EP. The p-type semiconductor region PS1 is located below the p-type well region PW1. That is, the p-type semiconductor region PS1 is formed in the p-type semiconductor layer EP below the p-type well region PW1. In the second embodiment, in the direction from the main surface of the semiconductor substrate SUB to the back surface, the p-type well region PW1 and the p-type semiconductor region PS1 are adjacent to each other. The p-type semiconductor region PS1 is separated from the n-type buried layer NBL. The impurity concentration of the p-type semiconductor region PS1 is higher than the impurity concentration of the p-type semiconductor layer EP below the p-type semiconductor region PS1.

[0159] In the transistor formation region 1B, a p-type resurf layer RE is formed in the semiconductor layer EP. The p-type resurf layer RE is formed below the p-type well region PW2 and the n-type drift region DF.

[0160] The p-type semiconductor region PS1 and the p-type resurf layer RE can be formed by the same ion implantation step, thereby suppressing the number of manufacturing steps of the semiconductor device. For example, before forming the p-type semiconductor region AD1 and the p-type semiconductor region AD2, the p-type semiconductor region PS1 and the p-type resurf layer RE can be formed using an ion implantation method.

[0161] The other configurations of the semiconductor device of the second embodiment are the same as those of the semiconductor device of the first embodiment.

[0162] In the second embodiment, a p-type semiconductor region PS1 having a higher p-type impurity concentration than the p-type semiconductor layer EP is formed in the p-type semiconductor layer EP below the p-type well region PW1. By forming the p-type semiconductor region PS1, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1 becomes higher, making it more difficult for the parasitic NPN bipolar transistor TR1 to operate. Therefore, the operation of the parasitic thyristor in the Zener diode formation region 1A can be further suppressed.

[0163] Third embodiment

[0164] Fig.21 is a cross-sectional view of a main part of the semiconductor device of the third embodiment. Fig.13 and Fig. 20 A cross section is shown at Fig.21 middle.

[0165] like Fig.21 As shown in , the semiconductor device of the third embodiment has a p-type semiconductor region PS2, a p-type resurf layer RE, and a p-type well region DPW.

[0166] like Fig.21 As shown in FIG. 1 , in the Zener diode formation region 1A, a p-type semiconductor region PS2 is formed in the semiconductor layer EP. The p-type semiconductor region PS2 is located below the p-type well region PW1. That is, the p-type semiconductor region PS2 is formed in the p-type semiconductor layer EP below the p-type well region PW1. In the third embodiment, the p-type semiconductor region PS2 is separated from the p-type well region PW1 and the n-type buried layer NBL. The impurity concentration of the p-type semiconductor region PS2 is higher than the impurity concentration of the p-type semiconductor layer EP below the p-type semiconductor region PS2. The impurity concentration of the p-type semiconductor region PS2 is also higher than the impurity concentration of the p-type semiconductor layer EP between the p-type semiconductor region PS2 and the p-type well region PW1.

[0167] In the transistor formation region 1B, a p-type RESURF layer RE and a p-type well region DPW are formed in the semiconductor layer. The p-type RESURF layer RE is formed below the p-type well region PW2 and the n-type drift region DF. The p-type well region DPW is formed below the p-type RESURF layer RE.

[0168] The p-type semiconductor region PS2 and the p-type well region DPW can be formed by the same ion implantation step, thereby suppressing the number of manufacturing steps of the semiconductor device. For example, before forming the p-type semiconductor region AD1 and the p-type semiconductor region AD2, the p-type semiconductor region PS2, the p-type RESURF layer RE and the p-type well region DPW can be formed using an ion implantation method.

[0169] The other configurations of the semiconductor device of the third embodiment are the same as those of the semiconductor device of the first embodiment.

[0170] In the third embodiment, a p-type semiconductor region PS2 having a higher p-type impurity concentration than the p-type semiconductor layer EP is formed in the p-type semiconductor layer EP below the p-type well region PW1. The formation of the p-type semiconductor region PS2 also increases the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1, making it more difficult for the parasitic NPN bipolar transistor TR1 to operate. Therefore, the operation of the parasitic thyristor in the Zener diode formation region 1A can be further suppressed.

[0171] Fourth embodiment

[0172] Fig. 22 is a main portion cross-sectional view of a semiconductor device of a fourth embodiment. Fig. 22 The cross sections of the Zener diode forming region 1A and the diode forming region 1C are shown. Fig. 22 The cross section of the Zener diode forming region 1A corresponds to Figure 1 and Fig.13 A cross section of the Zener diode forming region 1A.

[0173] like Fig. 22 As shown in , the semiconductor device of the fourth embodiment has a p-type semiconductor region PS3.

[0174] like Fig. 22 As shown in FIG. 1 , in the Zener diode formation region 1A, a p-type semiconductor region PS3 is formed in the semiconductor layer EP. The p-type semiconductor region PS3 is located below the p-type well region PW1. That is, the p-type semiconductor region PS3 is formed in the p-type semiconductor layer EP below the p-type well region PW1. In the fourth embodiment, in the direction from the main surface of the semiconductor substrate SUB to the back surface, the p-type semiconductor region PS3 and the n-type buried layer NBL are adjacent to each other. The p-type semiconductor region PS3 is separated from the p-type well region PW1. The impurity concentration of the p-type semiconductor region PS3 is higher than the impurity concentration of the p-type semiconductor layer EP on the p-type semiconductor region PS3.

[0175] The other configurations of the diode forming region 1A in the fourth embodiment are the same as those of the diode forming region 1A in the first embodiment.

[0176] In the fourth embodiment, the diode element is formed in the diode forming region 1C. Specifically, as Fig. 22 As shown in , the semiconductor device of the fourth embodiment has an n-type semiconductor region NR1, an n-type semiconductor region NR2, an n-type semiconductor region NC3, an n-type semiconductor region NC4, an n-type semiconductor region NC5, a p-type semiconductor region PA1, a p-type semiconductor region PA2 and a p-type buried layer PBL.

[0177] In the diode forming region 1C, an n-type semiconductor region NR1, an n-type semiconductor region NR2, an n-type semiconductor region NC3, an n-type semiconductor region NC4, an n-type semiconductor region NC5, a p-type semiconductor region PA1, a p-type semiconductor region PA2 and a p-type buried layer PBL are formed in the p-type semiconductor layer EP.

[0178] The n-type semiconductor region formed by the n-type semiconductor region NR1 and the n-type semiconductor region NR2 is used as the n-type cathode region of the diode. The n-type semiconductor region NR1 is formed below the n-type semiconductor region NR2. The n-type impurity concentration of the n-type semiconductor region NR2 is higher than the n-type impurity concentration of the n-type semiconductor region NR1. The plug PG is provided on the n-type semiconductor region NR2, and the plug PG is electrically connected to the n-type semiconductor region NR2.

[0179] The p-type semiconductor region formed by the p-type semiconductor region PA1, the p-type semiconductor region PA2 and the p-type semiconductor layer EP is used as a p-type anode region of the diode. The p-type semiconductor region PA1 is formed below the p-type semiconductor region PA2. The p-type impurity concentration of the p-type semiconductor region PA2 is higher than the p-type impurity concentration of the p-type semiconductor region PA1, and the p-type impurity concentration of the p-type semiconductor region PA1 is higher than the p-type impurity concentration of the p-type semiconductor layer EP. The plug PG is provided on the p-type semiconductor region PA2, and the plug PG is electrically connected to the p-type semiconductor region PA2.

[0180] The n-type semiconductor region NC4 is formed below the n-type semiconductor region NC5, and the n-type semiconductor region NC3 is formed below the n-type semiconductor region NC4. The n-type semiconductor region NC3 is in contact with the n-type buried layer NLB. The n-type impurity concentration of the n-type semiconductor region NC5 is higher than the n-type impurity concentration of the n-type semiconductor region NC4, and the n-type impurity concentration of the n-type semiconductor region NC4 is higher than the n-type impurity concentration of the n-type semiconductor region NC3. A plug PG is provided on the n-type semiconductor region NC5, and the plug PG is electrically connected to the n-type semiconductor region NC5.

[0181] The p-type buried layer PBL is formed on the n-type buried layer NBL. The p-type buried layer PBL and the n-type buried layer NBL are adjacent to each other in a direction from the main surface to the back surface of the semiconductor substrate SUB. The p-type impurity concentration of the p-type buried layer PBL is higher than the p-type impurity concentration of the p-type semiconductor layer EP.

[0182] The cathode potential is supplied from the wiring M1CN to the n-type semiconductor region NR2 via the plug PG. The anode potential is supplied from the wiring M1AN to the p-type semiconductor region PA2 via the plug PG. And, the anode potential is supplied from the wiring M1AN to the n-type buried layer NBL via the plug PG and the n-type semiconductor region NC5, the n-type semiconductor region NC4, and the n-type semiconductor region NC3. Therefore, in the diode formation region 1C, the potential of the p-type anode region and the potential of the n-type buried layer NBL are the same. This prevents the parasitic thyristor from operating in the diode formation region 1C.

[0183] The p-type semiconductor region PS3 of the Zener diode formation region 1A and the p-type buried layer PBL of the diode formation region 1C can suppress the number of manufacturing steps of the semiconductor device by forming them by the same ion implantation step.

[0184] In the present fourth embodiment, in the Zener diode formation region 1A, a p-type semiconductor region PS3 having a higher p-type impurity concentration than the p-type semiconductor layer EP is formed in the p-type semiconductor layer EP below the p-type well region PW1. By forming the p-type semiconductor region PS3, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1 becomes higher, making it more difficult for the parasitic NPN bipolar transistor TR1 to operate. Therefore, the operation of the parasitic thyristor in the Zener diode formation region 1A can be further suppressed.

[0185] Fifth embodiment

[0186] Fig.23 , Fig.24 , Fig.25 and Fig.26 1 is an explanatory diagram showing a use example of a semiconductor device. A circuit example using Zener diodes TD1, TD2, and TD3 is shown in FIG. Fig.23 and Fig.25 The connection relationship of Zener diode TD1, Zener diode TD2, and Zener diode TD3 is shown in FIG. Fig.24 and Fig.26 In each figure. Fig.24 The connection relationship between the Zener diode TD1, the Zener diode TD2, and the Zener diode TD3 is the same as that shown in FIG. Fig.23 The connection relationship of the Zener diode TD1, Zener diode TD2, and Zener diode TD3 in the circuit diagram is the same. Fig.26 The connection relationship between the Zener diode TD1, the Zener diode TD2, and the Zener diode TD3 is the same as that shown in FIG. Fig.25 The connection relationship among the Zener diode TD1, the Zener diode TD2 and the Zener diode TD3 in the circuit diagram is also the same. Fig.23 , Fig.24 , Fig.25 and Fig.26 An example of voltage when a negative surge voltage occurs is also shown.

[0187] like Fig.23 and Fig.25As shown in FIG. 1 , one end of the series circuit of Zener diodes TD1, TD2, and TD3 is connected to a connection point P2 between the input terminal TE and the circuit CT to be protected. The other end of the series circuit of Zener diodes TD1, TD2, and TD3 is connected to the ground potential. Therefore, when a negative surge voltage is applied from the input terminal TE to the circuit CT to be protected, the Zener diodes TD1, TD2, and TD3 operate, allowing current to flow from the input terminal TE to the ground via the Zener diodes TD1, TD2, and TD3. Therefore, when a negative surge voltage occurs at the input terminal TE, the circuit CT can be protected.

[0188] Among the Zener diodes TD1 , TD2 , and TD3 connected in series, the Zener diode TD1 is connected to the input terminal TE, the Zener diode TD3 is connected to the ground potential, and the Zener diode TD2 is provided between the Zener diodes TD1 and TD2 .

[0189] exist Fig.23 and Fig.24 In the case of , the cathode (cathode wiring M1C) of the Zener diode TD1 is connected to the input terminal TE. The anode (anode wiring M1A) of the Zener diode TD1 is connected to the cathode (cathode wiring M1C) of the Zener diode TD2. The anode (anode wiring M1A) of the Zener diode TD2 is connected to the anode (anode wiring M1A) of the Zener diode TD3. And the cathode (cathode wiring M1C) of the Zener diode TD3 is connected to the ground potential.

[0190] exist Fig.23 and Fig.24 In the case of , when a negative surge voltage occurs at the input terminal TE, the negative surge voltage is applied to the cathode (cathode wiring M1C) of the Zener diode TD1 via the connection point P2. Therefore, the Zener diodes TD1 and TD2 operate in the forward direction, and the Zener diode TD3 operates in the reverse direction. In the Zener diode TD3 operating in the reverse direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 6V, and in each of the Zener diodes TD1 and TD2 operating in the forward direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 0.7V.

[0191] Note that when the anode voltage VA is higher than the cathode voltage VK, the Zener diode operates in the forward direction, and when the anode voltage VA is lower than the cathode voltage VK, the Zener diode operates in the reverse direction.

[0192] exist Fig.25 and Fig.26In the case of , the anode (anode wiring M1A) of the Zener diode TD1 is connected to the input terminal TE. The cathode (cathode wiring M1C) of the Zener diode TD1 is connected to the cathode (cathode wiring M1C) of the Zener diode TD2. The anode (anode wiring M1A) of the Zener diode TD2 is connected to the cathode (cathode wiring M1C) of the Zener diode TD3. And the anode (anode wiring M1A) of the Zener diode TD3 is connected to the ground potential.

[0193] exist Fig.25 and Fig.26 In the case of , when a negative surge voltage occurs at the input terminal TE, the negative surge voltage is applied to the anode (anode wiring M1A) of the Zener diode TD1 via the connection point P2. Therefore, the Zener diode TD1 operates in the reverse direction, and the Zener diodes TD2 and TD3 operate in the forward direction. In the Zener diode TD1 operating in the reverse direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 6V, and in each of the Zener diodes TD2 and TD3 operating in the forward direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 0.7V.

[0194] exist Fig.23 and Fig.24 In the case of , in the Zener diode TD3 , the cathode voltage VK and the potential of the p-type substrate body SB are the same, and further, since the anode voltage VA is lower than the cathode voltage VK, the parasitic thyristor does not operate.

[0195] exist Fig.23 and Fig.24 In the case of , in the Zener diode TD1 and the Zener diode TD2 , the anode voltage VA and the cathode voltage VK are both negative, and also, since the anode voltage VA is higher than the cathode voltage VK, there is a possibility that the parasitic thyristor operates.

[0196] exist Fig.25 and Fig.26 In the case of , in the Zener diode TD3, since the anode voltage VK and the potential of the p-type substrate body SB are the same, the parasitic PNP bipolar transistor TR2 does not operate. Therefore, in the Zener diode TD3, the parasitic thyristor does not operate.

[0197] exist Fig.25 and Fig.26 In the case of, in the Zener diode TD1 and the Zener diode TD2, since both the anode voltage VA and the cathode voltage VK are negative, there is a possibility that the parasitic thyristor operates. However, when the anode voltage VA is lower than the cathode voltage VK, the parasitic thyristor is less likely to operate than when the anode voltage VA is higher than the cathode voltage VK.

[0198] Therefore, in Fig.23 and Fig.24 In the case of , there is a concern that parasitic thyristors operate in Zener diodes TD1 and TD2. On the other hand, in Fig.25 and Fig.26 In this case, there is a concern that a parasitic thyristor may operate in the Zener diode TD2.

[0199] In the first embodiment, the second embodiment, the third embodiment, and any of the first embodiment, the Zener diodes TD1, TD2, and TD3 have the structure of the Zener diode forming region 1A. Therefore, even in Fig.23 and Fig.24 In the case of Zener diodes TD1 and TD2, the operation of the parasitic thyristor can also be suppressed. Fig.25 and Fig.26 In this case, the Zener diode TD2 can also suppress the operation of the parasitic thyristor.

[0200] here, Fig.23 and Fig.24 The Zener diodes TD1 and TD2 in Fig.25 and Fig.26 The Zener diode TD2 in is compared. Fig.23 and Fig.24 In the Zener diode TD1, the potential difference between the p-type substrate body SB and the cathode region is -7.4V. Fig.23 and Fig.24 In the Zener diode TD2, the potential difference between the p-type substrate body SB and the cathode region is -6.7 V. On the other hand, in Fig.25 and Fig.26 The Zener diode TD2, in Fig.25 and Fig.26 In the Zener diode TD2, the potential difference between the p-type substrate body SB and the cathode region is -1.4 V. The greater the absolute value of the potential difference between the p-type substrate body SB and the cathode region, the easier it is for the parasitic thyristor to operate. Fig.23 and Fig.24 Compared with Zener diode TD1 and Zener diode TD2, parasitic thyristor is less likely to Fig.25 and Fig.26 Therefore, when the Zener diode TD2 is Fig.23 and Fig.24 The Zener diodes TD1, TD2 and TD3 in the Fig.25 and Fig.26 Compared with the Zener diodes TD1, TD2 and TD3 in the figure, it is easier to prevent Fig.25and Fig.26 The operation of the parasitic thyristors in the Zener diodes TD1, TD2, and TD3 in the Zener diodes is reduced. Fig.25 and Fig.26 The circuit configuration shown in FIG. 1 can reliably protect the circuit CT when a negative surge voltage is generated at the input terminal TE.

[0201] Although the present invention has been described in detail based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it is needless to say that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: Semiconductor substrate, comprising: a substrate region of a first conductivity type; A first semiconductor layer of a second conductivity type opposite to the first conductivity type is formed on the substrate region; and The second semiconductor layer of the first conductivity type is formed on the first semiconductor layer; an element isolation region penetrating the second semiconductor layer and the first semiconductor layer and reaching the substrate region; a cathode region of the second conductivity type of a Zener diode, the cathode region being formed in the second semiconductor layer; and an anode region of the first conductivity type of the Zener diode, the anode region being formed in the second semiconductor layer, The anode region comprises: The first semiconductor region of the first conductivity type is formed below the cathode region; and The second semiconductor region of the first conductivity type is formed below the first semiconductor region, wherein a first PN junction is formed between the first semiconductor region and the cathode region, and The impurity concentration of the second semiconductor region is higher than the impurity concentration of the first semiconductor region.

2. The semiconductor device according to claim 1, wherein the anode region includes a third semiconductor region of the first conductivity type, the third semiconductor region covers a side surface of the first semiconductor region, a side surface of the second semiconductor region, and a bottom surface of the second semiconductor region, and The impurity concentration of the first semiconductor region is higher than the impurity concentration of the third semiconductor region.

3. The semiconductor device according to claim 2, wherein the cathode region is disposed adjacent to the first semiconductor region and the third semiconductor region, and The second PN junction is formed between the third semiconductor region and the cathode region.

4. The semiconductor device according to claim 3, The impurity concentration of the third semiconductor region is higher than the impurity concentration of the second semiconductor layer.

5. The semiconductor device according to claim 3, comprising: a first plug disposed on the cathode region and electrically connected to the cathode region; as well as A second plug is electrically connected to the anode region.

6. The semiconductor device according to claim 5, wherein a first potential is supplied from the first plug to the cathode region, wherein a second potential is supplied from the second plug to the anode region, and The first potential and the second potential are lower than the potential of the substrate region.

7. The semiconductor device according to claim 6, The first potential and the second potential are negative potentials.

8. The semiconductor device according to claim 6, The second potential is higher than the first potential.

9. The semiconductor device according to claim 5, comprising: The fourth semiconductor region of the first conductivity type is formed on the third semiconductor region, The second plug is disposed on the fourth semiconductor region and is electrically connected to the third semiconductor region via the fourth semiconductor region.

10. The semiconductor device according to claim 1, The cathode region and the anode region are surrounded by the element isolation region.

11. The semiconductor device according to claim 1, The potential of the first semiconductor layer is a floating potential.

12. The semiconductor device according to claim 4, comprising: The fifth semiconductor region of the first conductivity type is formed in the second semiconductor layer and is located below the third semiconductor region, The impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the second semiconductor layer.

13. A method of manufacturing a semiconductor device including a Zener diode, the method comprising: (a) preparing a semiconductor substrate, the semiconductor substrate comprising: a substrate region of a first conductivity type; A first semiconductor layer of a second conductivity type opposite to the first conductivity type is formed on the substrate region; and The second semiconductor layer of the first conductivity type is formed on the first semiconductor layer; (b) forming an anode region of the first conductivity type of the Zener diode in the second semiconductor layer; and (c) forming a cathode region of the second conductivity type of the Zener diode in the second semiconductor layer, wherein said (b) comprises: (b1) forming a mask layer on the semiconductor substrate; (b2) after (b1), forming a first semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by first ion implantation; (b3) after (b1), forming a second semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by second ion implantation; and (b4) after (b2) and (b3), removing the mask layer, wherein the implantation energy of the second ion implantation is higher than the implantation energy of the first ion implantation, wherein the impurity concentration of the second semiconductor region is higher than the impurity concentration of the first semiconductor region, wherein after (b2) and (b3), the second semiconductor region is located below the first semiconductor region, and After (b2) and (c), the first semiconductor region is located below the cathode region, and a first PN junction is formed between the first semiconductor region and the cathode region.

14. The method according to claim 13, The dosage of the second ion implantation is greater than the dosage of the first ion implantation.

15. The method according to claim 13, comprising: (d) An element isolation region is formed, the element isolation region penetrating the second semiconductor layer and the first semiconductor layer and reaching the substrate region.

16. The method according to claim 13, wherein said (b) comprises: (b5) forming a third semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by third ion implantation, wherein the third semiconductor region covers the side surface of the first semiconductor region, the side surface of the second semiconductor region, and the bottom surface of the second semiconductor region, and The impurity concentration of the first semiconductor region is higher than the impurity concentration of the third semiconductor region.

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