Shield gate trench device and manufacturing method
By performing secondary etching of the shielded gate and forming a protective layer in the shielded gate trench device, the problem of isolation layer filling relying on high-end equipment is solved, and isolation reliability and device performance are improved.
Patent Information
- Application Number
- CN202310777617.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2025-01-10
AI Technical Summary
In the prior art, the isolation layer filling of shielded gate trench devices relies on high-end equipment, and the isolation reliability is poor, resulting in poor device performance.
By performing secondary etching on the shielded gate, small grooves on the top side are eliminated, and a protective layer is formed on the shielded gate. The isolation layer is filled by high-density plasma chemical vapor deposition method to ensure that the isolation layer is densely filled.
Improves the isolation reliability between the shielded gate and the control gate, reduces dependence on high-end devices, and improves device performance.
Smart Images
Figure CN119300444A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a shielded gate trench device and a manufacturing method thereof. Background Art
[0002] The shielded gate trench device introduces a shielded gate to reduce the gate-drain overlap area of the device, thereby reducing the gate-drain capacitance, thereby increasing the switching speed of the device and reducing the dynamic loss of the device, thereby improving the system utilization efficiency.
[0003] In shielded gate trench devices, a sufficiently thick isolation oxide layer (Inter-poly-oxide, IPO) is set between the polysilicon shielding gate and the polysilicon control gate for insulation isolation. The quality of the isolation oxide layer has a great influence on the performance of the device. Figures 1 to 6 , showing a method for manufacturing a shielded gate trench device, comprising the following steps: Figure 1 As shown, a trench is formed in the epitaxial layer 2; Figure 2 As shown, a dielectric material layer 5 is formed on the sidewalls and bottom of the trench; Figure 3 As shown, a polysilicon layer is formed in the trench and etched to form a shielding gate 6a; Figure 4 and Figure 5 As shown, the dielectric material layer 5 is etched to form a shielding gate dielectric layer 5a. In this step, the dielectric material layer 5 is wet etched. Due to the isotropic corrosion of the wet etching, a small groove will inevitably be formed on the top side of the shielding gate 6a; Figure 6 As shown, a high-density plasma chemical vapor deposition method (HDP) is used to fill and form an isolation material layer 8. Due to the presence of small grooves, it is easy to cause voids to form during the filling process, reducing the reliability of isolation. If the filling effect is to be improved, a higher equipment capacity or a larger etching rate (increased power) is required for HDP filling, which has high equipment requirements and high technical difficulty. In addition, increased power may cause the trench sidewalls to be affected by HDP, thereby causing device leakage.
[0004] Therefore, how to provide a shielding gate trench device and a manufacturing method to reduce the dependence of isolation layer filling on high-end capability equipment and improve the isolation reliability of the device has become a technical problem that needs to be urgently solved by technical personnel in this field.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a shielded gate trench device and a manufacturing method for solving the problems in the prior art such as high dependence of isolation layer filling on high-end capability equipment and poor isolation reliability of the device.
[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a shielded gate trench device, comprising the following steps:
[0008] providing a substrate, and forming a groove in the substrate;
[0009] forming a dielectric material layer on the sidewall and bottom of the trench, and forming a polysilicon layer in the trench;
[0010] etching the polysilicon layer to form a shielding gate;
[0011] Etching the dielectric material layer to form a shielding gate dielectric layer, wherein a top of the shielding gate dielectric layer is lower than a top of the shielding gate;
[0012] Etching the shielding gate so that the top of the shielding gate is not higher than the top of the shielding gate dielectric layer;
[0013] forming an isolation layer on the shielding gate;
[0014] A gate oxide layer is formed on the sidewall of the trench above the isolation layer, and a control gate is formed in the trench above the isolation layer.
[0015] Optionally, a top of the shielding gate is flush with a top of the shielding gate dielectric layer.
[0016] Optionally, in the process of etching the dielectric material layer to form the shielding gate dielectric layer, the dielectric material layer with a preset thickness above the shielding gate is retained as a protective layer.
[0017] Optionally, the method of forming an isolation layer on the shielding gate includes:
[0018] forming an isolation material layer in the trench above the shielding gate;
[0019] The isolation material layer is etched to form the isolation layer, wherein during the etching of the isolation material layer, the protection layer located above the isolation oxide layer is etched away.
[0020] Optionally, a method of forming the isolation material layer includes a high density plasma chemical vapor deposition method.
[0021] Optionally, a method of etching the dielectric material layer to form the shield gate dielectric layer includes wet etching.
[0022] Optionally, after forming the control gate, the method further includes:
[0023] forming a body region in the substrate on both sides of the control gate, wherein the vertical depth of the body region does not exceed the depth of the control gate;
[0024] A source region is formed in the body region, and a source electrode is formed above the substrate, wherein the source electrode is electrically connected to the source region.
[0025] The present invention further provides a shielded gate trench device, wherein the shielded gate trench device is manufactured by any one of the manufacturing methods described above, comprising:
[0026] a substrate having a groove therein;
[0027] A shielding gate is located in the trench, a shielding gate dielectric layer is provided between the shielding gate and the trench, and a top of the shielding gate is not higher than a top of the shielding gate dielectric layer;
[0028] A control gate is located in the trench and above the shielding gate, an isolation layer is arranged between the control gate and the shielding gate, and a gate oxide layer is arranged between the control gate and the trench.
[0029] Optionally, a top of the shielding gate is flush with a top of the shielding gate dielectric layer.
[0030] Optionally, it also includes:
[0031] a body region located in the substrate on both sides of the control gate, wherein the vertical depth of the body region does not exceed the depth of the control gate;
[0032] a source region located in the body region;
[0033] A source electrode is located above the substrate, and the source electrode is electrically connected to the source region.
[0034] As described above, in the shielded gate trench device and manufacturing method of the present invention, the shielded gate polysilicon is subjected to secondary etching, which can eliminate the small groove on the top side of the shielded gate, so that the isolation layer can be densely filled, thereby improving the isolation reliability of the shielded gate and the control gate. In addition, a protective layer is formed on the side wall of the trench above the shielded gate, and the side wall morphology of the trench is protected during the secondary etching of the shielded gate polysilicon, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 The diagram shows a method for manufacturing a shielded gate trench device, in which a trench is formed in an epitaxial layer.
[0036] Figure 2The diagram shows a method for manufacturing a shielded gate trench device, in which a dielectric material layer is formed on the sidewall and bottom of a trench.
[0037] Figure 3 A schematic diagram showing the formation of a shielding gate in a method for manufacturing a shielding gate trench device is shown.
[0038] Figure 4 Shown is a schematic diagram of etching a dielectric material layer in a method for manufacturing a shielded gate trench device.
[0039] Figure 5 Display as Figure 4 Enlarged schematic diagram of the dashed box area.
[0040] Figure 6 Shown is a schematic diagram of forming an isolation material layer in a method for manufacturing a shielded gate trench device.
[0041] Figure 7 Shown is a flow chart of a method for manufacturing a shielded gate trench device of the present invention.
[0042] Figure 8 It is a schematic diagram showing the process of forming an epitaxial layer on a semiconductor substrate in the method of manufacturing a shielded gate trench device according to the present invention.
[0043] Fig. 9 It is a schematic diagram showing the formation of a mask layer on an epitaxial layer in the method for manufacturing a shielded gate trench device of the present invention.
[0044] Fig.10 It is a schematic diagram showing the formation of a trench in an epitaxial layer in the method for manufacturing a shielded gate trench device of the present invention.
[0045] Fig.11 It is a schematic diagram showing the formation of a dielectric material layer on the sidewall and bottom of the trench in the method for manufacturing the shielded gate trench device of the present invention.
[0046] Fig.12 It is a schematic diagram showing the formation of a polysilicon layer in the method for manufacturing a shielded gate trench device of the present invention.
[0047] Fig.13 It is a schematic diagram showing the formation of a shielding gate in the method for manufacturing a shielding gate trench device of the present invention.
[0048] Fig.14 It is a schematic diagram showing the etching of the dielectric material layer in the method for manufacturing the shielded gate trench device of the present invention.
[0049] Fig.15 It is a schematic diagram showing etching a shielding gate in the method for manufacturing a shielding gate trench device of the present invention.
[0050] Fig.16It is a schematic diagram showing the formation of an isolation material layer in the method for manufacturing a shielded gate trench device of the present invention.
[0051] Fig.17 Schematic diagram showing etching of the isolation layer in the method for manufacturing the shielded gate trench device of the present invention
[0052] Fig.18 It is a schematic diagram showing the formation of a gate oxide layer in the method for manufacturing a shielded gate trench device of the present invention.
[0053] Fig.19 It is a schematic diagram showing the formation of a control gate in the method for manufacturing a shielded gate trench device of the present invention.
[0054] Fig. 20 It is a schematic diagram showing the formation of a body region in the method for manufacturing a shielded gate trench device of the present invention.
[0055] Fig.21 It is a schematic diagram showing the formation of a source region in the method for manufacturing a shielded gate trench device of the present invention.
[0056] Fig. 22 It is a schematic diagram showing the formation of an interlayer dielectric layer in the method for manufacturing a shielded gate trench device of the present invention.
[0057] Fig.23 It is a schematic diagram showing the formation of a source in the method for manufacturing a shielded gate trench device of the present invention.
[0058] Component number description
[0059] 1 Semiconductor substrate
[0060] 2 Epitaxial layer
[0061] 3 Hard mask layer
[0062] 4 Photoresist layer
[0063] 5 Dielectric material layer
[0064] 5a Shielding gate dielectric layer
[0065] 6 Polysilicon layer
[0066] 6a Shielding grid
[0067] 7. Protective layer
[0068] 8 Isolation material layer
[0069] 8a Isolation layer
[0070] 9 Gate Oxide Layer
[0071] 10 Control gate
[0072] 11 Body Area
[0073] 12 Source area
[0074] 13 Interlayer dielectric layer
[0075] 14 Source
[0076] Steps S1 to S7 DETAILED DESCRIPTION
[0077] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0078] See also Figures 1 to 23 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0079] This embodiment provides a method for manufacturing a shielded gate trench device. Figure 7 , which is a flow chart of a method for manufacturing the shielded gate trench device, comprising the following steps:
[0080] S1: providing a substrate, and forming a groove in the substrate;
[0081] S2: forming a dielectric material layer on the sidewall and bottom of the trench, and forming a polysilicon layer in the trench;
[0082] S3: etching the polysilicon layer to form a shielding gate;
[0083] S4: etching the dielectric material layer to form a shielding gate dielectric layer, wherein a top of the shielding gate dielectric layer is lower than a top of the shielding gate;
[0084] S5: etching the shielding gate so that the top of the shielding gate is not higher than the top of the shielding gate dielectric layer;
[0085] S6: forming an isolation layer on the shielding gate;
[0086] S7: forming a gate oxide layer on the sidewall of the trench above the isolation layer, and forming a control gate in the trench above the isolation layer.
[0087] First, see Figures 8 to 10 , performing step S1: providing a substrate and forming a groove in the substrate.
[0088] As an example, Figure 8 As shown, the base includes an epitaxial layer 2 formed on a semiconductor substrate 1. The semiconductor substrate 1 can be any suitable semiconductor material, and the epitaxial layer 2 can be any suitable semiconductor material. Specifically, in this embodiment, the semiconductor substrate 1 adopts a silicon substrate, and the epitaxial layer 2 adopts a silicon epitaxial layer.
[0089] As an example, Fig. 9 As shown, a hard mask layer 3 and a photoresist layer 4 are sequentially formed above the epitaxial layer 2, and the hard mask layer 3 includes at least one of a silicon oxide layer and a silicon nitride layer; specifically, in this embodiment, the hard mask layer 3 adopts a silicon oxide-silicon nitride-silicon oxide stack.
[0090] As an example, Fig.10 As shown, the photoresist layer 4 is patterned, an opening is formed in the hard mask layer 3 based on the photoresist layer 4, and the silicon epitaxial layer 2 is etched based on the hard mask layer 3 to form the trench.
[0091] Next, see Figure 11 to Figure 12 , executing step S2: forming a dielectric material layer 5 on the sidewall and bottom of the trench, and forming a polysilicon layer 6 in the trench.
[0092] As an example, Fig.11 As shown, the dielectric material layer 5 is formed by a thermal oxidation method or a deposition method, and the dielectric material layer 5 includes a silicon oxide layer.
[0093] As an example, Fig.12 As shown, the polysilicon layer 6 is deposited in the trench, wherein during the process of depositing the polysilicon layer 6 in the trench, the polysilicon layer 6 is also formed above the epitaxial layer 2 .
[0094] Next, see Fig.13 , performing step S3: etching the polysilicon layer 6 to form a shielding gate 6a.
[0095] As an example, the polysilicon layer 6 is etched by dry etching to form the shielding gate 6a. In other examples, the polysilicon layer 6 located above the epitaxial layer 2 can also be polished away by chemical mechanical polishing, and then the polysilicon layer 6 in the trench is etched by dry etching to form the shielding gate 6a.
[0096] Next, see Fig.14, executing step S4: etching the dielectric material layer 5 to form a shielding gate dielectric layer 5a, wherein the top of the shielding gate dielectric layer 5a is lower than the top of the shielding gate 6a.
[0097] As an example, in the process of etching the dielectric material layer 5 to form the shielding gate dielectric layer 5a, the dielectric material layer 5 above the shielding gate 6a is etched, which is beneficial to the subsequent filling of the isolation material layer 8 (see the subsequent Fig.16 ), if the dielectric material layer 5 is not etched and the isolation material layer 8 is directly filled, the existence of the dielectric material layer 5 makes the aperture above the shielding gate 6a small, which is not conducive to the filling of the isolation material layer 8a and is easy to form holes.
[0098] As an example, since the dielectric material layer 5 is etched in a direction perpendicular to the sidewall of the trench, the dielectric material layer 5 is etched by wet etching, wherein the dielectric material layer with a preset thickness above the shielding gate 6a is retained as a protective layer 7.
[0099] As an example, due to the isotropy of wet etching, during the process of etching the dielectric material layer 5 to form the shielding gate dielectric layer 5a, the dielectric material layer 5 on both sides of the top of the shielding gate 6a is over-etched to form small grooves. The existence of the small grooves is not conducive to the subsequent filling of the isolation material layer 8.
[0100] Next, see Fig.15 , executing step S5: etching the shielding gate 6a so that the top of the shielding gate 6a is not higher than the top of the shielding gate dielectric layer 5a.
[0101] As an example, the shielding gate 6 a is etched by dry etching so that the top of the shielding gate 6 a is flush with the top of the shielding gate dielectric layer 5 a to eliminate the small groove.
[0102] As an example, the shielding gate 6a is a polysilicon shielding gate, and the epitaxial layer 2 is a silicon epitaxial layer. The etching selectivity between the two is small. Due to the existence of the protective layer 7, the protective layer 7 is a silicon oxide layer, and the etching selectivity between silicon oxide and silicon is large. In the process of etching the shielding gate 6a, the side wall morphology of the groove will not be damaged, which is more practical.
[0103] Next, see Figure 16 to Figure 17 , executing step S6: forming an isolation layer 8a on the shielding gate 6a.
[0104] As an example, Fig.16As shown, a high-density plasma chemical vapor deposition method (HDP) is used to fill the groove to form an isolation material layer 8. Due to the elimination of the small grooves, the bottom of the filling area of the isolation material layer 8 is flat. The conventional HDP equipment can fill the isolation material layer 8 into the groove more densely, reducing the dependence on high-end capacity equipment; the isolation material layer 8 includes a silicon oxide layer.
[0105] As an example, Fig.17 As shown, the isolation material layer 8 is etched to form the isolation layer 8a.
[0106] As an example, during the etching of the isolation material layer 8, the protection layer 7 located above the isolation layer 8a is removed by etching; in other examples, the protection layer 7 is not removed and can be used as a part of the gate oxide layer formed subsequently.
[0107] As an example, a step of removing the hard mask layer 3 is also included.
[0108] Next, see Figure 18 to Figure 19 , executing step S7: forming a gate oxide layer 9 on the sidewall of the trench above the isolation layer 8a, and forming a control gate 10 in the trench above the isolation layer 8a.
[0109] As an example, the gate oxide layer 9 is formed by thermal oxidation or deposition, the control gate 10 is formed by deposition, the gate oxide layer 9 includes a silicon oxide layer, and the control gate 10 includes a polysilicon control gate.
[0110] As an example, after forming the control gate 10, the following steps are further included:
[0111] (1) Fig. 20 As shown, a body region 11 is formed in the substrate on both sides of the control gate 10 by ion implantation, and the vertical depth of the body region 11 does not exceed the depth of the control gate 10;
[0112] (2) Fig.21 As shown, an ion implantation method is used to form a source region 12 in the body region 11; wherein the epitaxial layer 2 as a drain region is doped with a first conductivity type, the body region 11 is doped with a second conductivity type, and the source region 12 is doped with the first conductivity type, the first conductivity type is doped with N-type, and the second conductivity type is doped with P-type, or the first conductivity type is doped with P-type, and the second conductivity type is doped with N-type;
[0113] (3) Fig. 22 As shown, an interlayer dielectric layer 13 is formed above the epitaxial layer 2, and the interlayer dielectric layer 13 includes a silicon oxide layer;
[0114] (4) Fig.23 As shown, a through hole is formed in the interlayer dielectric layer 13, and a source electrode 14 is formed above the interlayer dielectric layer 13. The source electrode 14 extends into the through hole and is electrically connected to the source region 12. Moreover, the source electrode 14 also extends into the body region 11, which can prevent the generation of parasitic transistors between the epitaxial layer 2, the body region 11 and the source region 12. The source and drain are only equivalent to a body diode, thereby improving the device performance.
[0115] As an example, the method further includes forming a back metal layer as a drain under the semiconductor substrate 1 .
[0116] At this point, a shielded gate trench device is obtained. Fig.23 The shielded gate trench device includes a substrate, a shielded gate 6a and a control gate 10, wherein the substrate has a trench; the shielded gate 6a is located in the trench, a shielded gate dielectric layer 5a is arranged between the shielded gate 6a and the trench, and the top of the shielded gate 6a is not higher than the top of the shielded gate dielectric layer 5a; the control gate 10 is located in the trench and above the shielded gate 6a, an isolation layer 8a is arranged between the control gate 10 and the shielded gate 6a, and a gate oxide layer 9 is arranged between the control gate 10 and the trench.
[0117] As an example, the base includes an epitaxial layer 2 formed on a semiconductor substrate 1; specifically, in this embodiment, the semiconductor substrate 1 is a silicon substrate, and the epitaxial layer 2 is a silicon epitaxial layer.
[0118] As an example, the shielding gate 6a includes a polysilicon shielding gate, the control gate 10 includes a polysilicon control gate, the shielding gate dielectric layer 5a includes a silicon oxide layer, the isolation layer 8a includes a silicon oxide layer, and the gate oxide layer 9 includes a silicon oxide layer, wherein the top of the shielding gate 6a is flush with the top of the shielding gate dielectric layer 5a.
[0119] As an example, it also includes a body region 11 and a source region 12, wherein the body region 11 is located in the substrate on both sides of the control gate 10, and the vertical depth of the body region 11 does not exceed the depth of the control gate 10; the source region 12 is located in the body region 11. The epitaxial layer 2 is doped with a first conductivity type as a drain region, the body region 11 is doped with a second conductivity type, and the source region 12 is doped with a first conductivity type, the first conductivity type is doped with N-type doping, and the second conductivity type is doped with P-type doping, or the first conductivity type is doped with P-type doping, and the second conductivity type is doped with N-type doping.
[0120] As an example, it also includes an interlayer dielectric layer 13 and a source 14, the interlayer dielectric layer 13 is located above the epitaxial layer 2; the source 14 is located above the interlayer dielectric layer 13, the source 14 penetrates the interlayer dielectric layer 13 and is electrically connected to the source region 12, and the source 14 also extends into the body region 11, which can prevent parasitic transistors from being generated between the epitaxial layer 2, the body region 11 and the source region 12, and the source and drain are only equivalent to a body diode, thereby improving device performance.
[0121] In summary, in the shielding gate trench device and manufacturing method of the present invention, the shielding gate polysilicon is subjected to secondary etching, which can eliminate the small groove on the top side of the shielding gate, so that the isolation layer can be densely filled, and the isolation reliability of the shielding gate and the control gate is improved. In addition, a protective layer is formed on the side wall of the trench above the shielding gate, and the side wall morphology of the trench is protected during the secondary etching of the shielding gate polysilicon, thereby improving the device performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0122] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a shielded gate trench device, characterized in that: The following steps are involved: providing a substrate, and forming a groove in the substrate; forming a dielectric material layer on the sidewall and bottom of the trench, and forming a polysilicon layer in the trench; etching the polysilicon layer to form a shielding gate; Etching the dielectric material layer to form a shielding gate dielectric layer, wherein a top of the shielding gate dielectric layer is lower than a top of the shielding gate; Etching the shielding gate so that the top of the shielding gate is not higher than the top of the shielding gate dielectric layer; forming an isolation layer on the shielding gate; A gate oxide layer is formed on the sidewall of the trench above the isolation layer, and a control gate is formed in the trench above the isolation layer.
2. The method for manufacturing a shielded gate trench device according to claim 1, characterized in that: The top of the shielding gate is flush with the top of the shielding gate dielectric layer.
3. The method for manufacturing a shielded gate trench device according to claim 1, characterized in that: In the process of etching the dielectric material layer to form the shielding gate dielectric layer, the dielectric material layer with a preset thickness above the shielding gate is retained as a protective layer.
4. The method for manufacturing a shielded gate trench device according to claim 3, characterized in that: The method of forming an isolation layer on the shielding gate includes: forming an isolation material layer in the trench above the shielding gate; The isolation material layer is etched to form the isolation layer, wherein during the etching of the isolation material layer, the protection layer located above the isolation layer is etched away.
5. The method for manufacturing a shielded gate trench device according to claim 4, characterized in that: The method of forming the isolation material layer includes a high density plasma chemical vapor deposition method.
6. The method for manufacturing a shielded gate trench device according to claim 1, characterized in that: The method of etching the dielectric material layer to form the shielding gate dielectric layer includes wet etching.
7. The method for manufacturing a shielded gate trench device according to claim 1, characterized in that: After forming the control gate, the method further includes: forming a body region in the substrate on both sides of the control gate, wherein the vertical depth of the body region does not exceed the depth of the control gate; A source region is formed in the body region, and a source electrode is formed above the substrate, wherein the source electrode is electrically connected to the source region.
8. A shielded gate trench device, characterized in that: The shielded gate trench device is manufactured by the manufacturing method according to any one of claims 1 to 7, comprising: a substrate having a groove therein; A shielding gate is located in the trench, a shielding gate dielectric layer is provided between the shielding gate and the trench, and a top of the shielding gate is not higher than a top of the shielding gate dielectric layer; A control gate is located in the trench and above the shielding gate, an isolation layer is arranged between the control gate and the shielding gate, and a gate oxide layer is arranged between the control gate and the trench.
9. The shielded gate trench device according to claim 8, characterized in that: The top of the shielding gate is flush with the top of the shielding gate dielectric layer.
10. The shielded gate trench device according to claim 8, characterized in that: Also includes: a body region located in the substrate on both sides of the control gate, wherein the vertical depth of the body region does not exceed the depth of the control gate; a source region located in the body region; A source electrode is located above the substrate, and the source electrode is electrically connected to the source region.