Shield gate trench device and preparation method thereof
By optimizing the process in the shielded gate trench device, forming a patterned mask layer and thinning the first dielectric layer to form a mesa, the problems of complex isolation layer process and poor breakdown resistance are solved, and the isolation layer of the device is improved Mass and switching performance.
Patent Information
- Application Number
- CN202310812788.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2025-01-10
AI Technical Summary
In the prior art, the isolation layer process of shielded gate trench devices is complex and has poor breakdown resistance, which leads to an increase in the Miller capacitance of the device and affects the switching time.
By forming a patterned mask layer on the upper surface of the semiconductor layer, the trench and the shielding gate layer are formed in sequence, and the first dielectric layer on the inner wall of the trench is thinned to form a mesa, and the shielding gate layer is back-etched so that it is flush with the mesa surface. , a second dielectric layer is formed as a mask to form an isolation layer to avoid sharp corners and hollows, and to improve the thickness and quality of the isolation layer.
Improves the isolation layer quality and breakdown resistance of the device, reduces Miller capacitors, and improves switching performance and breakdown stability.
Smart Images
Figure CN119300446A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a shielded gate trench device and a preparation method thereof. Background Art
[0002] At present, the production of the isolation oxide layer (Inter-poly-oxide, referred to as IPO) in the shielded gate trench device is often carried out by using a high-density plasma deposition (HDP) process and a thermal oxidation isolation process. The production of the isolation oxide layer in the shielded gate trench device is usually to form a polysilicon shielding gate layer (Source poly) after back etching, and then use a wet etching process to etch (OX remove) the field oxide layer on the inner wall of the trench, and then form the isolation oxide layer. Due to the isotropic corrosion characteristics of wet etching, a groove is formed between the top of the polysilicon shielding gate layer and the inner wall of the trench, such as Figure 1 and Figure 2 , which are schematic diagrams of the cross-sectional structure after forming a polysilicon shielding gate layer and a schematic diagram of the cross-sectional structure after wet etching of the field oxide layer, respectively, including a semiconductor layer 01, a substrate 011, an epitaxial layer 012, a trench 013, a field oxide layer 014, a polysilicon shielding gate layer 015 and a groove 016. When a high-density plasma deposition process is used to form an oxide layer filling the trench, a high-density plasma deposition process is first used to form an oxide layer filling the trench, and then the oxide layer is etched back, and the etching back time is controlled to obtain an isolation oxide layer with a thickness that meets the requirements, such as Figure 3 and Figure 4 As shown, they are schematic diagrams of the cross-sectional structure after forming an isolation oxide material layer filling the groove and a schematic diagram of the cross-sectional structure after etching the isolation oxide material layer to obtain the isolation oxide layer, including semiconductor layer 01, substrate 011, epitaxial layer 012, groove 013, field oxide layer 014, polysilicon shielding gate layer 015, groove 016, isolation oxide layer 02 and isolation oxide material layer 03. However, due to the back etching of the oxide layer filling the groove, an additional layer of mask is required, and the opening size of the groove between the polysilicon shielding gate layer and the inner wall of the groove is relatively small, which makes it easy to produce voids when filling the groove. In addition, in the shielding gate structure with a lower voltage, due to the small width of the groove, the high-density plasma deposition process cannot be used to effectively fill the groove, resulting in poor quality of the isolation oxide layer, affecting the gate-source breakdown resistance of the device; when the isolation oxide layer is made by the thermal oxidation process, the formation of the isolation oxide layer will not be affected by the characteristic size (CD) of the groove. After etching the field oxide layer, the exposed polysilicon shielding gate layer is directly oxidized to obtain the isolation oxide layer, as shown in FIG. Figure 5As shown in FIG. 1 , it is a schematic diagram of a cross-sectional structure after an isolation oxide layer is formed by a thermal oxidation process, including a semiconductor layer 01, a substrate 011, an epitaxial layer 012, a trench 013, a field oxide layer 014, a polysilicon shielding gate layer 015, a groove 016 and an isolation oxide layer 02. However, since a groove is formed between the polysilicon shielding gate layer and the inner wall of the trench, directly oxidizing the exposed polysilicon shielding gate layer will result in a sharp corner at the groove. The isolation oxide layer at the sharp corner is relatively thin, which can easily cause unstable gate-source breakdown. At the same time, after the polysilicon gate is subsequently filled, the contact area between the gate and the source will also increase, and then the Miller capacitance C of the device will increase. rss Increases, affecting the switching time of the device.
[0003] Therefore, there is an urgent need to find a method for preparing a shielded gate trench device that has a simple process, improves the breakdown resistance of the isolation layer, and does not affect the Miller capacitance of the device. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a shielded gate trench device and a preparation method thereof, so as to solve the problems of complex isolation layer process and poor breakdown resistance of the shielded gate trench device in the prior art.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a shielded gate trench device, comprising the following steps:
[0006] Providing a semiconductor layer including a substrate and an epitaxial layer stacked in sequence, forming a mask layer on the upper surface of the epitaxial layer and patterning the mask layer;
[0007] Based on the patterned mask layer, a plurality of grooves are formed on the upper surface of the epitaxial layer and are spaced apart from each other, and a first dielectric layer covering the inner wall and bottom of the groove and a shielding gate layer filling the groove are sequentially formed, wherein the upper surface of the shielding gate layer is lower than the upper surface of the epitaxial layer by a preset distance;
[0008] The first dielectric layer covering the inner wall of the trench above the shielding gate layer is thinned, and after the thinning, a table lower than the upper surface of the shielding gate layer is formed at the contact point between the first dielectric layer and the top of the shielding gate layer, and the shielding gate layer is back-etched to make the upper surface of the shielding gate layer flush with the table;
[0009] Forming a second dielectric layer covering the first dielectric layer and the exposed surface of the shielding grid layer, wherein the second dielectric layer is made of a different material from the first dielectric layer, and removing the second dielectric layer covering the mesa and the upper surface of the shielding grid layer;
[0010] An isolation layer is formed by using the second dielectric layer and the mask layer as masks, and the second dielectric layer and the first dielectric layer covering the inner wall of the trench above the isolation layer are removed.
[0011] Optionally, the material of the mask layer includes silicon nitride.
[0012] Optionally, a method of forming the first dielectric layer includes a thermal oxidation method.
[0013] Optionally, the method of thinning the first dielectric layer includes wet etching.
[0014] Optionally, the method of removing the second dielectric layer covering the mesa and the upper surface of the shielding gate layer comprises dry etching.
[0015] Optionally, the method of forming the isolation layer includes a thermal oxidation method.
[0016] Optionally, a material of the second dielectric layer includes silicon nitride.
[0017] Optionally, after removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method further includes forming a gate dielectric layer, a gate conductive layer, a second conductive type body region, a first conductive type source region, a gate, a source electrode and a drain electrode.
[0018] Optionally, after removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method also includes forming a gate dielectric layer, a polysilicon gate layer, a second conductive type base region, a first conductive type emitter region, a second conductive type emitter contact region, a gate, an emitter, a second conductive type collector region and a collector.
[0019] The present invention also provides a shielded gate trench device, and the shielded gate trench device is manufactured by adopting the above-mentioned shielded gate trench device manufacturing method.
[0020] As described above, the shielding gate trench device and the preparation method thereof of the present invention optimize the process of manufacturing the shielding gate trench device. Before forming the trench in the semiconductor layer, a patterned mask layer is formed on the upper surface of the semiconductor layer, and based on the patterned mask layer, the trench located on the upper surface of the epitaxial layer, the first dielectric layer covering the inner wall and bottom of the trench, and the shielding gate layer filling the bottom of the trench are sequentially formed. Then, based on the mask layer, the first dielectric layer covering the inner wall of the trench above the shielding gate layer is thinned, and while thinning the first dielectric layer, the table below the upper surface of the shielding gate layer is formed, the shielding gate layer is backetched so that the upper surface of the shielding gate layer is flush with the table, and then the shielding gate layer is formed. The second dielectric layer covers the surface of the first dielectric layer above the table, and the second dielectric layer and the mask layer are used as masks to form the isolation layer. The thickness of the isolation layer can be freely adjusted as needed, thereby avoiding the problem of increasing the facing area between the gate and the source of the device due to the formation of a sharp corner at the portion of the isolation layer close to the inner wall of the groove, and also avoiding the problem that the isolation layer is difficult to fill into the gap between the shielding gate layer and the groove, resulting in the gate and source (emitter) breakdown resistance of the device being affected. The switching performance of the device is improved, the quality of the isolation layer is improved, the breakdown stability of the gate and the source (emitter) is effectively improved, and then the performance of the device is improved, which has a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 The schematic diagram shows the cross-sectional structure of the shielded gate trench device manufacturing method after forming a polysilicon shielding gate layer.
[0022] Figure 2 The schematic diagram shows the cross-sectional structure after etching the field oxide layer in the preparation method of the shielded gate trench device.
[0023] Figure 3 The schematic diagram shows the cross-sectional structure of the shielded gate trench device manufacturing method after forming an isolation oxide material layer.
[0024] Figure 4 The schematic diagram of the cross-sectional structure after etching the isolation oxide material layer to obtain the isolation oxide layer in the method for preparing the shielded gate trench device is shown.
[0025] Figure 5 The schematic diagram of the cross-sectional structure of the shielded gate trench device manufacturing method after directly forming an isolation oxide layer by a thermal oxidation process is shown.
[0026] Figure 6 Shown is a process flow chart of a method for preparing a shielded gate trench device of the present invention.
[0027] Figure 7It is a schematic diagram showing the cross-sectional structure after the trench is formed in the method for preparing the shielded gate trench device of the present invention.
[0028] Figure 8 It is a schematic diagram of the cross-sectional structure after forming the shielding gate layer in the method for preparing the shielding gate trench device of the present invention.
[0029] Fig. 9 It is a schematic diagram showing the cross-sectional structure after thinning the first dielectric layer in the method for preparing the shielded gate trench device of the present invention.
[0030] Fig.10 It is a schematic diagram of the cross-sectional structure after etching back the shielding gate layer in the method for preparing the shielding gate trench device of the present invention.
[0031] Fig.11 It is a schematic diagram of the cross-sectional structure after forming the second dielectric layer in the method for preparing the shielded gate trench device of the present invention.
[0032] Fig.12 It is a schematic cross-sectional structure diagram of the method for preparing the shielded gate trench device of the present invention after removing the second dielectric layer covering the mesa and the exposed surface of the shielding gate layer.
[0033] Fig.13 It is a schematic diagram of the cross-sectional structure after forming an isolation layer in the method for preparing the shielded gate trench device of the present invention.
[0034] Fig.14 It is a schematic cross-sectional structure diagram of the method for preparing the shielded gate trench device of the present invention after removing the first dielectric layer covering the inner wall of the trench above the isolation layer.
[0035] Fig.15 It is a schematic diagram of the cross-sectional structure after forming the source contact hole in the method for preparing the shielded gate trench device of the present invention.
[0036] Description of Figure Numbers
[0037] 01 Semiconductor layer
[0038] 011 Substrate
[0039] 012 Epitaxial layer
[0040] 013 Groove
[0041] 014 Field Oxygen Layer
[0042] 015 Polysilicon shielding gate layer
[0043] 016 Groove
[0044] 02 Isolation Oxide Layer
[0045] 03 Isolation Oxide Material Layer
[0046] 1 Semiconductor layer
[0047] 11 Substrate
[0048] 12 Epitaxial layer
[0049] 13 Groove
[0050] 14 First dielectric layer
[0051] 141 Countertop
[0052] 15 Shielding layer
[0053] 16. Gate dielectric layer
[0054] 17 Gate conductive layer
[0055] 2 Mask layer
[0056] 20 Mask buffer layer
[0057] 3 Second dielectric layer
[0058] 4 Isolation layer
[0059] 5 Body Zones
[0060] 51 Source Area
[0061] 52 Source contact hole DETAILED DESCRIPTION
[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0063] See also Figures 6 to 15 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0064] Embodiment 1
[0065] This embodiment provides a method for preparing a shielded gate trench device, such as Figure 6 FIG. 1 is a process flow chart of a method for preparing the shielded gate trench device, comprising the following steps:
[0066] S1: providing a semiconductor layer including a substrate and an epitaxial layer stacked in sequence, forming a mask layer on an upper surface of the epitaxial layer and patterning the mask layer;
[0067] S2: Based on the patterned mask layer, a plurality of grooves are formed on the upper surface of the epitaxial layer and are spaced apart from each other, and a first dielectric layer covering the inner wall and bottom of the groove and a shielding gate layer filling the groove are sequentially formed, wherein the upper surface of the shielding gate layer is lower than the upper surface of the epitaxial layer by a preset distance;
[0068] S3: thinning the first dielectric layer covering the inner wall of the trench above the shielding gate layer, and after thinning, a table lower than the upper surface of the shielding gate layer is formed at the contact point between the first dielectric layer and the top of the shielding gate layer, and back-etching the shielding gate layer so that the upper surface of the shielding gate layer is flush with the table;
[0069] S4: forming a second dielectric layer covering the first dielectric layer and the exposed surface of the shielding grid layer, wherein the second dielectric layer is made of a different material from the first dielectric layer, and removing the second dielectric layer covering the mesa and the upper surface of the shielding grid layer;
[0070] S5: using the second dielectric layer and the mask layer as masks to form an isolation layer, and removing the second dielectric layer and the first dielectric layer covering the inner wall of the trench above the isolation layer.
[0071] See also Figures 7 to 10 , performing the steps S1, S2 and S3: providing a semiconductor layer 1 including a substrate 11 and an epitaxial layer 12 stacked in sequence, forming a mask layer 2 on the upper surface of the epitaxial layer 12 and patterning the mask layer 2; forming a plurality of grooves 13 located on the upper surface of the epitaxial layer 12 and spaced apart based on the patterned mask layer 2, and sequentially forming a first dielectric layer 14 covering the inner wall and bottom surface of the groove 13 and a shielding gate layer 15 filling the groove 13, and the upper surface of the shielding gate layer 15 is lower than the upper surface of the epitaxial layer 12 by a preset distance; thinning the first dielectric layer 14 covering the inner wall of the groove 13 above the shielding gate layer 15, and after thinning, a table 141 is formed at the contact between the first dielectric layer 14 and the top of the shielding gate layer 15, which is lower than the upper surface of the shielding gate layer 15, and etching back the shielding gate layer 15 so that the upper surface of the shielding gate layer 15 is flush with the table 141.
[0072] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.
[0073] Specifically, while ensuring device performance, the size, thickness and shape of the substrate 11 can be selected according to actual conditions and are not limited here.
[0074] Specifically, the doping type of the substrate 11 is the first conductive type, the conductive type of the epitaxial layer 12 is the first conductive type, and the doping concentration of the epitaxial layer 12 is less than the doping concentration of the substrate 1. While ensuring the device performance and the doping concentration of the epitaxial layer 12 is less than the doping concentration of the substrate 11, the doping concentration of the substrate 11 can be selected according to actual conditions and is no longer restricted here; the doping concentration of the epitaxial layer 12 can be selected according to actual conditions and is no longer restricted here.
[0075] Specifically, while ensuring device performance, the size, thickness and shape of the epitaxial layer 12 can be selected according to actual conditions and are not limited here.
[0076] As an example, the material of the mask layer 2 includes silicon nitride or other suitable dielectric materials.
[0077] Specifically, the method of forming the mask layer 2 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0078] Specifically, a mask buffer layer 20 is further provided between the mask layer 2 and the semiconductor layer 1 to facilitate the formation of the mask layer 2 .
[0079] Specifically, the method of forming the mask buffer layer 20 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.
[0080] Specifically, under the condition of ensuring the quality of the formed mask layer 2, the thickness of the mask buffer layer 20 can be selected according to actual conditions, and is not limited here.
[0081] Specifically, under the condition of ensuring the shielding performance of the mask layer 2 in the subsequent process, the thickness of the mask layer 2 can be selected according to actual conditions, and is not limited here.
[0082] Specifically, patterning the mask layer 2 includes the following steps: forming a patterned photoresist layer (not shown) on the upper surface of the mask layer 2; and etching the mask layer 2 and the mask buffer layer 20 in sequence based on the patterned photoresist layer to obtain the patterned mask layer 2.
[0083] Specifically, the method of forming the photoresist layer and the patterned photoresist layer is a commonly used photoresist coating, exposure, and development method, which will not be described in detail here.
[0084] Specifically, the method of etching the mask layer 2 includes dry etching, wet etching or other suitable methods; the method of etching the mask buffer layer 20 includes dry etching, wet etching or other suitable methods.
[0085] Specifically, Figure 7 , which is a schematic diagram of the cross-sectional structure after the groove 13 is formed, the method of forming the groove 13 on the upper surface layer of the epitaxial layer 12 includes dry etching, wet etching or other suitable methods.
[0086] Specifically, after forming the groove 13 and before forming the first dielectric layer 14, a step of removing the photoresist layer is also included. The method for removing the photoresist layer is a conventional photoresist stripping method, which will not be described in detail here.
[0087] As an example, the method of forming the first dielectric layer 14 includes thermal oxidation or other suitable methods. In this embodiment, a thick silicon oxide layer formed on the inner wall and bottom surface of the trench 11 by thermal oxidation is used as the first dielectric layer 14 .
[0088] Specifically, due to the shielding of the mask layer 2, in the process of forming the first dielectric layer 14 by the thermal oxidation process, the first dielectric layer 14 is only formed on the inner wall and bottom surface of the groove 13, thereby avoiding the formation of the first dielectric layer 14 on the upper surface of the semiconductor layer 1, thereby eliminating the step of removing the first dielectric layer 14 located on the upper surface of the semiconductor layer 1.
[0089] Specifically, under the condition of ensuring the device performance, the thickness of the first dielectric layer 14 can be selected according to actual conditions and is not limited here.
[0090] Specifically, Figure 8 As shown, it is a schematic diagram of the cross-sectional structure after the shielding gate layer 15 is formed. The formation of the shielding gate layer 15 includes the following steps: forming a shielding gate layer 15 that fills the groove 13 and covers the upper surface of the mask layer 2; removing the shielding gate layer 15 located on the upper surface of the mask layer 2 and the shielding gate layer 15 located in the groove 13 and at a preset height from the upper surface of the mask layer 2 to obtain the shielding gate layer 15 filling the bottom of the groove 13, that is, the upper surface of the shielding gate layer 15 is lower than the upper surface of the semiconductor layer 1 by a preset distance.
[0091] Specifically, the method of forming the shielding gate layer 15 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0092] Specifically, the method for removing the shielding gate layer 15 located on the upper surface of the mask layer 2 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods; the method for removing the shielding gate layer 15 located in the groove 13 includes dry etching, wet etching or other suitable methods.
[0093] Specifically, under the condition of ensuring the performance of the device, the distance between the upper surface of the shielding gate layer 15 and the upper surface of the semiconductor layer 1 can be selected according to actual conditions, and is not limited here.
[0094] As an example, Fig. 9 , which is a schematic diagram of the cross-sectional structure after the first dielectric layer 14 above the shielding gate layer 15 is thinned, and the method of thinning the first dielectric layer 14 includes wet etching or other suitable methods.
[0095] Specifically, since wet etching has the characteristics of isotropy and high etching selectivity, when the first dielectric layer 14 is etched by wet etching, the etchant will have an etching effect on the first dielectric layer 14 that is in contact with the etchant, resulting in the contact between the first dielectric layer 14 and the top of the shielding gate layer 15 to produce the table 141 that is lower than the upper surface of the shielding gate layer 15.
[0096] Specifically, after the first dielectric layer 14 is thinned, the first dielectric layer 14 with a preset thickness is attached to the inner wall of the groove 13 above the mesa 141, so as to facilitate the subsequent formation of the second dielectric layer on the inner wall of the groove 13 (see the subsequent Fig.11 ).
[0097] Specifically, under the condition of ensuring device performance and facilitating the formation of the second dielectric layer, the thickness of the thinned first dielectric layer 14 can be selected according to actual conditions, and is not limited here.
[0098] Specifically, Fig.10 , which is a schematic diagram of the cross-sectional structure after the shielding gate layer 15 is etched back, and the method of etching back the shielding gate layer 15 includes dry etching, wet etching or other suitable methods.
[0099] See also Figures 11 to 15 , perform step S4 and step S5: form a second dielectric layer 3 covering the exposed surface of the first dielectric layer 14 and the shielding gate layer 15, the second dielectric layer 3 and the first dielectric layer 14 are made of a different material, and remove the second dielectric layer 3 covering the mesa 141 and the upper surface of the shielding gate layer 15; use the second dielectric layer 3 and the mask layer 2 as masks to form an isolation layer 4, and remove the second dielectric layer 3 and the first dielectric layer 14 covering the inner wall of the groove 13 above the isolation layer 4.
[0100] As an example, the material of the second dielectric layer 3 includes silicon nitride or other suitable dielectric materials.
[0101] Specifically, Fig.11 , which is a schematic diagram of the cross-sectional structure after the second dielectric layer 3 is formed. The method for forming the second dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0102] As an example, Fig.12 As shown, it is a schematic diagram of the cross-sectional structure after removing the second dielectric layer 3 covering the mesa 141 and the exposed surface of the shielding gate layer 15. The method for removing the second dielectric layer 3 covering the mesa 141 and the upper surface of the shielding gate layer 15 includes dry etching or other suitable methods. In this embodiment, dry etching is used to remove the second dielectric layer 3 covering the mesa 141 and the upper surface of the shielding gate layer 15. Since dry etching has anisotropic etching characteristics, the etchant can be adjusted by adjusting the ratio of each component in the etchant so that the etchant only etches the second dielectric layer 3 covering the mesa 141 and the upper surface of the shielding gate layer 15, and retains the second dielectric layer 3 located on the inner wall of the groove 13.
[0103] As an example, Fig.13 , which is a schematic diagram of the cross-sectional structure after the isolation layer 4 is formed, and the method for forming the isolation layer 4 includes thermal oxidation method or other suitable methods.
[0104] Specifically, in the process of forming the isolation layer 4 by the thermal oxidation method, due to the shielding effect of the second dielectric layer 3 and the mask layer 2, the isolation layer 4 is formed only at the exposed mesa 141 and the shielding gate layer 15, thereby avoiding the generation of sharp corners during the etching of the first dielectric layer 14, making the isolation layer 4 and the inner wall of the trench 13 locally thinner, causing the device to be prone to gate-source breakdown, and at the same time increasing the facing area between the gate and the source (emitter) of the device, so that the Miller capacitance C of the device rss Increase, affecting the switching time of the device.
[0105] Specifically, Fig.14 As shown, it is a schematic diagram of the cross-sectional structure after removing the first dielectric layer 14 covering the inner wall of the groove 13 above the isolation layer 4, removing the second dielectric layer 3 located on the inner wall of the groove 13 and removing the mask layer 2 located above the semiconductor layer 1; removing the first dielectric layer 14 located on the inner wall of the groove 13 above the isolation layer 4 and removing the mask buffer layer 20 located on the upper surface of the semiconductor layer 1.
[0106] Specifically, the method for removing the second dielectric layer 3 located on the inner wall of the groove 13 includes dry etching, wet etching or other suitable methods; the method for removing the first dielectric layer 14 located on the inner wall of the groove 13 above the isolation layer 4 includes dry etching, wet etching or other suitable methods.
[0107] As an example, Fig.15 As shown, it is a schematic diagram of the cross-sectional structure after the source contact hole 52 is formed. After removing the first dielectric layer 14 covering the inner wall of the groove 13 above the isolation layer 4, it also includes the steps of forming a gate dielectric layer 16, a gate conductive layer 17, a second conductive type body region 5, a first conductive type source region 51, a gate (not shown), a source (not shown) and a drain (not shown) to obtain a shielded gate trench MOS device.
[0108] Specifically, the gate dielectric layer 16 covers the exposed inner wall of the trench 13 and the exposed surface of the isolation layer 4 .
[0109] Specifically, the method for forming the gate dielectric layer 16 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods. In this embodiment, the gate dielectric layer 16 is formed by thermal oxidation.
[0110] Specifically, under the condition of ensuring the device performance, the thickness of the gate dielectric layer 16 can be selected according to actual conditions and is not limited here.
[0111] Specifically, the method of forming the gate conductive layer 17 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0112] Specifically, the gate conductive layer 17 fills the portion of the trench 13 located above the isolation layer 4 , and the gate dielectric layer 16 wraps the sidewalls and the bottom surface of the gate conductive layer 17 .
[0113] Specifically, the body region 5 is located on the upper surface of the epitaxial layer 12 and has a bottom surface no lower than a bottom surface of the gate conductive layer 17 , and the source region 51 is located on the upper surface of the body region 5 .
[0114] Specifically, the method of forming the body region 5 includes ion implantation or other suitable methods; the method of forming the source region 51 includes ion implantation or other suitable methods.
[0115] Specifically, the device is further provided with a source contact hole 52 penetrating the source region 51 and exposing the body region 5 on the bottom surface. The source fills the source contact hole 52 , and the gate is electrically connected to the gate conductive layer 17 .
[0116] Specifically, the method of forming the source contact hole 52 includes dry etching, wet etching or other suitable methods.
[0117] Specifically, under the condition that the device performance is guaranteed and the source contact hole 52 penetrates the source region 51, the opening size and depth of the source contact hole 52 can be selected according to the actual situation, and are not limited here. The depth here refers to the distance between the bottom surface of the source contact hole 52 and the top opening.
[0118] Specifically, a second conductive type source contact region (not shown) is provided in the body region 5 at the bottom of the source contact hole 52, and the source contact region forms an ohmic contact with the source. While ensuring the device performance, the doping concentration, thickness and size of the source contact region can be selected according to actual conditions and are no longer restricted here.
[0119] Specifically, the method of forming the source contact region includes ion implantation or other suitable methods.
[0120] Specifically, the drain electrode is electrically connected to the substrate 11 , and the contact type between the drain electrode and the substrate 11 is ohmic contact.
[0121] Specifically, the method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the source includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the drain includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0122] As an example, after removing the first dielectric layer 14 covering the inner wall of the trench 13 above the isolation layer 4, the method also includes the steps of forming a gate dielectric layer (not shown), a polysilicon gate layer (not shown), a second conductivity type base region (not shown), a first conductivity type emitter region (not shown), a second conductivity type emitter contact region (not shown), a gate (not shown), an emitter (not shown), a second conductivity type collector region (not shown) and a collector (not shown) to obtain a shielded gate trench IGBT device.
[0123] Specifically, since the gate dielectric layer and the polysilicon gate layer in the IGBT device have the same structure, material and formation method as the gate dielectric layer 16 and the gate conductive layer 17 of the MOS device, they are not described in detail here.
[0124] Specifically, the base region is located on the upper surface of the epitaxial layer 12 , and the bottom surface of the base region 12 is not lower than the bottom surface of the polysilicon gate layer, the emitter region is located on the upper surface of the base region, and the collector region is located at the bottom layer of the substrate 11 .
[0125] Specifically, the device is further provided with an emitter contact hole (not shown) penetrating the emitter region and exposing the base region at the bottom, and an emitter contact region, wherein the emitter contact region is located in the base region at the bottom of the emitter contact hole.
[0126] Specifically, the method of forming the emitter contact hole includes dry etching, wet etching or other suitable methods.
[0127] Specifically, the method of forming the base region includes ion implantation or other suitable methods; the method of forming the emitter region includes ion implantation or other suitable methods; the method of forming the emitter contact region includes ion implantation or other suitable methods; the method of forming the collector region includes ion implantation or other suitable methods.
[0128] Specifically, the emitter fills the emitter contact hole and forms ohmic contacts with the emitter contact region and the emitter region respectively, the collector is electrically connected to the collector region and forms ohmic contacts, and the gate is electrically connected to the polysilicon gate layer.
[0129] Specifically, the method for forming the emitter includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the collector includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.
[0130] Specifically, since the gate of the IGBT device and the gate of the MOS device are formed by the same method and material, they are not limited here.
[0131] Specifically, by forming the patterned mask layer 2 on the upper surface of the semiconductor layer 1 before the thermal oxidation process is used to form the first dielectric layer 14, it is avoided that the first dielectric layer 14 is formed on the upper surface of the semiconductor layer 1 at the same time as the first dielectric layer 14 is formed, and then the step of removing the first dielectric layer 14 covering the upper surface of the semiconductor layer 1 is avoided, thereby simplifying the process steps.
[0132] Specifically, by thinning the first dielectric layer 14 attached to the inner wall of the groove 13 and etching back the shielding gate layer 15, and then forming the second dielectric layer 3 located only on the inner wall of the groove 13, and forming the isolation layer 4 based on the second dielectric layer 3, it is avoided that the portion of the isolation layer 4 close to the inner wall of the groove 13 forms a sharp corner, resulting in an increase in the facing area between the source (emitter) and the gate of the device, and then causing the Miller capacitance of the device to increase. It also avoids the problem that the isolation layer 4 is difficult to fill the gap between the shielding gate layer 15 and the groove 13, thereby improving the quality of the isolation layer 4, effectively improving the breakdown stability of the gate and source (emitter) of the device, and improving the switching performance of the device, thereby improving the performance of the device, and the thickness of the isolation layer 4 can also be freely adjusted as needed.
[0133] The method for preparing the shielded gate trench device of the present embodiment improves the process of manufacturing the device. After forming the patterned mask layer 2 on the upper surface of the semiconductor layer 1, the trench 13, the first dielectric layer 14 located on the inner wall and bottom surface of the trench 13, and the shielded gate layer 15 filling the bottom of the trench 13 are sequentially formed based on the patterned mask layer 2, the first dielectric layer 14 located on the inner wall of the trench 13 above the shielded gate layer 15 is thinned to form the table 141 lower than the upper surface of the shielded gate layer 15, and then the shielded gate layer 15 is etched back to make the upper surface of the shielded gate layer 15 flush with the table 141, and then a layer covering the top of the table 141 is formed. The second dielectric layer 3 is formed on the surface of the first dielectric layer 14, and the isolation layer 4 is formed based on the second dielectric layer 3 and the mask layer 2, so that the thickness of the isolation layer 4 can be freely adjusted as needed, and at the same time, it is avoided that the portion of the isolation layer 4 close to the inner wall of the groove 13 forms a sharp corner, which leads to an increase in the facing area between the gate and the source (emitter) in the device, and it is also avoided that the isolation layer 4 is difficult to fill the gap between the shielding gate layer 15 and the groove 13, thereby improving the quality of the isolation layer 4, effectively improving the breakdown stability of the gate and the source (emitter) of the device, avoiding the increase of the Miller capacitance of the device, improving the switching performance of the device, and then improving the performance of the device.
[0134] Embodiment 2
[0135] This embodiment provides a shielded gate trench device, such as Fig.15 , which is a schematic diagram of a partial cross-sectional structure of the shielded gate trench device. The shielded gate trench device is manufactured using the shielded gate trench device manufacturing method described in Example 1.
[0136] Specifically, when the shielded gate trench device is a MOS device, the shielded gate trench device includes a semiconductor layer 1, a trench 13, a first dielectric layer 14, a shielding gate layer 15, an isolation layer 4, a gate dielectric layer 16, a gate conductive layer 17, a second conductive type body region 5, a first conductive type source region 51, a source contact hole 52, a second conductive type source contact region, a gate, a source and a drain, wherein the semiconductor layer 1 includes a substrate 11 and an epitaxial layer 12 stacked in sequence; a plurality of the trenches 13 arranged at intervals are embedded in the upper surface layer of the epitaxial layer 12; the first dielectric layer 14 covers the bottom surface and the inner wall of the bottom of the trench 13; the shielding gate layer 15 fills the bottom of the trench 13, and the first dielectric layer 14 wraps the sidewalls and the bottom surface of the shielding gate layer 15; the isolation layer 4 covers the first dielectric layer 14 and The exposed surface of the shielding gate layer 15; the gate dielectric layer 16 covers the isolation layer 4 and the exposed surface of the inner wall of the groove 13 above the isolation layer 4; the gate conductive layer 17 fills the upper part of the groove 13, and the gate dielectric layer 16 wraps the side wall and the bottom surface of the gate conductive layer 17; the body region 5 is located on the upper surface layer of the epitaxial layer 12 and the bottom surface is not lower than the bottom surface of the gate conductive layer 17; the source region 51 is located on the upper surface layer of the body region 5; the source contact hole 52 passes through the source region 51 and the bottom surface exposes the body region 5; the source contact region is located in the body region 5 at the bottom of the source contact hole 52; the gate is electrically connected to the gate conductive layer 17; the source fills the source contact hole 52; the drain covers the bottom surface of the substrate 11 and is electrically connected to the substrate 11.
[0137] Specifically, when the shielded gate trench device is an IGBT device, the shielded gate trench device includes a semiconductor layer 1, a trench 13, a first dielectric layer 14, a shielding gate layer 15, an isolation layer 4, a gate dielectric layer, a polysilicon gate layer, a second conductive type base region, a first conductive type emitter region, an emitter contact hole, a second conductive type emitter contact region, a gate, an emitter, a second conductive type collector region and a collector, wherein the semiconductor layer 1 includes a substrate 11 and an epitaxial layer 12 stacked in sequence; a plurality of the trenches 13 arranged at intervals are embedded in the upper surface layer of the epitaxial layer 12; the first dielectric layer 14 covers the bottom surface and the inner wall of the bottom of the trench 13; the shielding gate layer 15 fills the bottom of the trench 13, and the first dielectric layer 14 wraps the sidewall and the bottom surface of the shielding gate layer 15; the isolation layer 4 covers the first dielectric layer 11. The exposed surface of the electrical layer 14 and the shielding gate layer 15; the gate dielectric layer covers the isolation layer 4 and the exposed surface of the inner wall of the groove 13 above the isolation layer 4; the polysilicon gate layer fills the upper part of the groove 13, and the gate dielectric layer wraps the side wall and the bottom surface of the polysilicon gate layer; the base region is located on the upper surface layer of the epitaxial layer 12 and the bottom surface is not lower than the bottom surface of the polysilicon gate layer; the emitter region is located on the upper surface layer of the base region; the emitter contact hole passes through the emitter region and the bottom surface exposes the base region; the emitter contact region is located in the base region at the bottom of the emitter contact hole; the gate is electrically connected to the polysilicon gate layer; the emitter fills the emitter contact hole; the collector region is located on the lower surface layer of the substrate 11; the collector covers the collector region and is electrically connected to the collector region.
[0138] Specifically, the substrate 1 is made of silicon, silicon carbide, silicon germanium or other suitable semiconductor materials.
[0139] Specifically, a mask buffer layer 20 is further provided between the mask layer 2 and the semiconductor layer 1 , so as to form the mask layer 2 with better quality.
[0140] Specifically, the material of the mask buffer layer 20 includes silicon oxide or other dielectric film layers that enhance the bonding force between the mask layer 2 and the semiconductor layer 1 .
[0141] Specifically, the material of the mask layer 2 includes silicon nitride or other suitable materials.
[0142] Specifically, under the condition of ensuring the performance of the device, the depth and opening size of the groove 13 can be selected according to actual conditions and are not limited here.
[0143] Specifically, the material of the first dielectric layer 14 includes silicon oxide or other suitable dielectric materials.
[0144] Specifically, the shielding gate layer 15 is made of polysilicon or other suitable conductive materials.
[0145] Specifically, the material of the isolation layer 4 includes silicon oxide or other suitable dielectric materials.
[0146] Specifically, the material of the gate dielectric layer 16 includes silicon oxide or other suitable dielectric materials; the material of the gate dielectric layer includes silicon oxide or other suitable dielectric materials.
[0147] Specifically, the gate conductive layer 17 is made of polysilicon or other suitable conductive materials.
[0148] Specifically, the material of the gate includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten or other suitable conductive materials.
[0149] Specifically, while ensuring device performance and forming ohmic contact between the source electrode and the source region 51, the doping concentration, thickness and size of the body region 5 can be selected according to actual conditions and are no longer restricted here; the doping concentration, thickness and size of the source region 51 can be selected according to actual conditions and are no longer restricted here.
[0150] Specifically, the material of the source electrode includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten or other suitable conductive materials; the material of the drain electrode includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten or other suitable conductive materials.
[0151] Specifically, under the condition of ensuring the performance of the device, the doping concentration, thickness and size of the base region can be selected according to the actual situation, and are not limited here; the doping concentration, thickness and size of the emitter region can be selected according to the actual situation, and are not limited here; the doping concentration, thickness and size of the emitter contact region can be selected according to the actual situation, and are not limited here; the opening size and depth of the emitter contact hole can be selected according to the actual situation, and are not limited here; the doping concentration and thickness of the collector region can be selected according to the actual situation, and are not limited here. The depth here refers to the distance between the bottom surface of the emitter contact hole and the opening of the emitter contact hole.
[0152] Specifically, the material of the emitter includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten or other suitable conductive materials; the material of the collector includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten or other suitable conductive materials.
[0153] Specifically, since the shielded gate trench device is manufactured by adopting the shielded gate trench device described in the first embodiment, the quality of the isolation layer 4 is improved, thereby improving the breakdown resistance performance of the device.
[0154] The shielded gate trench device of this embodiment is manufactured by adopting the method for manufacturing the shielded gate trench device described in the first embodiment, thereby improving the quality of the isolation layer 4 in the device and further improving the breakdown resistance performance of the device.
[0155] In summary, the shielded gate trench device and its preparation method of the present invention form a patterned mask layer on the upper surface of the semiconductor layer by optimizing the process of manufacturing the device, and sequentially form a groove, a first dielectric layer and a shielded gate layer based on the patterned mask layer, then thin the first dielectric layer covering the inner wall of the trench above the shielded gate layer, and form a table while thinning the first dielectric layer, and etch the shielded gate layer back so that the upper surface of the shielded gate layer is flush with the table, and then form a second dielectric layer covering the surface of the first dielectric layer above the table, and use the second dielectric layer and the mask layer as a mask to form an isolation layer. The thickness of the obtained isolation layer can be freely adjusted as needed, avoiding the formation of sharp corners in the portion of the isolation layer close to the inner wall of the trench, resulting in an increase in the facing area of the gate and the source (emitter) of the device, thereby avoiding the problem of an increase in the Miller capacitance of the device due to the formation in the isolation layer, and also avoiding the problem that the isolation layer is difficult to fill the gap between the shielded gate layer and the trench, thereby improving the switching performance of the device, improving the quality of the isolation layer, and effectively improving the breakdown stability between the gate and the source (emitter), thereby improving the performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0156] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a shielded gate trench device, characterized in that: The following steps are involved: Providing a semiconductor layer including a substrate and an epitaxial layer stacked in sequence, forming a mask layer on the upper surface of the epitaxial layer and patterning the mask layer; Based on the patterned mask layer, a plurality of grooves are formed on the upper surface of the epitaxial layer and are spaced apart from each other, and a first dielectric layer covering the inner wall and bottom of the groove and a shielding gate layer filling the groove are sequentially formed, wherein the upper surface of the shielding gate layer is lower than the upper surface of the epitaxial layer by a preset distance; The first dielectric layer covering the inner wall of the trench above the shielding gate layer is thinned, and after the thinning, a table lower than the upper surface of the shielding gate layer is formed at the contact point between the first dielectric layer and the top of the shielding gate layer, and the shielding gate layer is back-etched to make the upper surface of the shielding gate layer flush with the table; Forming a second dielectric layer covering the first dielectric layer and the exposed surface of the shielding grid layer, wherein the second dielectric layer is made of a different material from the first dielectric layer, and removing the second dielectric layer covering the mesa and the upper surface of the shielding grid layer; An isolation layer is formed by using the second dielectric layer and the mask layer as masks, and the second dielectric layer and the first dielectric layer covering the inner wall of the trench above the isolation layer are removed.
2. The method for preparing a shielded gate trench device according to claim 1, characterized in that: The material of the mask layer includes silicon nitride.
3. The method for preparing a shielded gate trench device according to claim 1, characterized in that: The method of forming the first dielectric layer includes a thermal oxidation method.
4. The method for preparing a shielded gate trench device according to claim 1, characterized in that: The method of thinning the first dielectric layer includes wet etching.
5. The method for preparing a shielded gate trench device according to claim 1, characterized in that: The method of removing the second dielectric layer covering the mesa and the upper surface of the shielding gate layer comprises dry etching.
6. The method for preparing a shielded gate trench device according to claim 1, characterized in that: The method of forming the isolation layer includes a thermal oxidation method.
7. The method for preparing a shielded gate trench device according to claim 1, characterized in that: The material of the second dielectric layer includes silicon nitride.
8. The method for preparing a shielded gate trench device according to claim 1, characterized in that: After removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method further includes forming a gate dielectric layer, a gate conductive layer, a second conductive type body region, a first conductive type source region, a gate, a source electrode and a drain electrode.
9. The method for preparing a shielded gate trench device according to claim 1, characterized in that: After removing the first dielectric layer covering the inner wall of the trench above the isolation layer, the method also includes the steps of forming a gate dielectric layer, a polysilicon gate layer, a second conductive type base region, a first conductive type emitter region, a second conductive type emitter contact region, a gate, an emitter, a second conductive type collector region and a collector.
10. A shielded gate trench device, characterized in that: The shielded gate trench device is manufactured by using the shielded gate trench device manufacturing method according to any one of claims 1 to 9.