Back contact solar cell based on dry fluorine etching polycrystalline silicon and preparation method thereof
In the preparation of solar cells through dry fluorine etching technology, the doped polysilicon layer is removed by laser film opening and fluorine-containing gas, which solves the problem of damage to the borosilicon glass layer and the phosphorus silicon glass layer in wet etching, and improves the Battery performance and reliability simplifies process flow and reduces costs.
Patent Information
- Application Number
- CN202411281987.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-01-10
AI Technical Summary
In the preparation process of existing solar cells, borosilicate glass layer (BSG) or phosphosilicate glass layer (PSG) masks are easily damaged during wet etching, resulting in poor phenomena such as leakage and short circuits, reducing battery performance and reliability. .
Using dry fluorine etching technology, laser film is performed in the target area of the doped silicon oxide layer, and fluorine-containing gas is used to remove the doped polysilicon layer below the film region to avoid corrosion of the BSG/PSG layer and simplify the process flow. And improve etching accuracy.
It effectively reduces the risk of battery leakage, improves battery performance, yield and reliability, simplifies the preparation process, and reduces production costs.
Smart Images
Figure CN119300512A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of solar photovoltaics, and in particular relates to a back-contact solar cell based on dry fluorine etching of polycrystalline silicon and a preparation method thereof. Background Art
[0002] The biggest feature of the back-contact battery is that the emitter and the metal contact are both on the back of the battery. The front of the battery is not affected by the metal electrode, so it has a higher short-circuit current Isc. At the same time, the back of the battery can allow wider metal grid lines to reduce the series resistance Rs, thereby increasing the fill factor FF. And this kind of battery with no obstruction on the front not only has high conversion efficiency, but also looks more beautiful. At the same time, the components of the full back electrode are easier to assemble. However, the preparation method of IBC batteries is relatively complicated and the process steps are cumbersome, requiring multiple steps of graphic and wet cleaning processes.
[0003] In order to reduce the complexity of the process, the borosilicate glass layer (BSG) or phosphorus silicon glass layer (PSG) naturally formed during the preparation process is usually used as a patterning mask, and then patterning is performed. This causes the BSG / PSG layer in the target area to remain in the battery structure and serve as a barrier layer for the next heterogeneous doping diffusion. Since wet cleaning and etching of the doped polysilicon layer below are required after patterning, the BSG / PSG layer will also be partially etched, which can easily cause the weak parts of the BSG / PSG layer in the local area to be penetrated by the etchant, resulting in "drilling". As a result, the BSG / PSG layer in the target area cannot achieve a good blocking effect in the subsequent heterogeneous diffusion doping, which ultimately leads to adverse phenomena such as leakage and short circuit in the finished battery, further reducing the battery performance, yield and reliability.
[0004] How to minimize the damage to the BSG / PSG layer mask during the solar cell manufacturing process to improve the performance and reliability of solar cells has become an urgent problem to be solved. Summary of the invention
[0005] The present invention aims to overcome the defects of low yield, poor performance and low reliability of solar cells in the prior art, and provides a back-contact solar cell based on dry fluorine etching of polycrystalline silicon and a preparation method thereof.
[0006] To achieve the above-mentioned purpose, the present invention is implemented by the following technical solutions: A method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon comprises the following steps: forming a tunneling layer on the back side of the silicon substrate; forming an amorphous silicon layer on the tunneling layer; converting the amorphous silicon layer into a doped polysilicon layer and forming a doped silicon oxide layer on the surface of the doped polysilicon layer; Laser film opening is performed in a target area of the doped silicon oxide layer; The doped polysilicon layer below the film opening area is removed.
[0007] The present invention uses a laser to remove the surface doped silicon oxide layer in the target area of the doped silicon oxide layer (that is, the area outside the area that needs to be retained), and then uses a fluorine-containing gas dry etching process to remove the doped polysilicon layer below the film opening area. Based on this, the present invention uses the difference in the selective etching of the doped silicon oxide layer and the doped polysilicon layer by dry fluorine etching to remove the doped polysilicon layer below the film opening area (that is, the area outside the area that needs to be retained). The BSG / PSG layer in the area that needs to be retained will not be corroded, and the doped polysilicon layer located below it can be well protected. On the one hand, the present invention uses dry etching instead of wet etching to remove the doped polysilicon layer below the film opening area, effectively avoiding the corrosion of the BSG / PSG layer in the traditional wet etching process, and further reducing the risk of leakage of the finished battery. On the other hand, the selectivity of wet etching is not as good as dry etching. Dry etching can accurately use the doped silicon oxide layer or the doped polysilicon layer as the etching stop layer, which helps to reduce the additional consumption of silicon substrate materials and further reduce production and manufacturing costs. The preparation method of the present invention has simple process, effectively improves the performance, yield and reliability of the prepared battery, and is conducive to promotion and application in production practice.
[0008] Preferably, before removing the doped polysilicon layer below the film opening area, the method further includes the following steps: The doped silicon oxide layer on the front side of the silicon substrate is removed by single-side etching.
[0009] Preferably, the laser wavelength used for film opening is 190~545nm.
[0010] Preferably, the laser used for opening the film is any one of a picosecond laser and a nanosecond laser.
[0011] Preferably, the area of the film opening region is larger than the area of the retained region of the doped silicon oxide layer.
[0012] The above arrangement helps to open the doped silicon oxide layer in the target area, thereby removing the doped silicon oxide layer on the surface by laser, making it easier to remove the doped polysilicon layer below the opened film area by dry fluorine etching.
[0013] Preferably, the process of removing the doped polysilicon layer below the film opening area is any one of non-plasma dry fluorine etching and plasma dry fluorine etching.
[0014] Preferably, the reaction gas in the non-plasma dry fluorine etching process is any one of F2, XeF2, CIF, CIF3, IF5, BrF5, and BrF3.
[0015] Preferably, the etching pressure in the non-plasma dry fluorine etching process is 0.2-8 Torr, and the etching temperature is room temperature.
[0016] Preferably, the etching time in the non-plasma dry fluorine etching process is 5s~5min.
[0017] Preferably, the etching method in the non-plasma dry fluorine etching process is any one of a continuous reaction and a pulse cycle reaction.
[0018] Preferably, the reaction gas in the plasma dry fluorine etching process is a mixture of Cl2, CF4 and HCl; a mixture of CCl4 and He; a mixture of HCl and HBr; CF4; a mixture of Cl2, HBr and O2; a mixture of SF6, O2 and Ar; a mixture of C4F6 and SF6; a mixture of HBr and O2; a mixture of HBr, O2 and He; a mixture of CF4 and O2; a mixture of CHF3, SF6 and O2; a mixture of NF3 and O2; a mixture of Ar and SF6; or a mixture of Ar, SF6 and Cl2.
[0019] The mixed gas of SF6 and O2 can be used for reactive ion etching of silicon. It relies on chemical etching of fluorine and has the advantage of being non-toxic, but the etched surface is relatively rough. Adding a certain amount of O2 to SF6 can achieve anisotropic etching with high etching selectivity, and mixing it with CHF3 can also obtain a smooth etching surface. In addition, when O2 is introduced, the reaction of O2 with fluorine sulfur groups prevents it from recombining with fluorine to form SF6, resulting in an increase in the concentration of fluorine atoms, thereby greatly increasing the etching rate of SF6 on silicon and improving the etching selectivity.
[0020] In addition, helium (He) and argon (Ar) are usually used as auxiliary dilution gases to obtain an ideal etching profile. Ar and He can increase the plasma potential, that is, increase the self-bias voltage, and can also play a directional bombardment role on the bottom of the doped polysilicon layer. The bombardment of argon shortens the adsorption and retention time of active oxygen atoms at the bottom of the doped polysilicon layer, greatly weakening the oxidation reaction of the doped polysilicon layer at the bottom.
[0021] Preferably, after removing the doped polysilicon layer below the film opening area, the method further includes the following steps: The tunneling layer in the area covered by the doped polysilicon layer below the opened film area is removed.
[0022] As a further preference, the solution for removing the tunneling layer in the area covered by the doped polysilicon layer below the opened film area is any one of HF solution and a mixed solution of HF and HCl.
[0023] As a further preferred method, the method of removing the tunneling layer in the area covered by the doped polysilicon layer below the opened film area comprises the following steps: When the tunneling layer is removed using an HF solution, the concentration of the HF solution is 1-10%, and the removal time is 5 s-5 min.
[0024] The use of a high concentration HF solution facilitates the removal of the tunneling layer in a shorter time.
[0025] As a further preferred method, the method of removing the tunneling layer in the area covered by the doped polysilicon layer below the opened film area comprises the following steps: When a mixed solution of HF and HCl is used to remove the tunneling layer, the concentration of the HCl solution is 1-5%, and the concentration of the HF solution is 0.2-1%.
[0026] Using a mixed solution of HF and HCl helps to further enhance the cleaning effect.
[0027] Preferably, the material of the tunneling layer is any one or more combinations of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide and silicon oxide.
[0028] Preferably, the thickness of the tunneling layer is 0.5-5 nm.
[0029] Preferably, the process for forming the tunneling layer is any one of a physical vapor deposition process, an atmospheric pressure chemical vapor deposition process (APCVD), a low pressure chemical vapor deposition process (LPCVD), a plasma chemical vapor deposition process (PECVD), a thermal oxidation process, and a chemical oxidation process.
[0030] Preferably, the amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer; the thickness of the amorphous silicon layer is 100-500 nm.
[0031] Preferably, the amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer; the thickness of the amorphous silicon layer is 100-500 nm.
[0032] As a further preference, when the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is of the first conductivity type.
[0033] More preferably, the doped amorphous silicon layer is any one of n-type doping and p-type doping.
[0034] Preferably, the process for forming the amorphous silicon layer is any one of a physical vapor deposition process (PVD), a low pressure chemical vapor deposition process (LPCVD), and a plasma chemical vapor deposition process (PECVD).
[0035] As a further preference, when the amorphous silicon layer is a doped amorphous silicon layer, the process of forming the amorphous silicon layer is an in-situ doping method.
[0036] As a further preference, the equipment for forming the amorphous silicon layer is a LPCVD device.
[0037] More preferably, the tunneling layer and the amorphous silicon layer can be continuously formed on the back side of the silicon substrate using the same LPCVD device.
[0038] By using the same LPCVD device to complete the two processes, the process flow can be simplified, which helps to reduce manufacturing time and thus reduce manufacturing costs. In addition, when the tunneling layer and the amorphous silicon layer are formed using the LPCVD device, the temperature difference between the operating temperature for forming the tunneling layer and the operating temperature for forming the amorphous silicon layer can be set in the range of 0 to 200°C. Preferably, the temperature difference can be in the range of 0 to 100°C. At this time, the operating temperature difference between the two processes is small, which is conducive to reducing the time required to change the operating temperature, thereby further improving the efficiency of continuously forming the tunneling layer and the amorphous silicon layer. At the same time, when the temperature difference is small, the parameter changes of the two process flows are small, which helps to control the temperature to be constant.
[0039] Preferably, the method for converting an amorphous silicon layer into a doped polycrystalline silicon layer comprises the following steps: When the amorphous silicon layer is an intrinsic amorphous silicon layer, high-temperature diffusion and annealing are performed on the intrinsic amorphous silicon layer to form a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer; When the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is annealed to form a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer.
[0040] As a further preference, the doped silicon oxide layer contains a dopant, and the dopant is boron or phosphorus.
[0041] Preferably, the doped silicon oxide layer is any one of a boron-doped silicon oxide layer and a phosphorus-doped silicon oxide layer.
[0042] As a further preference, the doped silicon oxide layer is any one of a borosilicate glass layer (BSG) and a phosphosilicate glass layer (PSG).
[0043] Preferably, the silicon substrate is any one of an n-type semiconductor substrate and a p-type semiconductor substrate.
[0044] As a further preference, the material of the silicon substrate is any one of single crystal silicon and polycrystalline silicon.
[0045] A back-contact solar cell is prepared by the method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon as described above.
[0046] Therefore, the present invention has the following beneficial effects: (1) The present invention uses laser to remove the surface doped silicon oxide layer in the target area of the doped silicon oxide layer, and then uses a fluorine-containing gas dry etching process to remove the doped polysilicon layer below the film opening area. The preparation method is simple in process and effectively improves the performance, yield and reliability of the prepared battery, which is conducive to promotion and application in production practice; (2) The present invention utilizes the difference in the selective etching of the doped silicon oxide layer and the doped polysilicon layer by dry fluorine etching to remove the doped polysilicon layer below the film opening area. The BSG / PSG layer in the area to be retained will not be corroded, and the doped polysilicon layer below it can be well protected; (3) The present invention uses dry fluorine etching instead of wet etching to remove the doped polysilicon layer below the film opening area, effectively avoiding the corrosion of the BSG / PSG layer in the traditional wet etching process, and further reducing the leakage risk of the finished battery; (4) The dry fluorine etching process of the present invention can accurately use the doped silicon oxide layer or the doped polysilicon layer as the etching stop layer, which helps to reduce the additional consumption of silicon substrate materials and further reduce the production cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 Schematic diagram of the structure of a back-contact solar cell based on dry fluorine etching of polycrystalline silicon.
[0048] Figure 2 Schematic diagram of the silicon substrate structure.
[0049] Figure 3 Schematic diagram of the structure for depositing a tunneling layer and an amorphous silicon layer on the back of the battery.
[0050] Figure 4 A schematic diagram of the structure for forming a boron-doped polysilicon layer by diffusion and forming a BSG layer on the surface of the boron-doped polysilicon layer.
[0051] Figure 5 Schematic diagram of the structure for laser film opening in the target area of the BSG layer.
[0052] Figure 6 Schematic diagram of the structure for removing the boron-doped polysilicon layer below the film opening area by dry fluorine etching.
[0053] Figure 7A schematic diagram of the structure for removing the tunneling layer in the area covered by the boron-doped polysilicon layer below the opened film area.
[0054] Figure 8 The present invention is a schematic structural diagram of forming a phosphorus-doped polysilicon layer on a silicon substrate and forming a PSG layer on the surface of the phosphorus-doped polysilicon layer.
[0055] Fig. 9 Schematic diagram of the structure for laser film opening in the target area of the PSG layer.
[0056] Fig.10 Schematic diagram of the structure for removing the phosphorus-doped polysilicon layer below the film opening area by dry fluorine etching.
[0057] Fig.11 This is a schematic diagram of the structure of the finished battery cell after texturing, coating and metallization. DETAILED DESCRIPTION
[0058] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments of the specification. Those of ordinary skill in the art will be able to implement the present invention based on these descriptions. In addition, the embodiments of the present invention involved in the following description are generally only embodiments of a part of the present invention, rather than all embodiments. Therefore, based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work should fall within the scope of protection of the present invention.
[0059] Example 1 This embodiment provides a method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon.
[0060] A method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon comprises the following steps: (S.1) Provide a silicon substrate. The structure of the silicon substrate is as follows Figure 2 As shown. The silicon substrate can be an n-type semiconductor substrate or a p-type semiconductor substrate. The material of the silicon substrate is silicon, which can be single crystal silicon or polycrystalline silicon. The front and back of the silicon substrate are consistent with the front and back of the solar cell, the front side is the side facing the sunlight, and the back side is the backlight side. As an implementation method, the silicon substrate needs to be dedamaged and polished first, Figure 2 The silicon substrate shown in FIG. 1 is subjected to double-sided polishing. The polishing is performed using an alkaline solution with an additive. The most preferred silicon substrate in this embodiment is an n-type semiconductor substrate.
[0061] A tunneling layer is formed on the back side of the silicon substrate. The tunneling layer is formed on the entire back side of the silicon substrate. The tunneling layer can produce a tunneling effect, allowing majority carriers to pass through while blocking minority carriers from passing through. As an embodiment, the material of the tunneling layer can be various materials through which majority carriers can tunnel. For example, oxides, nitrides, semiconductors, and conductive polymers. As an embodiment, the material of the tunneling layer can be any one or more combinations of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide. The most preferred material for the tunneling layer in this embodiment is silicon oxide, which has good passivation characteristics, and carriers can easily tunnel through the silicon oxide layer. As an embodiment, the thickness of the tunneling layer is 0.5 to 5 nm.
[0062] As an implementation method, the process for forming the tunnel layer may be a physical vapor deposition process, or a chemical vapor deposition process such as an atmospheric pressure chemical vapor deposition process (APCVD), a low pressure chemical vapor deposition process (LPCVD), or a plasma chemical vapor deposition process (PECVD). As another implementation method, when the tunnel layer is a silicon oxide layer, the process for forming the tunnel layer may also be any one of a thermal oxidation process and a chemical oxidation process.
[0063] As another embodiment, the pressure when forming the tunneling layer can be set lower than the atmospheric pressure to reduce the growth rate of the tunneling layer. For example, when forming the tunneling layer on the back side of the silicon substrate using a thermal oxidation process, the working pressure of the thermal oxidation process can be set lower than the atmospheric pressure. At this time, although the working temperature of the thermal oxidation process is relatively high (600°C or higher), due to the low working pressure, the tunneling layer can maintain a low growth rate, which can significantly reduce the thickness of the tunneling layer. Specifically, the working temperature of the thermal oxidation process can be set to 600-800°C, and the working pressure can be set to 600 Torr or lower, thereby effectively controlling the thickness of the tunneling layer.
[0064] The above-mentioned deposition process or thermal oxidation process for forming the tunnel layer can be performed in a deposition device. In view of the requirement of the process of forming the tunnel layer for a low-pressure environment, the tunnel layer can be manufactured in a low-pressure chemical vapor deposition device.
[0065] (S.2) An amorphous silicon layer is formed on the tunneling layer. The amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer. The thickness of the amorphous silicon layer is 100-500 nm.
[0066] When the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is of the first conductivity type. As another embodiment, the doped amorphous silicon layer is any one of n-type doping and p-type doping.
[0067] As an implementation manner, the process of forming the amorphous silicon layer is any one of a physical vapor deposition process (PVD), a low pressure chemical vapor deposition process (LPCVD), and a plasma chemical vapor deposition process (PECVD).
[0068] As another implementation manner, when the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer may be manufactured by in-situ doping.
[0069] As an implementation method, the device for forming the amorphous silicon layer is a LPCVD device. More preferably, in this embodiment, the same LPCVD device can be used to continuously form the tunneling layer and the amorphous silicon layer on the back side of the silicon substrate. The structure of depositing the tunneling layer and the amorphous silicon layer on the back side of the battery is as follows: Figure 3 shown.
[0070] By using the same LPCVD device to complete the two processes, the process flow can be simplified, which helps to reduce manufacturing time and thus reduce manufacturing costs. In addition, when the tunneling layer and the amorphous silicon layer are formed using the LPCVD device, the temperature difference between the operating temperature for forming the tunneling layer and the operating temperature for forming the amorphous silicon layer can be set in the range of 0 to 200°C. Further preferably, the temperature difference can be in the range of 0 to 100°C. At this time, the operating temperature difference between the two processes is small, which is conducive to reducing the time required to change the operating temperature, thereby further improving the efficiency of continuously forming the tunneling layer and the amorphous silicon layer. At the same time, when the temperature difference is small, the parameter changes of the two process flows are small, which helps to control the temperature to be constant.
[0071] (S.3) The amorphous silicon layer is converted into a doped polysilicon layer and a doped silicon oxide layer is formed on a surface of the doped polysilicon layer.
[0072] As an implementation manner, the doped silicon oxide layer is any one of a boron-doped silicon oxide layer and a phosphorus-doped silicon oxide layer.
[0073] As another implementation manner, the doped silicon oxide layer is any one of a borosilicate glass layer (BSG) and a phosphosilicate glass layer (PSG).
[0074] As an implementation method, when the amorphous silicon layer is an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer is subjected to high-temperature boron diffusion and annealing treatment, so that the intrinsic amorphous silicon layer is converted into a boron-doped polysilicon layer, and the outer layer of the boron-doped polysilicon layer is diffused to form a borosilicate glass layer (BSG). The thickness of the diffused borosilicate glass layer (BSG) is 30-60nm. The structure of diffusing to form a boron-doped polysilicon layer and forming a BSG layer on the surface of the boron-doped polysilicon layer is as follows: Figure 4 shown.
[0075] As another embodiment, a silicon substrate is placed in a boron diffusion furnace, and a boron source is used to perform boron diffusion treatment on the back side of the n-type silicon substrate at a temperature of 900 to 1050°C for 1 to 3 hours to form a p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer). The volume proportion of the boron source in the boron diffusion atmosphere in the boron diffusion furnace is 5 to 30%. The boron source can be selected from boron trichloride (BCl3) and / or boron tribromide (BBr3).
[0076] As an implementation method, when the amorphous silicon layer is an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer is subjected to high-temperature phosphorus diffusion and annealing treatment, so that the intrinsic amorphous silicon layer is converted into a phosphorus-doped polysilicon layer, and the outer layer of the phosphorus-doped polysilicon layer is diffused to form a phosphorus-silicate glass layer (PSG). The thickness of the diffused phosphorus-silicate glass layer (PSG) is 10-70nm. The structure of forming a phosphorus-doped polysilicon layer on a silicon substrate and forming a PSG layer on the surface of the phosphorus-doped polysilicon layer is as follows: Figure 8 shown.
[0077] As another implementation, a silicon substrate is placed in a phosphorus diffusion furnace, and a phosphorus source is used to perform phosphorus diffusion treatment on the back of the n-type silicon substrate at a temperature of 700 to 850°C for 1 to 3 hours to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer). The volume proportion of the phosphorus source in the phosphorus diffusion atmosphere in the phosphorus diffusion furnace is 20%. The phosphorus source can be phosphorus oxychloride (POCl3).
[0078] As an implementation method, when the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer only needs to be annealed to convert the doped amorphous silicon layer into a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer. The doped silicon oxide layer may contain a small amount of dopant, and the type of dopant is boron or phosphorus, depending on the doping type of the doped amorphous silicon layer.
[0079] (S.4) Laser opening is performed in a target area of the doped silicon oxide layer.
[0080] As an implementation method, the laser wavelength used for film opening is 190~545nm.
[0081] As an embodiment, the laser used for opening the film is any one of a picosecond laser and a nanosecond laser.
[0082] As an implementation method, the area of the film opening region is larger than the area of the doped silicon oxide layer retained region.
[0083] The above arrangement helps to open the doped silicon oxide layer in the target area, thereby removing the doped silicon oxide layer on the surface by laser, making it easier to remove the doped polysilicon layer below the opened film area by dry fluorine etching.
[0084] As another embodiment, laser film opening is performed in a target area of a borosilicate glass (BSG) layer. The structure of laser film opening in a target area of a BSG layer is as follows: Figure 5 shown.
[0085] As another embodiment, laser film opening is performed in a target area of a phosphosilicate glass (PSG) layer. The structure of laser film opening in a target area of a PSG layer is as follows: Fig. 9 In addition, the laser used for laser film opening in the target area of the PSG layer can be the same laser as the laser used for laser film opening in the target area of the BSG layer, or a different laser, such as a laser with lower power, can be used.
[0086] (S.5) Removing the doped polysilicon layer below the film opening area.
[0087] As an implementation manner, before removing the doped polysilicon layer below the film opening area, the following steps are also included: The doped silicon oxide layer on the front side of the silicon substrate is removed by single-side etching.
[0088] As an implementation manner, the process of removing the doped polysilicon layer below the film opening area is any one of non-plasma dry fluorine etching and plasma dry fluorine etching.
[0089] As an embodiment, the reaction gas in the non-plasma dry fluorine etching process is any one of F2, XeF2, CIF, CIF3, IF5, BrF5, and BrF3.
[0090] As an implementation mode, the etching pressure in the non-plasma dry fluorine etching process is 0.2-8 Torr, and the etching temperature is room temperature.
[0091] As an implementation method, the etching time in the non-plasma dry fluorine etching process is 5s~5min.
[0092] As another implementation, when the reaction gas in the non-plasma dry fluorine etching process is XeF2, the flow rate of XeF2 is 10-50 sccm, the carrier gas is N2, and the flow rate of the carrier gas is 20-200 sccm.
[0093] As an implementation mode, the etching method in the non-plasma dry fluorine etching process is any one of a continuous reaction and a pulse cycle reaction.
[0094] Among them, the pulse cycle reaction is to fill the reaction chamber with gas in a cyclic pulse manner, delay for a certain period of time, and after the etching reaction has been carried out for a period of time, the gas in the reaction chamber is evacuated and the etching tail gas is discharged, and then the next cycle is carried out until the etching result meets the actual needs. This etching method can make full use of the fluorine-containing gas to react with the doped polysilicon layer, which helps to reduce the gas consumption and further reduce the production cost.
[0095] As an embodiment, the reaction gas in the plasma dry fluorine etching process is a mixture of Cl2, CF4 and HCl; a mixture of CCl4 and He; a mixture of HCl and HBr; CF4; a mixture of Cl2, HBr and O2; a mixture of SF6, O2 and Ar; a mixture of C4F6 and SF6; a mixture of HBr and O2; a mixture of HBr, O2 and He; a mixture of CF4 and O2; a mixture of CHF3, SF6 and O2; a mixture of NF3 and O2; a mixture of Ar and SF6; or a mixture of Ar, SF6 and Cl2.
[0096] The mixed gas of SF6 and O2 can be used for reactive ion etching of silicon. It relies on chemical etching of fluorine and has the advantage of being non-toxic, but the etched surface is relatively rough. Adding a certain amount of O2 to SF6 can achieve anisotropic etching with high etching selectivity, and mixing it with CHF3 can also obtain a smooth etching surface. In addition, when O2 is introduced, the reaction of O2 with fluorine sulfur groups prevents it from recombining with fluorine to form SF6, resulting in an increase in the concentration of fluorine atoms, thereby greatly increasing the etching rate of SF6 on silicon and improving the etching selectivity.
[0097] In addition, helium (He) and argon (Ar) are usually used as auxiliary dilution gases to obtain an ideal etching profile. Ar and He can increase the plasma potential, that is, increase the self-bias voltage, and can also play a directional bombardment role on the bottom of the doped polysilicon layer. The bombardment of argon shortens the adsorption and retention time of active oxygen atoms at the bottom of the doped polysilicon layer, greatly weakening the oxidation reaction of the doped polysilicon layer at the bottom.
[0098] As another embodiment, when the doped silicon oxide layer is a borosilicate glass layer (BSG), a dry fluorine etching process is used to remove the boron-doped polysilicon layer below the film opening area. The structure of removing the boron-doped polysilicon layer below the film opening area by using a dry fluorine etching process is as follows: Figure 6 shown.
[0099] As another embodiment, when the doped silicon oxide layer is a phosphosilicate glass layer (PSG), a dry fluorine etching process is used to remove the phosphorus-doped polysilicon layer below the film opening area. The structure of removing the phosphorus-doped polysilicon layer below the film opening area by using a dry fluorine etching process is as follows: Fig.10 In addition, compared with the boron-doped polysilicon layer, the phosphorus-doped polysilicon layer is easier to remove.
[0100] As an implementation mode, after removing the doped polysilicon layer below the film opening area, the following steps are further included: The tunneling layer in the area covered by the doped polysilicon layer below the opened film area is removed.
[0101] As an implementation mode, when the doped silicon oxide layer is a borosilicate glass layer (BSG), after removing the boron-doped polysilicon layer below the film opening area, the following steps are further included: The tunneling layer in the area covered by the boron-doped polysilicon layer below the opened film area is removed. The structure of removing the tunneling layer in the area covered by the boron-doped polysilicon layer below the opened film area is as follows: Figure 7 shown.
[0102] As an implementation manner, the solution for removing the tunneling layer in the area covered by the doped polysilicon layer below the opened film area is any one of an HF solution and a mixed solution of HF and HCl.
[0103] As another embodiment, a method for removing the tunneling layer in the area covered by the doped polysilicon layer below the opened film area includes the following steps: When the tunneling layer is removed using an HF solution, the concentration of the HF solution is 1-10%, and the removal time is 5 s-5 min.
[0104] The use of a high concentration HF solution facilitates the removal of the tunneling layer in a shorter time.
[0105] As another embodiment, a method for removing the tunneling layer in the area covered by the doped polysilicon layer below the opened film area includes the following steps: When a mixed solution of HF and HCl is used to remove the tunneling layer, the concentration of the HCl solution is 1-5%, and the concentration of the HF solution is 0.2-1%.
[0106] The use of a mixed solution of HF and HCl helps to further enhance the cleaning effect. In addition, the silicon substrate below the tunneling layer serves as a stop layer for HF solution corrosion.
[0107] As an implementation method, the silicon substrate is subjected to alkali texturing. An alkali texturing solution containing NaOH or KOH with an additive is used, the temperature is 65-85°C, and the process time is 3-10 minutes. A pyramid-shaped texture surface is formed in the local area of the front and back of the silicon substrate, which can effectively reduce the reflection of light, thereby improving the efficiency of the battery.
[0108] As an implementation method, after the texturing process is completed, the front and back sides are plated, forming a passivation anti-reflection layer on the front side and a passivation layer on the back side.
[0109] As an implementation manner, the surface passivation and anti-reflection layer may be any one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and silicon carbide.
[0110] As an implementation method, metallization is performed after the coating process is completed. The metallization is achieved by screen printing silver paste and co-sintering or electroplating. Fig.11 The finished battery cell is shown.
[0111] This embodiment also provides a back-contact solar cell based on dry fluorine etching of polycrystalline silicon.
[0112] The structure of the back contact solar cell based on dry fluorine etching of polycrystalline silicon is as follows Figure 1 As shown. The back contact solar cell based on dry fluorine etching of polycrystalline silicon is prepared by the preparation method of the back contact solar cell as described above. The positive electrode and the negative electrode of the back contact solar cell based on dry fluorine etching of polycrystalline silicon are both arranged on the back side, and the positive electrode and the negative electrode are respectively in contact with the doped polycrystalline silicon layer below through the opening of the back passivation layer, and the doped polycrystalline silicon layer is arranged on the tunneling layer on the back side.
[0113] The above description is only a detailed description of the preferred embodiments and principles of the present invention. For ordinary technicians in this field, according to the ideas provided by the present invention, there will be changes in the specific implementation methods, and these changes should also be regarded as the protection scope of the present invention.
Claims
1. A method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon, characterized in that: The following steps are involved: forming a tunneling layer on the back side of the silicon substrate; forming an amorphous silicon layer on the tunneling layer; converting the amorphous silicon layer into a doped polysilicon layer and forming a doped silicon oxide layer on the surface of the doped polysilicon layer; Laser film opening is performed in a target area of the doped silicon oxide layer; The doped polysilicon layer below the film opening area is removed.
2. The method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 1, characterized in that: The process of removing the doped polysilicon layer below the film opening area is any one of non-plasma dry fluorine etching and plasma dry fluorine etching.
3. The method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 2, characterized in that: The reaction gas in the non-plasma dry fluorine etching process is any one of F2, XeF2, CIF, CIF3, IF5, BrF5, and BrF3.
4. The method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 2 or 3, characterized in that: The etching pressure in the non-plasma dry fluorine etching process is 0.2-8 Torr, and the etching temperature is room temperature.
5. The method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 2, characterized in that: The reaction gas in the plasma dry fluorine etching process is any one of a mixture of Cl2, CF4 and HCl; a mixture of CCl4 and He; a mixture of HCl and HBr; CF4; a mixture of Cl2, HBr and O2; a mixture of SF6, O2 and Ar; a mixture of C4F6 and SF6; a mixture of HBr and O2; a mixture of HBr, O2 and He; a mixture of CF4 and O2; a mixture of CHF3, SF6 and O2; a mixture of NF3 and O2; a mixture of Ar and SF6; and a mixture of Ar, SF6 and Cl2.
6. The method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 1, characterized in that: After removing the doped polysilicon layer below the film opening area, the following steps are also included: The tunneling layer in the area covered by the doped polysilicon layer below the opened film area is removed.
7. A method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 1 or 6, characterized in that: The material of the tunneling layer is any one or more combinations of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide.
8. The method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon according to claim 1, characterized in that: The amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer; the thickness of the amorphous silicon layer is 100-500 nm.
9. A back-contact solar cell prepared by the method for preparing a back-contact solar cell based on dry fluorine etching of polycrystalline silicon as described in any one of claims 1 to 8.