Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the field of photovoltaic technology, and provides a solar cell and a preparation method thereof, and a photovoltaic module, so as to avoid the electric leakage condition of doped regions with different doping types, thereby improving the photoelectric conversion efficiency. The solar cell comprises a substrate which comprises a front surface and a back surface which are oppositely arranged; the back surface of the substrate comprises a first doped region and a second doped region which are sequentially arranged at an interval, and an insulating region arranged between the first doped region and the second doped region; the doped polycrystalline silicon passivation contact structure is arranged in the first doped region, the doped amorphous silicon structure is arranged in the second doped region, and the passivation layer is arranged in the insulating region; the doped polycrystalline silicon passivation contact structure comprises a tunneling oxide layer and a doped polycrystalline silicon layer which are sequentially laminated on the back surface of the substrate; the doped amorphous silicon structure comprises a doped amorphous silicon layer, and the doped polycrystalline silicon layer and the doped amorphous silicon layer are different in doping type; wherein the passivation layer is not overlapped with the doped polycrystalline silicon passivation contact structure and the doped amorphous silicon structure respectively along the thickness direction of the substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of photovoltaic technology, and in particular to a solar cell and a method for preparing the same, and a photovoltaic module. Background Art

[0002] Photovoltaic power generation converts solar energy into electrical energy through photovoltaic modules, thus providing a green, environmentally friendly and renewable energy production method, which has been widely used in many fields. Photovoltaic modules include battery strings, which are composed of multiple solar cells connected together.

[0003] Back-contact solar cells are an important type of cells. The back of a back-contact solar cell has N-type doping regions and P-type doping regions arranged alternately, but adjacent N-type doping regions and P-type doping regions are prone to leakage, thereby reducing the photoelectric conversion efficiency. Summary of the invention

[0004] The embodiments of the present disclosure provide a solar cell and a method for preparing the same, and a photovoltaic module to avoid leakage in doping regions with different doping types, thereby improving photoelectric conversion efficiency.

[0005] According to some embodiments of the present disclosure, the embodiments of the present disclosure provide, on one hand, a solar cell, including a substrate, the substrate including a front side and a back side arranged opposite to each other;

[0006] The back side of the substrate comprises a first doping region and a second doping region which are arranged in sequence and at intervals, and an insulating region which is arranged between the first doping region and the second doping region;

[0007] The solar cell further comprises: a doped polysilicon passivation contact structure arranged in the first doping region, a doped amorphous silicon structure arranged in the second doping region, and a passivation layer arranged in the insulating region; the doped polysilicon passivation contact structure comprises: a tunneling oxide layer and a doped polysilicon layer stacked in sequence on the back side of the substrate; the doped amorphous silicon structure comprises a doped amorphous silicon layer, and the doping types of the doped polysilicon layer and the doped amorphous silicon layer are different;

[0008] The passivation layer does not overlap with the doped polysilicon passivation contact structure and the doped amorphous silicon structure along the thickness direction of the substrate.

[0009] According to some embodiments of the present disclosure, the surface of the tunneling oxide layer close to the substrate is lower than the surface of the doped amorphous silicon structure close to the substrate and the surface of the passivation layer close to the substrate along a preset direction, and the preset direction is the direction from the front side of the substrate to the back side of the substrate.

[0010] According to some embodiments of the present disclosure, a surface of the doped amorphous silicon structure close to the substrate and a surface of the passivation layer close to the substrate are arranged flush.

[0011] According to some embodiments of the present disclosure, a surface of the passivation layer close to the substrate is higher than a surface of the doped amorphous silicon structure close to the substrate along a preset direction;

[0012] Alternatively, the surface of the passivation layer close to the substrate is lower than the surface of the doped amorphous silicon structure close to the substrate along a preset direction.

[0013] According to some embodiments of the present disclosure, a surface of the tunneling oxide layer close to the substrate, a surface of the doped amorphous silicon structure close to the substrate, and a surface of the passivation layer close to the substrate are arranged flush with each other.

[0014] According to some embodiments of the present disclosure, in the substrate, the surface of the substrate in contact with the tunneling oxide layer, the surface of the substrate in contact with the doped amorphous silicon structure, and the surface of the substrate in contact with the passivation layer are all polished surfaces or velvet surfaces.

[0015] According to some embodiments of the present disclosure, in the substrate, the surface of the substrate in contact with the tunnel oxide layer is a polished surface, and the surface of the substrate in contact with the doped amorphous silicon structure and the surface of the substrate in contact with the passivation layer are both velvet surfaces.

[0016] According to some embodiments of the present disclosure, a width of the insulating region along the arrangement direction of the first doping region and the second doping region ranges from 150 um to 300 um.

[0017] According to some embodiments of the present disclosure, the doped polysilicon passivation contact structure further includes: a first transparent conductive layer disposed on a side of the doped polysilicon layer away from the substrate;

[0018] The doped amorphous silicon structure further includes: an intrinsic hydrogenated amorphous silicon layer and a second transparent conductive layer arranged in the second doping region, the intrinsic hydrogenated amorphous silicon layer being arranged on a side of the doped amorphous silicon layer close to the substrate, and the second transparent conductive layer being arranged on a side of the doped amorphous silicon layer away from the substrate;

[0019] The solar cell also includes: an anti-reflection layer arranged in the insulating region, the anti-reflection layer is located on the side of the passivation layer away from the substrate; wherein the passivation layer and the anti-reflection layer do not overlap with the first transparent conductive layer and the second transparent conductive layer along the thickness direction of the substrate.

[0020] According to some embodiments of the present disclosure, the ratio of the overall thickness of the passivation layer and the anti-reflection layer to the overall thickness of the tunneling oxide layer, the doped polysilicon layer and the first transparent conductive layer is in the range of 1:1.3-1:2;

[0021] The ratio of the overall thickness of the passivation layer and the anti-reflection layer to the overall thickness of the intrinsic hydrogenated amorphous silicon layer, the doped amorphous silicon layer and the second transparent conductive layer is in the range of 1:1.2-1:2.

[0022] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a method for preparing a solar cell, comprising:

[0023] Providing a substrate; wherein the substrate comprises a front side and a back side arranged opposite to each other; the back side of the substrate comprises a first doping region and a second doping region arranged in sequence and spaced apart from each other, and an insulating region arranged between the first doping region and the second doping region;

[0024] A doped polysilicon passivation contact structure, a doped amorphous silicon structure and a passivation layer are respectively formed on the back side of the substrate; wherein the doped polysilicon passivation contact structure is arranged in the first doping region, and the doped polysilicon passivation contact structure comprises: a tunneling oxide layer and a doped polysilicon layer which are sequentially stacked on the back side of the substrate; the doped amorphous silicon structure is arranged in the second doping region, and the doped amorphous silicon structure comprises a doped amorphous silicon layer, and the doped polysilicon layer and the doped amorphous silicon layer have different doping types; the passivation layer is arranged in the insulating region, and the passivation layer does not overlap with the doped polysilicon passivation contact structure and the doped amorphous silicon structure respectively along the thickness direction of the substrate.

[0025] According to some embodiments of the present disclosure, a doped polysilicon passivation contact structure, a doped amorphous silicon structure and a passivation layer are respectively formed on the back side of a substrate, including:

[0026] A doped polysilicon passivation contact structure, a passivation layer and a doped amorphous silicon structure are sequentially formed on the back side of the substrate.

[0027] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a photovoltaic assembly, including:

[0028] A battery string, formed by connecting a plurality of solar cells as described in any one of the above items, or by connecting a plurality of solar cells formed by the above solar cell preparation method;

[0029] Encapsulation film, used to cover the surface of the battery string;

[0030] The cover plate is used to cover the surface of the packaging film facing away from the battery string.

[0031] The embodiments of the present disclosure provide a solar cell and a method for preparing the same, and a photovoltaic module. The solar cell provided by the embodiments of the present disclosure has an insulating region arranged between a first doping region and a second doping region, and the doped polysilicon passivation contact structure of the first doping region and the doped amorphous silicon structure of the second doping region are completely isolated by a passivation layer in the insulating region, without reducing the doping concentration of the doped polysilicon layer and the doped amorphous silicon layer. That is, leakage between the doped polysilicon passivation contact structure and the doped amorphous silicon structure can be avoided without reducing the performance of the cell, thereby improving the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of the structure of a solar cell provided in an embodiment of the present disclosure;

[0034] Figure 2 and Figure 3 for Figure 1 Schematic diagram of two cross sections along the cross-sectional direction CD;

[0035] Figures 4 to 7 To form Figure 3 Multiple structural schematic diagrams of a solar cell during the preparation process shown;

[0036] Figures 8 to 12 for Figure 1 Schematic diagrams of various cross sections along the cross-sectional direction CD;

[0037] Fig.13 for Figure 2 Bottom view of

[0038] Fig.14 A three-dimensional structural diagram of a photovoltaic module provided in an embodiment of the present disclosure;

[0039] Fig.15 for Fig.14 Schematic cross-section along section direction NN1. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be clearly and completely described below in combination with the specific embodiments of the present disclosure and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0041] In the description of the embodiments of the present disclosure, "at least one" means one or more, "at least one layer" means one or more layers, "multiple" means two or more, "multiple layers" means two or more layers, "multiple groups" means two or more groups, and "multiple pieces" means two or more pieces, unless otherwise clearly and specifically defined.

[0042] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features.

[0043] In the description of the embodiments of the present disclosure, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] In the description of the embodiments of the present disclosure, the orientation or positional relationship indicated by the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure. For example, if the device or element in the figure is inverted, then the element described as being "below" or "below" or "below" or "bottom" of other elements or features will be oriented "above" or "top" of the other elements or features. Therefore, the term "below" may cover both the above and below orientations depending on the context in which the term is used, which will be obvious to a person of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein can be interpreted accordingly.

[0046] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0047] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. In addition, when describing that a component is "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0048] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. A second component is formed or provided above or on a first component, or a second component is formed or provided on a surface of a first component, or a second component is formed or provided on one side of a first component, which may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which there may be additional components between the first component and the second component, so that the first component and the second component may not be in direct contact. For the sake of simplicity and clarity, various components may be arbitrarily drawn in different proportions. In the accompanying drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, a second component is formed or provided on the surface of a first component, which means that the first component is in direct contact with the second component. Among them, the above-mentioned "component" may refer to: layer, film, area, part, structure, etc.

[0049] The present disclosure provides a solar cell, including a substrate, wherein the substrate includes a front surface and a back surface that are oppositely disposed; Figure 1 As shown, the back side of the substrate 1 includes a first doping region A1 and a second doping region A2 which are sequentially arranged at intervals, and an insulating region A0 arranged between the first doping region A1 and the second doping region A2.

[0050] refer to Figure 2 , Figure 3 ,as well as Figures 8 to 12As shown, the solar cell also includes: a doped polysilicon passivation contact structure 11 arranged in the first doping area, a doped amorphous silicon structure 12 arranged in the second doping area, and a passivation layer 101 arranged in the insulating area; the doped polysilicon passivation contact structure 11 includes: a tunneling oxide layer 111 and a doped polysilicon layer 112 stacked in sequence on the back side of the substrate 1; the doped amorphous silicon structure 12 includes a doped amorphous silicon layer 121, and the doped polysilicon layer 112 and the doped amorphous silicon layer 121 have different doping types; wherein the passivation layer 101 does not overlap with the doped polysilicon passivation contact structure 11 and the doped amorphous silicon structure 12 along the thickness direction of the substrate.

[0051] In the doped polysilicon passivation contact structure of the disclosed embodiment, the doping element concentration of the doped polysilicon layer can be greater than the doping element concentration of the substrate, so that a sufficiently high potential barrier can be formed on the back side of the substrate, and the potential barrier can induce bending of the energy band on the back side of the substrate, realize the aggregation of majority carriers (also called majority carriers) and depletion of minority carriers (also called minority carriers) on the back side of the substrate, and reduce the recombination of carriers on the back side of the substrate. The tunneling oxide layer can cause an asymmetric shift in the energy band on the back side of the substrate, so that the potential barrier to majority carriers among the carriers is lower than the potential barrier to minority carriers among the carriers. Therefore, majority carriers can more easily perform quantum tunneling through the tunneling oxide layer to be transmitted to the doped polysilicon layer, while minority carriers find it difficult to pass through the tunneling oxide layer to realize selective transmission of carriers.

[0052] In addition, the tunneling oxide layer also has a chemical passivation effect. Specifically, due to the presence of interface state defects at the interface between the substrate and the tunneling oxide layer, the interface state density on the back of the substrate is relatively large. The increase in the interface state density will promote the recombination of photogenerated carriers, thereby reducing the fill factor, short-circuit current and open-circuit voltage of the solar cell, and thus making the photoelectric conversion efficiency of the solar cell low. The tunneling oxide layer plays a chemical passivation role by saturating the dangling bonds on the back of the substrate, thereby reducing the defect state density on the back of the substrate, and then reducing the recombination centers on the substrate surface to reduce the carrier recombination rate.

[0053] In the embodiment of the present disclosure, the material of the tunnel oxide layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or magnesium fluoride.

[0054] In the disclosed embodiment, the doped polysilicon layer can also play a field passivation effect. Specifically, the doped polysilicon layer forms an electrostatic field pointing to the inside of the substrate on the back of the substrate, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration and reducing the carrier recombination rate at the substrate interface, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0055] The doped polysilicon layer can be doped with the same type of doping elements as the substrate. For example, if the doping element type of the substrate is P-type, the doping element type of the doped polysilicon layer can also be P-type. In this case, the doping element type of the doped amorphous silicon layer can be N-type, that is, the first doping region is a P-type doping region, and the second doping region is an N-type doping region; if the doping element type of the substrate is N-type, the doping element type of the doped polysilicon layer can also be N-type. In this case, the doping element type of the doped amorphous silicon layer can be P-type, that is, the first doping region is an N-type doping region, and the second doping region is a P-type doping region.

[0056] In the disclosed embodiments, the doped polysilicon passivation contact structure provides good surface passivation for the back side of the substrate. The tunneling oxide layer allows majority carriers to tunnel into the doped polysilicon layer while blocking the recombination of minority carriers, so that majority carriers are transmitted laterally in the doped polysilicon layer and collected by the metal electrode, thereby greatly reducing the metal contact recombination current and improving the open circuit voltage and short circuit current of the solar cell.

[0057] In the disclosed embodiments, the structure of the doped amorphous silicon layer is not limited. For example, the doped amorphous silicon layer can be any one of a doped hydrogenated amorphous silicon layer (a-Si:H), a hydrogenated nanocrystalline silicon layer (nc-Si:H) and a hydrogenated nanocrystalline silicon oxide layer (nc-SiOx:H) or a stack of any multiple layers. The doping element type of the doped amorphous silicon layer is not limited. The P-type amorphous silicon layer is used as an example for explanation. For example, the P-type doped amorphous silicon layer can be a P-type hydrogenated amorphous silicon layer (a-Si:H(p)), a P-type hydrogenated nanocrystalline silicon layer (nc-Si:H(p)) or a P-type hydrogenated nanocrystalline silicon oxide layer (nc-SiOx:H(p)); or, the P-type doped amorphous silicon layer can also be a stacked structure of a P-type hydrogenated amorphous silicon layer, a P-type hydrogenated nanocrystalline silicon layer and a P-type hydrogenated nanocrystalline silicon oxide layer stacked in sequence on the back side of the substrate. In this stacked structure, the thickness ratio of the P-type hydrogenated amorphous silicon layer, the P-type hydrogenated nanocrystalline silicon layer and the P-type hydrogenated nanocrystalline silicon oxide layer is in the range of 1:3:1-1:10:1. Specifically, the thickness ratio of the P-type hydrogenated amorphous silicon layer, the P-type hydrogenated nanocrystalline silicon layer and the P-type hydrogenated nanocrystalline silicon oxide layer can be 1:3:1, 1:4:1, 1:5:1, 1:6:1, 1:7:1, 1:8:1, 1:9:1 or 1:10:1.

[0058] In the disclosed embodiments, the material of the passivation layer is not limited. For example, the material of the passivation layer can be silicon oxide, aluminum oxide, silicon nitride, silicon carbide or silicon oxynitride. On the one hand, silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride has good insulation properties and can play a good insulation effect to ensure that the doped polysilicon passivation contact structure and the doped amorphous silicon layer are insulated from each other; on the other hand, silicon oxide, aluminum oxide, silicon nitride and silicon oxynitride are all high-transmittance materials with a transmittance greater than 80%, which can greatly improve the bifaciality of solar cells.

[0059] In the disclosed embodiment, the doped polysilicon layer may be an N-type polysilicon layer, and the doped amorphous silicon layer may be a P-type amorphous silicon layer; or, the doped polysilicon layer may be a P-type polysilicon layer, and the doped amorphous silicon layer may be an N-type amorphous silicon layer. For example, the N-type polysilicon layer may be obtained by doping phosphorus into polysilicon, and the doping concentration of the phosphorus may range from 1E19 / cm^3 to 6E20 / cm^3. Specifically, the doping concentration of the phosphorus may be 1E19 / cm^3, 1E20 / cm^3, 2E20 / cm^3, 3E20 / cm^3, 4E20 / cm^3, 5E20 / cm^3 or 6E20 / cm^3.

[0060] In the embodiments of the present disclosure, the solar cell can be a single-sided cell, in which case the front side of the substrate can be used as a light-receiving surface for receiving incident light, and the back side can be used as a backlight surface. Alternatively, the solar cell can also be a double-sided cell, in which case both the front side and the back side of the substrate can be used as light-receiving surfaces for receiving incident light, the front side can be the main light-receiving surface, and the back side can be the secondary light-receiving surface. It can be understood that the backlight surface referred to in the embodiments of the present disclosure can also receive incident light, but the degree of receiving the incident light is weaker than that of the light-receiving surface, and therefore is defined as a backlight surface.

[0061] In the disclosed embodiment, a texturing process may be performed on at least one of the front or back surfaces of the substrate, so that a velvet surface is formed on at least one of the front or back surfaces of the substrate, which can enhance the absorption utilization rate of the front and back surfaces of the substrate for incident light. In some embodiments, the velvet surface may be a pyramid velvet surface, which not only reduces the reflectivity of the substrate surface, but also forms a light trap, enhances the substrate's absorption effect on incident light, and improves the photoelectric conversion efficiency of the solar cell.

[0062] For example, if the solar cell is a single-sided cell, a velvet surface can be formed on the light-receiving surface of the substrate, such as a pyramid velvet surface, and the backlight surface of the substrate can be a polished surface, so the backlight surface of the substrate is flatter than the light-receiving surface. It should be noted that for single-sided cells, velvet surfaces can also be formed on both the light-receiving surface and the backlight surface of the substrate. If the solar cell is a double-sided cell, velvet surfaces can be formed on both the light-receiving surface and the backlight surface of the substrate.

[0063] In the disclosed embodiment, the substrate is used to receive incident light and generate photogenerated carriers. The type of substrate is not limited. For example, the substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, and the N-type doping element may be any one of the Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be any one of the Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0064] In the embodiments of the present disclosure, the material of the substrate is not limited. For example, the material of the substrate can be an elemental semiconductor material. The elemental semiconductor material can be composed of a single element, for example, silicon or germanium. The morphology of the elemental semiconductor material can be single crystal, polycrystalline, amorphous or microcrystalline (a state having both single crystal and amorphous states is called microcrystalline), for example, silicon can be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon. Alternatively, the material of the substrate can also be a compound semiconductor material, for example, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride or copper indium selenide, etc.

[0065] In the embodiment of the present disclosure, the substrate may also be a sapphire substrate, a silicon on insulator substrate, or a germanium on insulator substrate.

[0066] In the embodiment of the present disclosure, a doped polysilicon passivation contact structure is arranged in the first doping region, and a doped amorphous silicon layer is arranged in the second doping region. The solar cell provided in the embodiment of the present disclosure is a hybrid back contact cell in which TOPCon (Tunnel Oxide Passivated Contact) cell technology is superimposed on HIT / HJT (Heterojunction Technology heterojunction cell) cell technology.

[0067] The size of the solar cell is not limited either. For example, the solar cell may be a complete cell, half a cell, or a quarter of a cell.

[0068] Compared to the related art, in which leakage is solved by reducing the doping concentration of the first doping region and the second doping region, the solar cell provided by the embodiment of the present disclosure has an insulating region between the first doping region and the second doping region, and the doped polysilicon passivation contact structure of the first doping region and the doped amorphous silicon structure of the second doping region are completely isolated by the passivation layer of the insulating region. There is no need to reduce the doping concentration of the doped polysilicon layer and the doped amorphous silicon layer. That is, leakage between the doped polysilicon passivation contact structure and the doped amorphous silicon structure can be avoided without reducing the battery performance, thereby improving the photoelectric conversion efficiency.

[0069] A set of test data is provided below to illustrate various performances of the solar cell provided by the embodiments of the present disclosure.

[0070] Among them, the embodiments of the present disclosure refer to Figure 1 The solar cell shown is provided with an insulating region, and the comparative example refers to a solar cell without an insulating region. The rest of the structures of the two are the same. Various test data are shown in Table 1.

[0071] Table 1

[0072] Voc Isc FF Eta Comparative Example 735mV <![CDATA[42.38mA / cm 2 ]]> 83.89％ 26.14％ Embodiments of the present disclosure 735mV <![CDATA[42.32mA / cm 2 ]]> 84.63％ 26.33％

[0073] It can be directly concluded from Table 1 that there is little difference between the embodiment of the present disclosure and the comparative example in terms of the open circuit voltage Voc and the short circuit current Isc, but the filling factor FF of the embodiment of the present disclosure is significantly greater than the filling factor FF of the comparative example, indicating that the contact electrical performance of the embodiment of the present disclosure is better. Therefore, the conversion efficiency Eta of the embodiment of the present disclosure is greater than the conversion efficiency Eta of the comparative example.

[0074] In the embodiment of the present disclosure, the area ratio of the insulating area to the back of the battery is not limited and can be limited according to actual conditions. For example, the percentage range of the area ratio of the insulating area to the back of the battery can be 10%-50%, for example: the percentage of the area ratio of the insulating area to the back of the battery is 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45% or 50%.

[0075] In the embodiment of the present disclosure, the area ratio of the first doped region to the back of the battery is not limited and can be limited according to actual conditions. For example, the percentage range of the area ratio of the first doped region to the back of the battery can be 10%-30%, for example: the percentage of the area ratio of the first doped region to the back of the battery is 10%, 13%, 15%, 18%, 20%, 23%, 25%, 28% or 30%.

[0076] In the embodiment of the present disclosure, the area ratio of the second doping region to the back of the battery is not limited and can be limited according to actual conditions. For example, the percentage range of the area ratio of the second doping region to the back of the battery can be 20%-40%, for example: the percentage of the area ratio of the second doping region to the back of the battery is 20%, 23%, 25%, 28%, 30%, 33%, 35%, 38% or 40%.

[0077] In the solar cell of the embodiment of the present disclosure, there is no limitation on the heights of the surface of the tunneling oxide layer close to the substrate, the surface of the doped amorphous silicon structure close to the substrate, and the surface of the passivation layer close to the substrate along a preset direction, wherein the preset direction is the direction from the front side of the substrate to the back side of the substrate.

[0078] It should be noted that the doped amorphous silicon structure may include multiple film layers, and the surface of the doped amorphous silicon structure close to the substrate refers to the surface of the film layer in the doped amorphous silicon structure that is in contact with the substrate and close to the substrate. For example, if the doped amorphous silicon structure includes a doped amorphous silicon layer, and the doped amorphous silicon layer is in contact with the substrate, then the surface of the doped amorphous silicon structure close to the substrate refers to the surface of the doped amorphous silicon layer close to the substrate. Figure 2 , Figure 3 ,as well as Figures 8 to 12 As shown, if the doped amorphous silicon structure 12 includes an intrinsic hydrogenated amorphous silicon layer 122 and a doped amorphous silicon layer 121 arranged in a stacked manner, wherein the intrinsic hydrogenated amorphous silicon layer 122 is arranged on a side of the doped amorphous silicon layer 121 close to the substrate 1, at this time, the intrinsic hydrogenated amorphous silicon layer 122 is in contact with the substrate 1, then the surface of the doped amorphous silicon structure 12 close to the substrate 1 refers to the surface of the intrinsic hydrogenated amorphous silicon layer 122 close to the substrate 1. Figure 2 , Figure 3 ,as well as Figures 8 to 12 The illustration is made by taking the case where the surface of the doped amorphous silicon structure close to the substrate is the surface of the intrinsic hydrogenated amorphous silicon layer close to the substrate as an example.

[0079] Specifically, refer to Figure 2 , Figure 3 ,as well as Figures 8 to 10 As shown, the surface 1110 of the tunneling oxide layer 111 close to the substrate 1 is lower than the surface 1220 of the doped amorphous silicon structure 12 close to the substrate 1 and the surface 1010 of the passivation layer 101 close to the substrate 1 along a preset direction OZ, and the preset direction OZ is the direction from the front side of the substrate 1 to the back side of the substrate 1.

[0080] In some embodiments, in order to facilitate production and reduce production difficulty, reference is made to Figure 2 , Figure 3 and Figure 8 As shown, the surface 1220 of the doped amorphous silicon structure 12 close to the substrate 1 is flush with the surface 1010 of the passivation layer 101 close to the substrate 1. At this time, the surface of the substrate in contact with the doped amorphous silicon structure and the surface of the substrate in contact with the passivation layer can both be polished or velvet.

[0081] In some embodiments, reference Fig.10 As shown, the surface 1010 of the passivation layer 101 close to the substrate 1 is higher than the surface 1220 of the doped amorphous silicon structure 12 close to the substrate 1 along the preset direction OZ; or, referring to Fig. 9 As shown, the surface of the passivation layer 101 close to the substrate 1 is lower than the surface of the doped amorphous silicon structure 12 close to the substrate 1 along the preset direction OZ.

[0082] Specifically, in order to facilitate production and reduce the difficulty of production, refer to Fig.11 and Fig.12As shown, a surface 1110 of the tunneling oxide layer 111 close to the substrate 1 , a surface 1220 of the doped amorphous silicon structure 12 close to the substrate 1 , and a surface 1010 of the passivation layer 101 close to the substrate 1 are arranged flush with each other.

[0083] In the substrate of the solar cell of the embodiment of the present disclosure, the types of the surfaces of the substrate contacting the tunneling oxide layer, the surface of the substrate contacting the doped amorphous silicon structure, and the surface of the substrate contacting the passivation layer are not limited.

[0084] Specifically, in one or more embodiments, in order to facilitate manufacturing and reduce the difficulty of manufacturing, the surface of the substrate 1 in contact with the tunneling oxide layer 111, the surface of the substrate 1 in contact with the doped amorphous silicon structure 10, and the surface of the substrate in contact with the passivation layer 101 are all as follows: Fig.10 and Fig.11 Polished surface as shown or Figure 8 Suede shown.

[0085] Alternatively, in one or more embodiments, considering the actual process conditions, reference Figure 3 As shown, in the substrate 1 , the surface of the substrate 1 in contact with the tunnel oxide layer 111 is a polished surface, and the surface of the substrate 1 in contact with the doped amorphous silicon structure 12 and the surface of the substrate 1 in contact with the passivation layer 101 are both velvet surfaces.

[0086] Of course, when the surface of the substrate in contact with the tunneling oxide layer is a polished surface, either the surface of the substrate in contact with the doped amorphous silicon structure or the surface of the substrate in contact with the passivation layer is a polished surface and the other is a velvet surface; specifically, the surface of the substrate in contact with the doped amorphous silicon structure is a polished surface, and the surface of the substrate in contact with the passivation layer is a velvet surface; or, the surface of the substrate in contact with the doped amorphous silicon structure is a velvet surface, and the surface of the substrate in contact with the passivation layer is a polished surface.

[0087] In one or more embodiments, in order to achieve a good insulation effect and minimize the area occupied by the back of the battery, the width of the insulating region along the arrangement direction of the first doping region and the second doping region is in the range of 150um-300um. For example, refer to Figure 2 As shown, the width D of the insulating region along the arrangement direction of the first doping region and the second doping region is 150um, 170um, 200um, 230um, 250um, 270um, 290um or 300um.

[0088] In one or more embodiments, the first doped region is an N-type doped region, and the second doped region is a P-type doped region, that is, the doped polysilicon layer is an N-type polysilicon layer, and the doped amorphous silicon layer is a P-type amorphous silicon layer. The first doped region is used to transmit electrons, and the second doped region is used to transmit holes. In this case, in order to ensure the transmission efficiency of electrons and holes, reference Figure 1 As shown, along the arrangement direction of the first doping region and the second doping region, the ratio of the width of the first doping region to the width of the second doping region is in the range of 1:4-1:7. By way of example, the ratio of the width of the first doping region to the width of the second doping region is 1:4, 1:4.3, 1:4.5, 1:4.7, 1:5, 1:5.3, 1:5.5, 1:5.7, 1:6, 1:6.3, 1:6.5, 1:6.7 or 1:7.

[0089] In one or more embodiments, reference Figure 2 , Figure 3 ,as well as Figures 8 to 12 As shown, the doped polysilicon passivation contact structure 11 further includes: a first transparent conductive layer 113 arranged on the side of the doped polysilicon layer 112 away from the substrate 1; the doped amorphous silicon structure 12 further includes: an intrinsic hydrogenated amorphous silicon layer 122 and a second transparent conductive layer 123 arranged in the second doping region, the intrinsic hydrogenated amorphous silicon layer 122 is arranged on the side of the doped amorphous silicon layer 121 close to the substrate 1, and the second transparent conductive layer 123 is located on the side of the doped amorphous silicon layer 121 away from the substrate 1; the solar cell further includes: an anti-reflection layer 102 arranged in the insulating region, the anti-reflection layer 102 is located on the side of the passivation layer 101 away from the substrate 1; wherein the passivation layer 101 and the anti-reflection layer 102 do not overlap with the first transparent conductive layer 113 and the second transparent conductive layer 123 along the thickness direction OZ of the substrate 1.

[0090] By setting a first transparent conductive layer, the conductivity of the doped polysilicon layer can be improved, and the reflectivity of the back of the battery can be improved; by setting a second transparent conductive layer, the conductivity of the doped amorphous silicon layer can be improved, and the reflectivity of the back of the battery can be improved. The materials of the first transparent conductive layer and the second transparent conductive layer can be the same, or different; considering the reduction of production costs, the materials of the first transparent conductive layer and the second transparent conductive layer can be the same; for example, the first transparent conductive layer and the second transparent conductive layer can be TCO (Transparent Conductive Oxides, transparent conductive oxide) films. Since the doped polysilicon layer, the doped amorphous silicon layer and the TCO film all have high parasitic absorption, the bifaciality of the battery will be reduced; in the embodiment of the present disclosure, an insulating region is set, and a passivation layer and an anti-reflection layer are set in the insulating region, so that the bifaciality of the battery can be increased while ensuring the conversion efficiency of the battery. By setting an intrinsic hydrogenated amorphous silicon layer, the contact performance between the doped amorphous silicon layer and the substrate can be improved, thereby improving the stability of the battery.

[0091] By setting an anti-reflection layer, the reflection damage on the back of the battery can be reduced. The anti-reflection layer can be a single-layer structure, and the material of the single-layer structure can be silicon oxynitride or silicon nitride. Alternatively, the anti-reflection layer can also be a laminated structure, which includes a first anti-reflection sublayer and a second anti-reflection sublayer arranged in a laminated manner, and the first anti-reflection sublayer is arranged between the passivation layer and the second anti-reflection sublayer; wherein the material of the first anti-reflection sublayer can be silicon nitride, and its thickness ranges from 10 to 40 nm. Specifically, the thickness of the first anti-reflection sublayer can be 10 nm, 13 nm, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, 30 nm, 33 nm, 35 nm, 38 nm or 40 nm. The material of the second anti-reflection sublayer can be silicon oxynitride, and its thickness ranges from 30 to 60 nm. Specifically, the thickness of the second anti-reflection sublayer can be 30 nm, 33 nm, 35 nm, 38 nm, 40 nm, 43 nm, 45 nm, 50 nm, 53 nm, 55 nm, 58 nm or 60 nm.

[0092] In the disclosed embodiment, the passivation layer and the anti-reflection layer do not overlap with the first transparent conductive layer and the second transparent conductive layer along the thickness direction of the substrate, which can better isolate the doped polysilicon passivation contact structure and the doped amorphous silicon structure and avoid leakage of the doped polysilicon passivation contact structure and the doped amorphous silicon structure.

[0093] In one or more embodiments, in order to reduce costs, reference Figure 2 , Figure 3 ,as well as Figures 8 to 12 As shown, the ratio of the overall thickness H2 of the passivation layer 101 and the anti-reflection layer 102 to the overall thickness H1 of the tunneling oxide layer 111, the doped polysilicon layer 112 and the first transparent conductive layer 113 is in the range of 1:1.3-1:2. For example, the ratio may be 1:1.3, 1:1.4, 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9 or 1:2; the ratio of the overall thickness H2 of the passivation layer 101 and the anti-reflection layer 102 to the overall thickness H3 of the intrinsic hydrogenated amorphous silicon layer 122, the doped amorphous silicon layer 121 and the second transparent conductive layer 123 is in the range of 1:1.2-1:2. For example, the ratio may be 1:1.2, 1:1.3, 1:1.4, 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9 or 1:2.

[0094] The overall thickness range of the passivation layer and the anti-reflection layer can be 70nm-120nm. For example, the overall thickness of the passivation layer and the anti-reflection layer can be 70nm, 75nm, 78nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm or 120nm; wherein the thickness range of the passivation layer is 2nm-10nm. For example, the thickness of the passivation layer can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm.

[0095] It should be noted that the reference Figure 2 , Figure 3 ,as well as Figures 8 to 12 As shown, the solar cell provided by the embodiment of the present disclosure may also include: a first electrode 13 arranged on the side of the first transparent conductive layer 113 away from the substrate 1, a second electrode 14 arranged on the side of the second transparent conductive layer 123 away from the substrate 1, a front passivation layer 16 and a front anti-reflection layer 17 arranged on the front side of the substrate 1, and the front anti-reflection layer 17 is arranged on the side of the front passivation layer 16 away from the substrate 1.

[0096] Among them, the first electrode is electrically connected to the doped polysilicon layer through the first transparent conductive layer, and the second electrode is electrically connected to the doped amorphous silicon layer through the second transparent conductive layer. In some embodiments, the doped polysilicon layer is an N-type polysilicon layer, and the doped amorphous silicon layer is a P-type amorphous silicon layer. In this case, the first electrode is a negative electrode and the second electrode is a positive electrode. Alternatively, the doped polysilicon layer is a P-type polysilicon layer, and the doped amorphous silicon layer is an N-type amorphous silicon layer. In this case, the first electrode is a positive electrode and the second electrode is a negative electrode. The first electrode and the second electrode can be sintered by a burn-through slurry. The material of the first electrode and the second electrode can be one or more of aluminum, silver, gold, nickel, molybdenum or copper. Reference Fig.13 As shown, the first electrode 13 and the second electrode 14 are fine grids (or auxiliary grids) of the solar cell, which are used to collect and summarize the current of the solar cell. Of course, the solar cell provided by the embodiment of the present disclosure may also include a third electrode and a fourth electrode, the third electrode is connected to one end of all the first electrodes, and the fourth electrode is connected to one end of all the second electrodes. The third electrode and the fourth electrode are the main grids of the solar cell, which are used to summarize the current of each fine grid. The material of the front passivation layer can be silicon oxide, aluminum oxide, silicon nitride, silicon carbide or silicon oxynitride. The structure of the front anti-reflection layer is the same as the structure of the anti-passivation layer arranged on the back of the substrate. For details, please refer to the above description, which will not be repeated here.

[0097] The present disclosure also provides a method for preparing a solar cell, including:

[0098] S1. Provide a substrate; wherein the substrate comprises a front side and a back side arranged opposite to each other; the back side of the substrate comprises a first doping region and a second doping region arranged in sequence and at intervals, and an insulating region arranged between the first doping region and the second doping region.

[0099] S2. A doped polysilicon passivation contact structure, a doped amorphous silicon structure and a passivation layer are respectively formed on the back side of the substrate; wherein the doped polysilicon passivation contact structure is arranged in the first doping region, and the doped polysilicon passivation contact structure includes: a tunneling oxide layer and a doped polysilicon layer stacked in sequence on the back side of the substrate; the doped amorphous silicon structure is arranged in the second doping region, and the doped amorphous silicon structure includes a doped amorphous silicon layer, and the doping types of the doped polysilicon layer and the doped amorphous silicon layer are different; the passivation layer is arranged in the insulating region, and the passivation layer does not overlap with the doped polysilicon passivation contact structure and the doped amorphous silicon structure respectively along the thickness direction of the substrate.

[0100] In the embodiments of the present disclosure, the relevant descriptions of the various structures in the solar cell can refer to the aforementioned embodiments and will not be repeated here.

[0101] In step S2, the preparation order of the doped polysilicon passivation contact structure, the doped amorphous silicon structure and the passivation layer is not limited and can be specifically selected according to the process equipment.

[0102] In the solar cell prepared by the above method, an insulating region is set between the first doping region and the second doping region, and the doped polysilicon passivation contact structure of the first doping region and the doped amorphous silicon structure of the second doping region are completely isolated by the passivation layer of the insulating region. There is no need to reduce the doping concentration of the doped polysilicon layer and the doped amorphous silicon layer. That is, leakage between the doped polysilicon passivation contact structure and the doped amorphous silicon structure can be avoided without reducing the performance of the battery, thereby improving the photoelectric conversion efficiency.

[0103] Since the manufacturing processes of the doped polysilicon passivation contact structure of the first doped region and the doped amorphous silicon structure of the second doped region are different, the process temperatures required for the two are also different. Specifically, the doped polysilicon passivation contact structure of the first doped region needs to be prepared in a high temperature (600°C-900°C) environment, and the doped amorphous silicon structure of the second doped region needs to be prepared in a low temperature (less than 250°C) environment. Therefore, in the actual manufacturing process, in order to avoid the influence of high temperature on the doped amorphous silicon layer, the doped polysilicon passivation contact structure of the first doped region is generally prepared first, and then the doped amorphous silicon structure of the second doped region is prepared.

[0104] Specifically, step S2, forming a doped polysilicon passivation contact structure, a doped amorphous silicon structure and a passivation layer on the back side of the substrate, respectively, includes:

[0105] S2', forming a doped polysilicon passivation contact structure, a passivation layer and a doped amorphous silicon structure in sequence on the back side of the substrate.

[0106] It should be noted that in the solar cell provided in the embodiments of the present disclosure, the preparation processes of the doped polysilicon passivation contact structure in the first doped region, the doped amorphous silicon structure in the second doped region, and the passivation layer in the insulating region are different. By adjusting the preparation sequence and process steps, any solar cell structure in the above embodiments can be obtained.

[0107] The following details how Figure 3 The method for preparing the solar cell shown.

[0108] The preparation method comprises:

[0109] S11. Clean, polish and texturize the silicon wafer.

[0110] S12. Form a tunneling oxide layer on the back side of the silicon wafer. The material of the tunneling oxide layer may be silicon oxide.

[0111] S13, forming a polysilicon layer on a side of the tunnel oxide layer away from the silicon wafer, and doping the polysilicon layer to obtain a doped polysilicon layer.

[0112] S14, performing graphic processing on the back side of the silicon wafer to remove the PSG (PhosphoSilicate Glass) layer in the insulating area and the second doping area.

[0113] S15. Remove PSG on the front side of the silicon wafer. Specifically, hydrofluoric acid (HF) may be used for removal.

[0114] S16, etching and texturing the front and back sides of the silicon wafer to remove the doped polysilicon layer in the insulating areas and the second doping areas on the front and back sides.

[0115] S17, cleaning and removing the PSG in the first doping region on the back of the silicon wafer, specifically, using hydrofluoric acid (HF) to remove the PSG, and obtaining the following: Figure 4 The structure shown.

[0116] S18. Form a front passivation layer on the front side of the silicon wafer. The material of the front passivation layer may be aluminum oxide, silicon oxide, or silicon carbide.

[0117] S19, forming a front anti-reflection layer on the side of the front passivation layer away from the silicon wafer; in order to protect the front anti-reflection layer in the subsequent wet process, a dense silicon nitride layer can also be formed on the side of the front anti-reflection layer away from the silicon wafer, and the thickness of the silicon nitride layer can be in the range of 2nm-10nm, and the Si:N atomic ratio thereof is in the range of 1:1.25-1.55:1. Specifically, the thickness of the silicon nitride layer can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, and the Si:N atomic ratio thereof is 1:1.25, 1:1.20, 1:1.15, 1:1.10, 1:1.05, 1.1:1, 1.2:1 or 1.25:1.

[0118] S20. Form a passivation layer on the back side of the silicon wafer.

[0119] S21, forming an anti-reflection layer on the side of the passivation layer on the back of the silicon wafer away from the silicon wafer; in order to protect the anti-reflection layer arranged on the back of the silicon wafer in the subsequent wet process, a dense silicon nitride layer can also be formed on the side of the anti-reflection layer on the back of the silicon wafer away from the silicon wafer, and the thickness of the silicon nitride layer can be in the range of 2nm-10nm, and the Si:N atomic ratio thereof is in the range of 1:1.25-1.55:1. Specifically, the thickness of the silicon nitride layer can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, and the Si:N atomic ratio thereof is 1:1.25, 1:1.20, 1:1.15, 1:1.10, 1:1.05, 1.1:1, 1.2:1 or 1.25:1.

[0120] S22, annealing the silicon wafer to improve the passivation level.

[0121] S23, performing patterning on the silicon wafer to remove the passivation layer and the anti-reflection layer in the first doping region and the second doping region, thereby obtaining Figure 5 The structure shown.

[0122] S24, cleaning the silicon wafer, specifically, using hydrofluoric acid (HF) for pickling.

[0123] S25. In a low temperature environment below 250 degrees Celsius, an intrinsic hydrogenated amorphous silicon layer a-Si:H(i) is deposited on the entire back side of the silicon wafer.

[0124] S26. In a low temperature environment below 250 degrees Celsius, deposit a doped amorphous silicon layer on the entire surface of the intrinsic hydrogenated amorphous silicon layer away from the silicon wafer.

[0125] S27, performing a patterning process on the back side of the silicon wafer to remove the intrinsic hydrogenated amorphous silicon layer and the doped amorphous silicon layer in the first doped region and the insulating region on the back side of the silicon wafer, thereby obtaining Figure 6 The structure shown.

[0126] S28. Form a TCO film on the entire back side of the silicon wafer.

[0127] S29, performing a patterning process on the TCO film to remove the TCO film in the insulating area, thereby obtaining Figure 7 The structure shown.

[0128] S30, using a screen printing process, forming a first electrode and a second electrode on the side of the TCO film in the first doping area and the second doping area on the back of the silicon wafer away from the silicon wafer, respectively, and finally obtaining Figure 3 The structure shown.

[0129] It should be noted that the specific process methods and equipment used in step 11 to step S30 can be obtained by referring to relevant technologies and will not be described in detail here.

[0130] The embodiment of the present disclosure further provides a photovoltaic module, which is used to convert received light energy into electrical energy. Fig.14 and Fig.15 As shown, the photovoltaic module includes: a battery string, which is formed by connecting multiple solar cells 40 formed by the preparation method provided in the above embodiment, or, is formed by connecting multiple solar cells 40 provided in the above embodiment; a packaging film 41, which is used to cover the surface of the battery string; a cover plate 42, which is used to cover the surface of the packaging film 41 away from the battery string.

[0131] It should be noted that the solar cells are electrically connected to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or in parallel. Since the solar cells include sliced ​​cells, and the sliced ​​cells are formed by segmenting the whole solar cell, the power loss of the photovoltaic module can be improved by the current drop of the sliced ​​cells, so as to improve the photoelectric conversion efficiency of the photovoltaic module.

[0132] In one or more embodiments, reference Fig.14 As shown, multiple battery cells can be electrically connected via conductive ribbons 402 . Fig.14 Only one positional relationship between solar cells is shown. Since the electrodes with positive polarity and the electrodes with negative polarity in the solar cells provided by the embodiments of the present disclosure are both arranged on the back side of the substrate, in order to improve the photoelectric conversion efficiency, Fig.14As shown, the front of all cells are arranged on the same side, the back of all cells are arranged on the same side, and the conductive strip 402 connects the same side of two adjacent cells 40. The photovoltaic module formed in this way can be applied to distributed photovoltaic scenes such as color steel tile roofs, photovoltaic tiles or photovoltaic curtain walls, such as photovoltaic building integration (BIPV), and of course can also be applied to other scenes requiring photoelectric conversion. The photovoltaic module has the characteristics of good quality and high quality.

[0133] In one or more embodiments, no intervals are provided between the battery cells, that is, the battery cells overlap each other.

[0134] In one or more embodiments, the encapsulation film includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front side or the back side of the solar cell, and the second encapsulation layer covers the other of the front side or the back side of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene co-elastomer (POE) film or a polyethylene terephthalate (PET) film.

[0135] In some cases, there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, the photovoltaic module is formed and there is no longer the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film.

[0136] In one or more embodiments, the cover plate may be a cover plate with a light-transmitting function such as a glass cover plate, a plastic cover plate, etc. Specifically, the surface of the cover plate facing the encapsulation film may be a concave-convex surface, thereby increasing the utilization rate of the incident light. The cover plate includes a first cover plate and a second cover plate, the first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer.

[0137] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A solar cell, characterized in that: The invention comprises a substrate, wherein the substrate comprises a front side and a back side which are arranged opposite to each other; The back side of the substrate comprises a first doping region and a second doping region which are sequentially arranged at intervals, and an insulating region which is arranged between the first doping region and the second doping region; The solar cell further comprises: a doped polysilicon passivation contact structure arranged in the first doping region, a doped amorphous silicon structure arranged in the second doping region, and a passivation layer arranged in the insulating region; the doped polysilicon passivation contact structure comprises: a tunneling oxide layer and a doped polysilicon layer stacked in sequence on the back side of the substrate; the doped amorphous silicon structure comprises a doped amorphous silicon layer, and the doped polysilicon layer and the doped amorphous silicon layer have different doping types; Wherein, the passivation layer does not overlap with the doped polysilicon passivation contact structure and the doped amorphous silicon doped amorphous silicon structure respectively along the thickness direction of the substrate.

2. The solar cell according to claim 1, characterized in that: The tunneling oxide layer is close to the surface of the substrate and is lower than the surface of the doped amorphous silicon structure close to the substrate and the surface of the passivation layer close to the substrate along a preset direction, and the preset direction is the direction from the front side of the substrate to the back side of the substrate.

3. The solar cell according to claim 2, characterized in that: The surface of the doped amorphous silicon layer close to the substrate is flush with the surface of the passivation layer close to the substrate.

4. The solar cell according to claim 2, characterized in that: The surface of the passivation layer close to the substrate is higher than the surface of the doped amorphous silicon structure close to the substrate along the preset direction; Alternatively, a surface of the passivation layer close to the substrate is lower than a surface of the doped amorphous silicon structure close to the substrate along the preset direction.

5. The solar cell according to claim 1, characterized in that: The surface of the tunneling oxide layer close to the substrate, the surface of the doped amorphous silicon structure close to the substrate, and the surface of the passivation layer close to the substrate are arranged flush with each other.

6. The solar cell according to any one of claims 1 to 5, characterized in that: In the substrate, the surface of the substrate in contact with the tunnel oxide layer, the surface of the substrate in contact with the doped amorphous silicon structure, and the surface of the substrate in contact with the passivation layer are all polished surfaces or velvet surfaces.

7. The solar cell according to any one of claims 1 to 5, characterized in that: In the substrate, the surface of the substrate in contact with the tunnel oxide layer is a polished surface, and the surface of the substrate in contact with the doped amorphous silicon structure and the surface of the substrate in contact with the passivation layer are both velvet surfaces.

8. The solar cell according to claim 1, characterized in that The width of the insulating region along the arrangement direction of the first doping region and the second doping region ranges from 150um to 300um.

9. The solar cell according to claim 1, characterized in that: The doped polysilicon passivation contact structure further includes: a first transparent conductive layer disposed on a side of the doped polysilicon layer away from the substrate; The doped amorphous silicon structure further includes: an intrinsic hydrogenated amorphous silicon layer and a second transparent conductive layer disposed in the second doped region, the intrinsic hydrogenated amorphous silicon layer being disposed on a side of the doped amorphous silicon layer close to the substrate, and the second transparent conductive layer being located on a side of the doped amorphous silicon layer away from the substrate; The solar cell further includes: an anti-reflection layer arranged in the insulating region, the anti-reflection layer being located on a side of the passivation layer away from the substrate; wherein the passivation layer and the anti-reflection layer do not overlap with the first transparent conductive layer and the second transparent conductive layer along a thickness direction of the substrate.

10. The solar cell according to claim 9, characterized in that: The ratio of the overall thickness of the passivation layer and the anti-reflection layer to the overall thickness of the tunneling oxide layer, the doped polysilicon layer and the first transparent conductive layer is in the range of 1:1.3-1:2; The ratio of the overall thickness of the passivation layer and the anti-reflection layer to the overall thickness of the intrinsic hydrogenated amorphous silicon layer, the doped amorphous silicon layer and the second transparent conductive layer is in the range of 1:1.2-1:

2.

11. A method for preparing a solar cell, characterized in that: include: Providing a substrate; wherein the substrate comprises a front side and a back side arranged opposite to each other; the back side of the substrate comprises a first doping region and a second doping region arranged in sequence and spaced apart, and an insulating region arranged between the first doping region and the second doping region; A doped polysilicon passivation contact structure, a doped amorphous silicon structure and a passivation layer are respectively formed on the back side of the substrate; wherein the doped polysilicon passivation contact structure is arranged in the first doping region, and the doped polysilicon passivation contact structure comprises: a tunneling oxide layer and a doped polysilicon layer stacked in sequence on the back side of the substrate; the doped amorphous silicon structure is arranged in the second doping region, and the doped amorphous silicon structure comprises a doped amorphous silicon layer, and the doped polysilicon layer and the doped amorphous silicon layer have different doping types; the passivation layer is arranged in the insulating region, and the passivation layer does not overlap with the doped polysilicon passivation contact structure and the doped amorphous silicon structure respectively along the thickness direction of the substrate.

12. The preparation method according to claim 11, characterized in that: The method of forming a doped polysilicon passivation contact structure, a doped amorphous silicon structure and a passivation layer on the back side of the substrate respectively comprises: The doped polysilicon passivation contact structure, the passivation layer and the doped amorphous silicon structure are sequentially formed on the back side of the substrate.

13. A photovoltaic module, characterized in that: include: A battery string formed by connecting a plurality of solar cells according to any one of claims 1 to 10, or by connecting a plurality of solar cells formed by the method for preparing a solar cell according to claim 11 or 12; A packaging film, used to cover the surface of the battery string; The cover plate is used to cover the surface of the packaging film away from the battery string.

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