Preparation method of full-color display array structure with light isolation

Abstract

The invention relates to the technical field of photoelectric devices, and discloses a preparation method of a full-color display array structure with optical isolation. The method comprises the following steps: firstly, arranging an LED material structure on a silicon-based gallium nitride epitaxial wafer, forming an LED table top by adopting an ICP etching process, and establishing an array structure; and then through further etching, isolation of the sub-pixels is realized, and accurate distribution of blue, red and green light-emitting areas is ensured. On the basis, a transparent electrode and an ohmic contact layer are arranged, a row control line electrode is formed, and ohmic contact is optimized, so that the conductivity is improved, and the contact resistance is reduced. And then an organic insulating material and an inorganic optical film are used for forming an optical isolation column, so that optical crosstalk between pixels is prevented, and the display image quality is improved. And finally, preparing the full-color display array by depositing an N-surface electrode, spraying fluorescent powder and integrating a driving circuit. According to the preparation method, the lighting effect and the color performance of the display array are improved, and the preparation method is suitable for high-resolution and high-brightness photoelectric display application.

Description

Technical Field

[0001] The invention relates to the technical field of optoelectronic devices and discloses a method for preparing a full-color display array structure with optical isolation. Background Art

[0002] At present, full-color display technology is widely used in various optoelectronic display devices, among which LED-based display arrays are widely used due to their high brightness, long life and low power consumption. In the preparation process of such display arrays, silicon-based gallium nitride (GaN-on-Si) materials have become a popular substrate material due to their compatibility with silicon-based integrated circuit processes and their superior thermal conductivity. At the same time, the use of ICP etching technology can form a fine LED table array on the substrate, and then by setting row and column electrodes, independent control of RGB sub-pixels can be achieved to achieve a full-color display effect. However, the existing full-color LED display array technology still faces some problems and challenges in practical applications, which seriously affect the performance of the display and user experience.

[0003] First, the optical crosstalk phenomenon still exists in the prior art. Although the prior art adopts an optical isolation column structure to reduce the optical interference between adjacent pixels, due to the limitations of materials and structural design, the optical isolation column cannot completely eliminate the light reflection between pixels, which still leads to a certain degree of color distortion and reduced luminous efficiency, which puts forward higher requirements for high-resolution and high-quality display effects. Secondly, the problem of excessively high electrode contact resistance has not been completely solved in the prior art. Although the existing P-side electrodes and N-side electrodes improve conductivity by adopting transparent electrode materials and ohmic contact layers, under high current conditions, the contact resistance will still limit the conductivity efficiency of the electrode, thereby affecting the overall stability and power consumption performance of the display array. In addition, material selection and compatibility issues also limit the long-term performance of the display array. In the prior art, silicon-based gallium nitride (GaN-on-Si) materials are often used to improve thermal conductivity, but due to the lattice mismatch between GaN and silicon, material defects are easily generated, resulting in reduced luminous efficiency and affecting the service life of the display.

[0004] In view of the above problems, the present invention proposes a method for preparing a full-color display array structure with optical isolation, which solves the problems of optical crosstalk, excessively high electrode contact resistance and poor material compatibility, and has significant technical advantages. Summary of the invention

[0005] The present invention relates to a method for preparing a full-color display array structure with optical isolation, aiming to solve the problems of display performance degradation caused by lattice mismatch, thermal expansion coefficient mismatch and optical crosstalk in the prior art. Due to problems such as lattice mismatch and stress, GaN materials are prone to defects on silicon-based materials, affecting luminous efficiency. Traditional optical isolation technology is difficult to effectively suppress optical crosstalk between adjacent pixels, resulting in reduced display quality. In the setting of the ohmic contact layer, the contact resistance is not effectively optimized, resulting in limited electrode conductivity, which in turn affects the overall performance of the display array.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] The present invention provides a method for preparing a full-color display array structure with light isolation, comprising:

[0008] S1: Prepare an array structure, set an LED material structure on a substrate to form an LED epitaxial wafer; use an ICP etching process to remove part of the epitaxial layer to form an LED table, and the LED table forms an array structure;

[0009] S2: isolating sub-pixels, respectively setting blue pixel units on the array structure, and continuing to etch the base using the ICP etching process to separate the blue pixel units into a blue light-emitting area, a red light-emitting area, and a green light-emitting area;

[0010] S3: preparing a row control line electrode, setting a transparent motor and an ohmic contact layer on the LED table to form a P-side electrode, and connecting the P-side electrodes of each sub-pixel to form a row control line electrode;

[0011] S4: preparing a light isolation column, forming a first part of an organic insulating column by coating and photolithography; forming a second part of an inorganic optical film by thin film deposition and etching; sleeve-mounting the second part on the first part; and arranging the light isolation column between the pixel unit gaps;

[0012] S5: preparing a column control line electrode, preparing an N-side electrode in a pixel unit gap, and connecting the N-side electrode of each sub-pixel to form a column control line electrode;

[0013] S6: spraying sub-pixels, thinning and polishing the back of the substrate, aligning each column of sub-pixels with a spraying process, aligning each column of red light-emitting areas and green light-emitting areas with a spraying process, and coating red phosphors and green phosphors in sequence;

[0014] S7: Adding a driving circuit to the P-side electrode and the N-side electrode led out from the front side of the substrate to complete the preparation of the wafer-level display array.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. The present invention designs a method for preparing a full-color display array structure with optical isolation. By selecting a silicon-based gallium nitride (GaN-on-Si) epitaxial wafer as the substrate material, the thermal conductivity and stability of the material are significantly improved. By calculating the lattice mismatch and thermal expansion coefficient mismatch, the defect generation of GaN materials on the silicon base is reduced, thereby improving the luminous efficiency and material stability. This optimization greatly improves the array structure of the LED table, thereby effectively improving the luminous efficiency of each pixel unit, avoiding the problem that traditional GaN materials are prone to defects on silicon-based materials, and can significantly extend the service life of the display array and improve the overall performance.

[0017] 2. The present invention introduces a combination of organic insulating columns and inorganic optical films in the optical isolation structure, and further reduces the optical crosstalk between adjacent pixels by precisely controlling the thickness and light reflection performance of the isolation columns. This design effectively improves the color purity and display quality of the pixels, especially in small pitch and high resolution applications. In addition, by controlling the transmittance of the optical isolation columns to specific wavelengths, the display effect is further improved, so that the display device can still maintain excellent image quality performance in complex light environments.

[0018] 3. In the design of the electrode, the present invention selects transparent conductive oxide materials (such as ITO, AZO, FTO) as the P-side electrode material. By combining an optimized deposition process, the contact resistance of the electrode is significantly reduced and the conductivity of the electrode is improved. Compared with the prior art, the present invention can maintain the stability and efficiency of the display array under high current, further reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It is understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a flow chart of the method of the present invention;

[0021] Figure 2 is a schematic diagram of sub-pixel spraying of the present invention; DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but is only for selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0023] Please refer to Figure 1-Figure 2 It is a flow chart of a method for preparing a full-color display array structure with light isolation provided by an embodiment of the present invention.

[0024] The present invention provides a method for preparing an array structure with a light-isolated full-color display, S1: preparing an array structure, arranging an LED material structure on a substrate to form an LED epitaxial wafer; using an ICP etching process to remove part of the epitaxial layer to form an LED table, and the LED table forms an array structure;

[0025] S101: Substrate material selection: GaN-on-Si epitaxial wafer is used as substrate material; this material has excellent thermal conductivity and stability, and is compatible with silicon-based integration processes. The lattice mismatch and thermal expansion coefficient mismatch can be calculated, as shown in formula (1)-formula (2);

[0026]

[0027] Δα=α GaN -α Si Formula (2)

[0028] Among them, ∈ is the lattice mismatch, a GaN and a Si Represent the lattice constants of GaN and Si respectively; Δα is the mismatch of thermal expansion coefficient, α GaN and α SiRepresent the thermal expansion coefficient mismatch of GaN and Si respectively; this formula is used to calculate the lattice mismatch and thermal expansion coefficient difference between gallium nitride (GaN) and silicon-based materials (Si). Lattice mismatch can cause stress and defects in the material during epitaxial growth, which can reduce the luminous efficiency and affect the stability of the display. Through this formula, the degree of mismatch between GaN and Si can be evaluated, and then the material performance can be optimized, defects can be reduced, and luminous efficiency can be improved by adjusting process parameters (such as deposition temperature and growth rate). And based on the calculation results of lattice mismatch, fine epitaxial growth control technology can be further developed to ensure the stability and efficient luminescence of the material by optimizing deposition temperature, deposition rate and stress management.

[0029] S102: LED material structure setting, depositing multiple LED material layers on the silicon-based gallium nitride epitaxial wafer through epitaxial growth, including an n-GaN layer, an active region layer and a p-GaN layer, and finally forming an LED epitaxial wafer. The epitaxial growth model is specifically as shown in formula (3);

[0030]

[0031] Where R is the material deposition rate, D s is the surface diffusion coefficient, D b is the volume diffusion coefficient; this formula is used to calculate the surface diffusion coefficient D during material deposition s and the bulk diffusion coefficient D b The relationship between can be used to control the material deposition rate. Through this formula, the conditions for epitaxial growth can be optimized to ensure uniform deposition of LED material structures. This is crucial to improving the luminous efficiency and display effect of each pixel in LED displays. And based on this formula, the epitaxial growth process of the material can be further optimized, and the uniformity and quality of the material can be controlled by adjusting the surface diffusion and body diffusion rates.

[0032] S103: forming an LED table array structure, using an ICP (plasma dry etching) process to etch away part of the epitaxial layer to form an LED table, wherein the LED table forms an array structure, and each table serves as a pixel unit. The ICP etching model and the array arrangement are specifically as shown in formula (4)-formula (5);

[0033]

[0034] Where E is the electric field strength, V biasis the bias voltage, d is the thickness of the etching gap; D is the array spacing, and N is the number of pixels per unit area. Formula (4) is used to calculate the electric field strength during the etching process. By adjusting the electric field strength, the etching rate and accuracy can be controlled to ensure that the etching depth of each sub-pixel is consistent, thereby improving the resolution and pixel uniformity of the display array. Based on this formula, a more accurate etching process control technology can be developed. By adjusting the electric field strength, high-precision graphic control can be achieved, which is particularly suitable for the manufacture of high-resolution displays. Formula (5) uses a standard rectangular or honeycomb arrangement to calculate the spacing of each pixel unit. ICP etching technology provides precise graphic control capabilities, ensuring the consistency of each pixel unit and high-resolution display effects.

[0035] S2: isolating sub-pixels, respectively setting blue pixel units on the array structure, and continuing to etch the base using the ICP etching process to separate the blue pixel units into a blue light-emitting area, a red light-emitting area, and a green light-emitting area;

[0036] S201: The base is further etched, and the ICP etching process is continued on each LED table to further divide the base to form red, green and blue light-emitting areas, as shown in formula (6);

[0037]

[0038] Among them, E is the etching rate, Δh is the etching depth, and Δt is the time; this formula is used to calculate the rate during the etching process. Through this formula, the etching process can be accurately controlled to ensure that the shape and size of each sub-pixel are consistent. This is very important for the high-resolution requirements of the display array, and can effectively reduce the light crosstalk and color distortion caused by uneven etching. The technical means derived from this formula is to dynamically adjust the etching parameters (such as plasma power and gas pressure), monitor and adjust the etching rate in real time, ensure high-precision array structure, improve production efficiency and display quality, especially in the production of small-pitch LED displays.

[0039] S202: photolithography mask control area, using photolithography mask technology to accurately control the area of ​​each sub-pixel to ensure that the RGB three colors are evenly distributed in the array, as shown in formula (7);

[0040] E exposure =I×t Formula (7)

[0041] Among them, E exposure is the exposure energy, I is the light intensity, and t is the exposure time; the sub-pixel area is defined by the photolithography process. The sub-pixel area is precisely controlled using photolithography mask technology to avoid optical crosstalk and color distortion. By optimizing the exposure energy and light intensity, the precise positioning of each sub-pixel area is ensured, thereby improving the overall image quality of the display.

[0042] S203: Processing stress and lattice mismatch, targeting the lattice mismatch problem between gallium nitride materials and silicon-based materials, using optimized etching process and annealing treatment to reduce defect density and improve the luminous efficiency of each sub-pixel, as shown in formula (8) to formula (9);

[0043]

[0044] Where, σ is stress, E is elastic modulus, ΔT is temperature change, ν is Poisson's ratio; ∈ is lattice mismatch ratio, a substrate is the lattice constant of the base material, a film is the lattice constant of the epitaxial layer material. Equation (9) is used to calculate the lattice mismatch rate between different materials, thereby optimizing the etching process and stress management.

[0045] S3: preparing a row control line electrode, setting a transparent motor and an ohmic contact layer on the LED table to form a P-side electrode, and connecting the P-side electrodes of each sub-pixel to form a row control line electrode;

[0046] S301: P-side electrode setting: on the top of each LED table (i.e., on the p-GaN layer), a transparent electrode and an ohmic contact layer are deposited to form a P-side electrode, and the P-side electrodes of all sub-pixels are connected together by photolithography and etching processes to form a row control line electrode. The light transmittance of the transparent electrode and the contact resistance of the ohmic contact layer are calculated and the ohmic contact optimization is performed as shown in formulas (10)-(12);

[0047]

[0048]

[0049] Where T is the transmittance, I transmitted is the transmitted light intensity, I incident is the incident light intensity; R c is the ohmic contact resistance, ρ is the contact resistivity, A is the contact area; I is the current passing through the electrode, V is the voltage, and R is the total resistance of the electrode; Formula (11) is used to calculate the ohmic contact resistance. This formula can be used to optimize the selection of transparent conductive materials and the design of contact area to reduce the contact resistance of the electrode and improve the conductivity of the electrode. Based on this formula, suitable transparent conductive materials (such as ITO, AZO, etc.) can be selected, and the contact resistance can be reduced by optimizing the deposition process to improve the efficiency of the display array. This technical means can effectively reduce power consumption and improve the stability and brightness of the display. Formula (12) is used to calculate the current distribution of the row control line electrode to ensure uniform current distribution.

[0050] S302: Ohmic contact optimization, in order to improve the conductivity of the electrode and reduce the contact resistance, select the appropriate transparent conductive oxide material and optimize the deposition conditions. The material selected is ITO, which is a common choice for transparent conductive materials with low resistivity and high light transmittance. AZO and FTO are also alternative materials with good conductivity and transparency, suitable for different application requirements. Deposition condition optimization is to optimize the electrical and optical properties of the TCO film by adjusting the working gas pressure, sputtering power, substrate temperature and post-processing conditions to achieve low contact resistance and high conductivity.

[0051] S4: preparing a light isolation column, forming a first part of an organic insulating column by coating and photolithography; forming a second part of an inorganic optical film by thin film deposition and etching; sleeve-mounting the second part on the first part; and arranging the light isolation column between the pixel unit gaps;

[0052] S401: Forming an organic insulating column, forming a first portion of an organic insulating column between sub-pixels by coating and photolithography; the insulating column material is polyimide, which has good insulation and thermal stability, and the coating thickness of the organic insulating material is calculated as shown in Formula (13);

[0053]

[0054] Where d is the coating thickness, V is the volume of the coating material, and A is the area of ​​the coating region;

[0055] S402: Formation of an inorganic optical film, using thin film deposition and etching methods to form a second portion of an inorganic optical film, such as a silicon nitride or silicon oxide film, on the outer surface of the organic insulating column. These materials can provide excellent light isolation effects.

[0056] S403: Setting optical isolation columns, setting the optical isolation columns between each pixel unit to avoid optical crosstalk between adjacent pixels, thereby improving display quality, and controlling the film thickness by a film deposition rate formula, as shown in formulas (14)-(15);

[0057]

[0058] Where, T(λ) is the transmittance of the optical isolation column for a specific wavelength, λ is the wavelength of light, n is the refractive index of the optical film, d is the thickness of the optical isolation column, and θ is the incident angle; R dep is the deposition rate, d film is the film thickness, t depis the deposition time. Formula (14) is used to calculate the transmittance of the optical isolation column to light of different wavelengths. This formula can be used to design optical isolation structures for different wavelengths to reduce optical crosstalk and improve display effects. Based on this formula, optical optimization technology can be developed to design the optimal optical isolation column structure for different display environments (such as outdoor or high-brightness scenes) to ensure color reproduction and brightness consistency. This technical approach can significantly improve the performance of the display, especially under complex lighting conditions. Formula (15) is used to calculate the rate of thin film deposition on the optical isolation column. By controlling the deposition rate, the thickness of the optical isolation column can be ensured to be uniform, thereby optimizing the optical performance of the display array and reducing optical crosstalk. Based on this formula, accurate thin film deposition technology can be derived. By adjusting the deposition rate, the thickness and reflective performance of the optical isolation column can be optimized. This technology can further improve the color purity and luminous efficiency of the display array.

[0059] S5: preparing a column control line electrode, preparing an N-side electrode in a pixel unit gap, and connecting the N-side electrode of each sub-pixel to form a column control line electrode;

[0060] S501: Setting the N-side electrode, depositing the N-side electrode material in the gap between each sub-pixel by sputtering or evaporation technology, and then connecting these electrodes by photolithography and etching technology to form a column control line electrode as shown in formula (15)-formula (16);

[0061]

[0062] Where J is the current density, I is the current passing through the N-side electrode, A is the cross-sectional area of ​​the N-side electrode, η is the injection efficiency, and V is the voltage. Formula (15) is used to optimize the size and material of the column control line electrode to ensure sufficient current density. Formula (16) calculates the injection efficiency using the current density calculated by Formula (15).

[0063] S502: Electrode interface optimization, optimizing the contact interface between the N-side electrode material and the gallium nitride layer, reducing the contact resistance and improving the current injection efficiency, using the minimized column control line electrode resistance as shown in formula (17);

[0064]

[0065] Where R is the resistance, ρ is the resistivity, L is the length of the electrode, and A is the cross-sectional area of ​​the electrode. The optimized connection of the column control line electrodes improves the control accuracy, reduces the complexity of the driving circuit, and enhances the response speed and stability of the display.

[0066] S6: spraying sub-pixels, thinning and polishing the back of the substrate, aligning each column of sub-pixels with a spraying process, aligning each column of red light-emitting areas and green light-emitting areas with a spraying process, and coating red phosphors and green phosphors in sequence;

[0067] S601: thinning and polishing the back side of the substrate, thinning and polishing the back side of the substrate to improve the light transmittance and reduce the overall thickness of the device, and calculating the back side thinning is specifically as shown in formula (18);

[0068]

[0069] Wherein, R is the thinning rate, H is the thickness after thinning, and t is the thinning time; Formula (18) is used to control the thickness and speed of substrate thinning to ensure the light transmittance of the device.

[0070] S602: Phosphor spraying: using precision spraying equipment to align each sub-pixel area, spraying red and green phosphors respectively. The red and green phosphors emit light under the light excitation of the blue LED, thereby achieving full-color display. The spraying is controlled by controlling the spraying density and the coverage and thickness of the spraying are calculated for feedback, as shown in formula (19)-formula (20).

[0071]

[0072] Where D is the coverage density of the spray, v is the spraying speed, t is the spraying time, and d is the distance between the nozzle and the substrate; A covered is the area covered by the phosphor, A total is the total area. Equation (19) is used to control the spraying density of red and green phosphors to ensure uniform light emission of each sub-pixel.

[0073] S7: Adding a driving circuit to the P-side electrode and the N-side electrode led out from the front side of the substrate to complete the preparation of the wafer-level display array.

[0074] S701: Design of the driving circuit, connecting the P-side electrode and the N-side electrode led out on the front side of the substrate, adding the driving circuit including the row driver, the column driver and the pixel driving circuit, completing the overall structural design of the wafer-level display array, by designing the voltage distribution and output control in the driving circuit and the total power consumption of the circuit, as shown in Formula (21)-Formula (22);

[0075] P=V×I Formula (21)

[0076]

[0077] Where P is power consumption, V is voltage, and I is current; V out is the output voltage of the drive circuit, V in is the input voltage, R 1 and R 2is a voltage divider resistor; Formula (21) is used to calculate the power consumption of the driving circuit. This formula can be used to optimize the design of the driving circuit, ensuring that the display works efficiently while reducing power consumption and extending the service life of the display array. Based on this formula, the circuit design can be optimized and low-power display driving technology can be developed, which is particularly suitable for display devices that are used for a long time, and can significantly reduce energy consumption and extend the life of the device.

[0078] S702: Circuit integration optimization. In the integrated circuit design, it is necessary to consider aspects such as electromagnetic compatibility, power management, and heat dissipation design. The stable operation of the display array is ensured by calculating the electromagnetic compatibility and the output current of the driving circuit, as shown in formula (23)-formula (24).

[0079]

[0080] Among them, I out is the output current of the driving circuit, V out is the output voltage of the driving circuit, R load is the load resistance; EMI is electromagnetic interference, V noise is the noise voltage and f is the frequency.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention has various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a full-color display array structure with optical isolation, characterized in that: The following steps are involved: S1: Prepare an array structure, set an LED material structure on a substrate to form an LED epitaxial wafer; use an ICP etching process to remove part of the epitaxial layer to form an LED table, and the LED table forms an array structure; S2: isolating sub-pixels, respectively setting blue pixel units on the array structure, and continuing to etch the base using the ICP etching process to separate the blue pixel units into a blue light-emitting area, a red light-emitting area, and a green light-emitting area; S3: preparing a row control line electrode, setting a transparent motor and an ohmic contact layer on the LED table to form a P-side electrode, and connecting the P-side electrodes of each sub-pixel to form a row control line electrode; S4: preparing a light isolation column, forming a first part of an organic insulating column by coating and photolithography; forming a second part of an inorganic optical film by thin film deposition and etching; sleeve-mounting the second part on the first part; and arranging the light isolation column between the pixel unit gaps; S5: preparing a column control line electrode, preparing an N-side electrode in a pixel unit gap, and connecting the N-side electrode of each sub-pixel to form a column control line electrode; S6: spraying sub-pixels, thinning and polishing the back of the substrate, aligning each column of sub-pixels with a spraying process, aligning each column of red light-emitting areas and green light-emitting areas with a spraying process, and coating red phosphors and green phosphors in sequence; S7: Adding a driving circuit to the P-side electrode and the N-side electrode led out from the front side of the substrate to complete the preparation of the wafer-level display array.

2. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S1, the selection of substrate materials, the structural setting of LED materials, and the formation of LED table array structures are performed according to the following steps: S101: Substrate material selection: GaN-on-Si epitaxial wafer is used as substrate material; this material has excellent thermal conductivity and stability, and is compatible with silicon-based integration processes. The lattice mismatch and thermal expansion coefficient mismatch can be calculated, as shown in formula (1)-formula (2); Dα=α GaN -a Si expression(2) Among them, ∈ is the lattice mismatch, a GaN and a Si Represent the lattice constants of GaN and Si respectively; Δα is the mismatch of thermal expansion coefficient, α GaN and α Si Represent the thermal expansion coefficient mismatch of GaN and Si respectively; this formula is used to calculate the lattice mismatch and thermal expansion coefficient difference between gallium nitride (GaN) and silicon-based materials (Si). Lattice mismatch will cause stress and defects in the material during epitaxial growth, which will reduce the luminous efficiency and affect the stability of the display; through this formula, the mismatch between GaN and Si can be evaluated, and then the material performance can be optimized, defects can be reduced, and luminous efficiency can be improved by adjusting process parameters (such as deposition temperature and growth rate); S102: LED material structure setting, depositing multiple LED material layers on the silicon-based gallium nitride epitaxial wafer through epitaxial growth, including an n-GaN layer, an active region layer and a p-GaN layer, and finally forming an LED epitaxial wafer. The epitaxial growth model is specifically as shown in formula (3); Where R is the material deposition rate, D s is the surface diffusion coefficient, D b is the volume diffusion coefficient; this formula is used to calculate the surface diffusion coefficient D during material deposition s and the bulk diffusion coefficient D b The relationship between can be used to control the material deposition rate; through this formula, the conditions for epitaxial growth can be optimized to ensure uniform deposition of LED material structures; S103: forming an LED table array structure, using an ICP (plasma dry etching) process to etch away part of the epitaxial layer to form an LED table, wherein the LED table forms an array structure, and each table serves as a pixel unit. The ICP etching model and the array arrangement are specifically as shown in formula (4)-formula (5); Where E is the electric field strength, V bias is the bias voltage, d is the thickness of the etching gap; D is the array spacing, and N is the number of pixels per unit area; this formula is used to calculate the electric field strength during the etching process. By adjusting the electric field strength, the etching rate and accuracy can be controlled to ensure that the etching depth of each sub-pixel is consistent, thereby improving the resolution and pixel uniformity of the display array.

3. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S2, the base is further etched, the photolithography mask controls the area, and the stress and lattice mismatch are processed according to the following steps: S201: The base is further etched, and the ICP etching process is continued on each LED table to further divide the base to form red, green and blue light-emitting areas, as shown in formula (6); Where E is the etching rate, Δh is the etching depth, and Δt is the time. This formula is used to calculate the rate during the etching process, where Δh is the etching depth and Δt is the etching time. Through this formula, the etching process can be accurately controlled to ensure that the shape and size of each sub-pixel are consistent, which can effectively reduce the light crosstalk and color distortion caused by uneven etching. S202: photolithography mask control area, using photolithography mask technology to accurately control the area of ​​each sub-pixel to ensure that the RGB three colors are evenly distributed in the array, as shown in formula (7); E exposure =I×t Formula (7) Among them, E exposure is the exposure energy, I is the light intensity, and t is the exposure time; S203: Processing stress and lattice mismatch, targeting the lattice mismatch problem between gallium nitride materials and silicon-based materials, using optimized etching process and annealing treatment to reduce defect density and improve the luminous efficiency of each sub-pixel, as shown in formula (8) to formula (9); Among them, σ is stress, E is elastic modulus, ΔT is temperature change, ν is Poisson's ratio; ∈ is lattice mismatch ratio, a substrate is the lattice constant of the base material, a film is the lattice constant of the epitaxial layer material.

4. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S3, the P-side electrode is set and the ohmic contact optimization is specifically performed according to the following steps: S301: P-side electrode setting: on the top of each LED table (i.e., on the p-GaN layer), a transparent electrode and an ohmic contact layer are deposited to form a P-side electrode, and the P-side electrodes of all sub-pixels are connected together by photolithography and etching processes to form a row control line electrode. The light transmittance of the transparent electrode and the contact resistance of the ohmic contact layer are calculated and the ohmic contact optimization is performed as shown in formulas (10)-(12); Where T is the transmittance, I transmitted is the transmitted light intensity, I incident is the incident light intensity; R c is the ohmic contact resistance, ρ is the contact resistivity, A is the contact area; I is the current passing through the electrode, V is the voltage, and R is the total resistance of the electrode; Formula (11) is used to calculate the ohmic contact resistance. This formula can be used to optimize the selection of transparent conductive materials and the design of contact area to reduce the contact resistance of the electrode and improve the conductivity of the electrode; S302: Ohmic contact optimization: To improve the conductivity of the electrode and reduce the contact resistance, select suitable transparent conductive oxide materials and optimize the deposition conditions. ITO is selected as the material, which is a common choice for transparent conductive materials with low resistivity and high light transmittance. AZO and FTO are also alternative materials with good conductivity and transparency, suitable for different application requirements. Deposition condition optimization is to optimize the electrical and optical properties of the TCO film by adjusting the working gas pressure, sputtering power, substrate temperature and post-processing conditions to achieve low contact resistance and high conductivity.

5. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S4, the formation of the organic insulating column, the formation of the inorganic optical film, and the arrangement of the optical isolation column are specifically performed according to the following steps: S401: Forming an organic insulating column, forming a first portion of an organic insulating column between sub-pixels by coating and photolithography; the insulating column material is polyimide, which has good insulation and thermal stability, and the coating thickness of the organic insulating material is calculated as shown in Formula (13); Where d is the coating thickness, V is the volume of the coating material, and A is the area of ​​the coating region; S402: forming an inorganic optical film, using a thin film deposition and etching method to form a second portion of an inorganic optical film, such as a silicon nitride or silicon oxide film, on the outer surface of the organic insulating column. These materials can provide excellent light isolation effects; S403: Setting optical isolation columns, setting the optical isolation columns between each pixel unit to avoid optical crosstalk between adjacent pixels, thereby improving display quality, and controlling the film thickness by a film deposition rate formula, as shown in formulas (14)-(15); Where, T(λ) is the transmittance of the optical isolation column for a specific wavelength, λ is the wavelength of light, n is the refractive index of the optical film, d is the thickness of the optical isolation column, and θ is the incident angle; R dep is the deposition rate, d film is the film thickness, t dep is the deposition time; Formula (14) is used to calculate the transmittance of the optical isolation column to light of different wavelengths. Based on this formula, the optimal optical isolation column structure can be designed for different display environments (such as outdoor or high-brightness scenes) to ensure the consistency of color reproduction and brightness, thereby significantly improving the performance of the display, especially under complex lighting conditions; Formula (15) is used to calculate the rate of thin film deposition on the optical isolation column. By adjusting the deposition rate, the thickness and reflective performance of the optical isolation column are optimized, and the color purity and luminous efficiency of the display array are improved.

6. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S5, the setting of the N-side electrode and the optimization of the electrode interface are specifically performed according to the following steps: S501: Setting the N-side electrode, depositing the N-side electrode material in the gap between each sub-pixel by sputtering or evaporation technology, and then connecting these electrodes by photolithography and etching technology to form a column control line electrode as shown in formula (15)-formula (16); Where J is the current density, I is the current passing through the N-side electrode, A is the cross-sectional area of ​​the N-side electrode, η is the injection efficiency, and V is the voltage; S502: Electrode interface optimization, optimizing the contact interface between the N-side electrode material and the gallium nitride layer, reducing the contact resistance and improving the current injection efficiency, using the minimized column control line electrode resistance as shown in formula (17); Where R is the resistance, ρ is the resistivity, L is the length of the electrode, and A is the cross-sectional area of ​​the electrode.

7. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S6, the back side of the substrate is thinned and polished, and the phosphor spraying is specifically performed according to the following steps: S601: thinning and polishing the back side of the substrate, thinning and polishing the back side of the substrate to improve the light transmittance and reduce the overall thickness of the device, and the back side thinning is calculated as shown in formula (18); Where R is the thinning rate, H is the thickness after thinning, and t is the thinning time; S602: Phosphor spraying: using precision spraying equipment to align each sub-pixel area, spraying red and green phosphors respectively. The red and green phosphors emit light under the light excitation of the blue LED, thereby achieving full-color display. The spraying is controlled by controlling the spraying density and the coverage and thickness of the spraying are calculated for feedback, as shown in formula (19)-formula (20). Where D is the coverage density of the spray, v is the spraying speed, t is the spraying time, and d is the distance between the nozzle and the substrate; A covered is the area covered by the phosphor, A total is the total area.

8. The method for preparing a full-color display array structure with light isolation according to claim 1, characterized in that: In step S7, the design of the driving circuit and the optimization of the circuit integration are specifically performed according to the following steps: S701: Design of the driving circuit, connecting the P-side electrode and the N-side electrode led out on the front side of the substrate, adding the driving circuit including the row driver, the column driver and the pixel driving circuit, completing the overall structural design of the wafer-level display array, by designing the voltage distribution and output control in the driving circuit and the total power consumption of the circuit, as shown in Formula (21)-Formula (22); P=V×I Formula (21) Where P is power consumption, V is voltage, and I is current; V out is the output voltage of the drive circuit, V in is the input voltage, R1 and R2 are voltage divider resistors; Formula (21) is used to calculate the power consumption of the driving circuit. This formula can be used to optimize the design of the driving circuit, ensuring that the display works efficiently while reducing power consumption and extending the service life of the display array; S702: Circuit integration optimization. In the integrated circuit design, it is necessary to consider aspects such as electromagnetic compatibility, power management, and heat dissipation design. The stable operation of the display array is ensured by calculating the electromagnetic compatibility and the output current of the driving circuit, as shown in formula (23)-formula (24). Among them, I out is the output current of the driving circuit, V out is the output voltage of the driving circuit, R load is the load resistance; EMI is electromagnetic interference, V noise is the noise voltage and f is the frequency.

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