SOT-MRAM device preparation method and SOT-MRAM device

Abstract

The invention discloses an SOT-MRAM device preparation method and an SOT-MRAM device, and belongs to the technical field of magnetic memories. The method comprises the following steps: sequentially depositing an intercalation layer and a hard mask layer on the surface of an MTJ film along the thickness direction; depositing a dielectric layer and exposing the hard mask layer; then the hard mask layer is subjected to a chemical reaction, and under the chemical reaction, the selection between the hard mask layer and other layers is relatively large, so that the hard mask layer can be accurately removed, and compared with a traditional CMP (Chemical Mechanical Polishing) mode, the process window has more obvious advantages; meanwhile, in the process of removing the hard mask layer, oxidation of the MTJ thin film can be prevented due to the existence of the intercalation layer, and the intercalation layer can be made of a specific material, so that the SOT efficiency can be further enhanced. The technological process is easy to implement, and compared with a top pinning SOT-MRAM device, the bottom pinning SOT-MRAM device has the advantage that the electrical and magnetic properties of the bottom pinning SOT-MRAM device are more excellent.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic memory, and in particular to a SOT-MRAM device preparation method and a SOT-MRAM device. Background Art

[0002] Compared with STT (Spin Transfer Torque)-MRAM, SOT (Spin Orbit Torque)-MRAM (Magnetic Random Access Memory) has the advantages of fast writing speed, unlimited erasing and read-write separation. SOT-MTJ (Magnetic Tunnel Junction) is its core structure. Its obvious structural feature is the SOT track layer with a thickness of only a few nanometers. The SOT track layer provides an independent channel for write current and read-write separation.

[0003] In the current manufacturing of SOT-MRAM, MTJ usually adopts a top pinning (TP) structure, in which the free layer of MTJ is located at the bottom and the SOT track layer is located below the free layer. MTJ etching stops on the SOT track layer, which is difficult to control accurately, resulting in a small MTJ etching window, which increases the difficulty of SOT-MRAM manufacturing process. At the same time, the electrical, magnetic and annealing stability of the magnetic tunnel junction based on top pinning are not as good as those of the MTJ based on bottom pinning (BP). Therefore, it is very important to realize the process integration and preparation of SOT-MRAM based on the structure of the MTJ based on bottom pinning.

[0004] However, in the current manufacturing of bottom-pinned SOT-MRAM devices, CMP (Chemical Mechanical Polishing) is usually used to polish the surface dielectric layer to expose the MTJ, and then the SOT track layer is deposited. The problem is that the free layer is only a few nanometers and the load effect of the CMP process makes it difficult to stop accurately on the free layer, resulting in a small process window. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing a SOT-MRAM device and a SOT-MRAM device, thereby improving the SOT-MRAM device preparation process window.

[0006] To achieve the above object, the present invention provides a method for preparing a SOT-MRAM device, comprising:

[0007] A columnar structure is formed on the surface of the substrate; the columnar structure comprises an MTJ film, an intercalation layer and a hard mask layer arranged in sequence in a direction away from the substrate; the MTJ film at least comprises a reference layer, a barrier layer and a free layer arranged in sequence in a direction away from the substrate;

[0008] Depositing at least one dielectric layer on the surface of the substrate having the columnar structure, and exposing the surface of the hard mask layer;

[0009] After the surface of the hard mask layer is exposed, the hard mask layer is removed by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate;

[0010] The track layer is deposited in the area where the track layer is to be deposited, so as to prepare the SOT-MRAM device.

[0011] Optionally, depositing at least one dielectric layer on the surface of the substrate having the columnar structure includes:

[0012] Depositing a first dielectric layer on the surface of the substrate having the columnar structure;

[0013] Accordingly, the process of removing the hard mask layer by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate includes:

[0014] The hard mask layer is removed by causing a chemical reaction to occur, exposing the surface of the intercalation layer to form a groove, so as to form the track layer region to be deposited on the surface of the substrate; the intercalation layer is the bottom surface of the groove.

[0015] Optionally, depositing at least one dielectric layer on the surface of the substrate having the columnar structure includes:

[0016] Depositing a first dielectric layer and a second dielectric layer in sequence along a thickness direction on the surface of the substrate having the columnar structure;

[0017] Accordingly, the process of removing the hard mask layer by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate includes:

[0018] The hard mask layer is removed by chemically reacting the hard mask layer, and the second dielectric layer is removed by chemically reacting the second dielectric layer, exposing the surface of the intercalation layer to form a groove; the intercalation layer serves as the bottom surface of the groove;

[0019] The sidewall of the groove is removed to form the track layer region to be deposited on the surface of the substrate.

[0020] Optionally, removing the sidewall of the groove includes:

[0021] The sidewall of the groove is removed by grazing incidence etching.

[0022] Optionally, the deposition height of the first dielectric layer is flush with the height of the intercalation layer, or exceeds the height of the intercalation layer.

[0023] Optionally, the material of the second dielectric layer is amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass;

[0024] Accordingly, removing the second dielectric layer by causing a chemical reaction in the hard mask layer includes:

[0025] A reaction gas or liquid is introduced to chemically react with the second dielectric layer, thereby removing the second dielectric layer.

[0026] Optionally, the material of the hard mask layer is amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass;

[0027] Accordingly, removing the hard mask layer by causing a chemical reaction in the hard mask layer includes:

[0028] A reaction gas or liquid is introduced to chemically react with the second dielectric layer, thereby removing the second dielectric layer.

[0029] Optionally, after depositing the track layer in the area where the track layer is to be deposited, the method further includes:

[0030] Depositing a third dielectric layer on the surface of the track layer, wherein the track layer and the third dielectric layer constitute a second stacked structure;

[0031] performing a patterning process on the second stacked structure;

[0032] After the patterning process, a fourth dielectric layer is deposited on the surface of the substrate;

[0033] A top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process; the top interconnect structure penetrates through the third dielectric layer and is connected to the track layer.

[0034] Optionally, exposing the surface of the hard mask layer includes:

[0035] The chemical mechanical polishing method is adopted to polish until the surface of the hard mask layer is exposed.

[0036] Optionally, the material of the track layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe or a topological insulator;

[0037] The material of the intercalation layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, topological insulator or NiO.

[0038] Optionally, the track layer is rectangular or L-shaped.

[0039] Optionally, the surface of the MTJ film is circular, elliptical or rectangular, forming a perpendicularly magnetized MTJ;

[0040] Alternatively, the surface of the MTJ film is elliptical or rectangular, forming an MTJ with in-plane magnetization.

[0041] Optionally, the material of the first dielectric layer is SiN or SiO2.

[0042] To achieve the above object, the present invention further provides a SOT-MRAM device, comprising: a SOT-MRAM device prepared by the above-mentioned SOT-MRAM device preparation method.

[0043] Obviously, the present invention provides a method for preparing a SOT-MRAM device, first depositing an intercalation layer and a hard mask layer in sequence on the surface of the MTJ film along the thickness direction; then depositing a dielectric layer and exposing the hard mask layer; then causing the hard mask layer to undergo a chemical reaction, under which the hard mask layer and other layers have a relatively large selection ratio, so the hard mask layer can be accurately removed, so the process window advantage is more obvious compared to the traditional CMP method; at the same time, in the process of removing the hard mask layer, the presence of the intercalation layer can prevent the MTJ film from oxidizing, and the intercalation layer can be made of a specific material, thereby further enhancing the SOT efficiency. This process flow is simple to implement, and the electrical and magnetic properties of the bottom pinned SOT-MRAM device are superior to those of the top pinned SOT-MRAM device. The present invention also provides a SOT-MRAM device, which is prepared by the above-mentioned SOT-MRAM device preparation method, so it also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0045] Figure 1 A flow chart of a method for preparing a SOT-MRAM device provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of the shape of a first track layer provided in an embodiment of the present invention;

[0047] Figure 3 A schematic diagram of the shape of a second track layer provided in an embodiment of the present invention;

[0048] Figures 4 to 10 A schematic flow chart of a first method for preparing a SOT-MRAM device provided in an embodiment of the present invention;

[0049] Figures 11 to 20 A schematic flow chart of a second method for preparing a SOT-MRAM device provided in an embodiment of the present invention.

[0050] The following are the descriptions of the reference numerals:

[0051] 101-first bottom dielectric layer; 102-bottom electrode; 103-second bottom dielectric layer; 104-bottom via; 105-bottom conductive layer; 106-MTJ film; 107-intercalation layer; 108-hard mask layer; 103a-first layer first dielectric layer; 101a-second layer first dielectric layer; 109-track layer; 103b-third dielectric layer; 110-top via; 111-top conductive layer; 112-second dielectric layer. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Please refer to Figure 1 , Figure 1 A flow chart of a method for preparing a SOT-MRAM device provided in an embodiment of the present invention, the method may include:

[0054] S101: forming a columnar structure on the surface of a substrate; the columnar structure comprises an MTJ film, an intercalation layer and a hard mask layer sequentially arranged in a direction away from the substrate; the MTJ film at least comprises a reference layer, a barrier layer and a free layer sequentially arranged in a direction away from the substrate.

[0055] The process of forming the columnar structure in this embodiment may specifically include:

[0056] Depositing an MTJ thin film, an intercalation layer, and a hard mask layer in sequence along a thickness direction on a surface of the substrate to form a first stacked structure;

[0057] The first stacked structure is patterned to form a columnar structure; the columnar structure is connected to the bottom electrode.

[0058] It should be noted that in this embodiment, the substrate includes a bottom electrode, the bottom electrode is formed in the first bottom dielectric layer, the first bottom dielectric layer plays an insulating role, and the first bottom dielectric layer and the bottom electrode constitute the substrate. This embodiment does not limit the specific type of the first bottom dielectric layer, for example, the material of the first bottom dielectric layer can be SiO or SiN, or other insulating materials.

[0059] In this embodiment, the columnar structure needs to be electrically connected to the bottom electrode, that is, the MTJ film needs to be connected to the bottom electrode. This embodiment does not limit the specific method of connecting the MTJ film and the bottom electrode, as long as the MTJ film and the bottom electrode can be electrically connected. For example, the substrate may also include a bottom interconnect structure; the bottom interconnect structure is formed in the first bottom dielectric layer; one end of the bottom interconnect structure is connected to the bottom electrode, and the other end is connected to the MTJ film. Correspondingly, after the graphical processing, one end of the bottom interconnect structure is connected to the bottom electrode, and the other end is connected to the columnar structure.

[0060] This embodiment does not limit the specific type of the bottom interconnect structure, for example, the material of the bottom interconnect structure may be metal, or other conductive materials. This embodiment does not limit the specific structure of the bottom interconnect structure, for example, the bottom interconnect structure may include a bottom via; or the bottom interconnect structure may include a bottom via and a bottom conductive layer connected in sequence along the thickness direction.

[0061] Furthermore, the substrate in this embodiment may further include a second bottom dielectric layer, which is located inside the first bottom dielectric layer, covers the surface of the bottom electrode, and surrounds the bottom interconnect structure to play an insulating role. This embodiment does not limit the specific type of the second bottom dielectric layer, for example, the material of the second bottom dielectric layer may be SiO or SiN, or other insulating materials.

[0062] This embodiment does not limit the specific method of depositing the MTJ film, intercalation layer and hard mask layer. For example, physical vapor deposition or chemical vapor deposition can be used to sequentially deposit the MTJ film, intercalation layer and hard mask layer on the surface of the substrate along the thickness direction to form a first stacked structure.

[0063] The MTJ film in this embodiment is not limited to including a reference layer, a barrier layer and a free layer, and other film layers may be added according to actual needs. The magnetization direction of the free layer may be changed by a current or a magnetic field.

[0064] This embodiment does not limit the specific type of intercalation layer. For example, the intercalation layer can be made of the same material as the track layer, such as W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, or a topological insulator. When such a material is used, the MTJ film can be electrically connected to the track layer through the intercalation layer; or the intercalation layer can be made of a material different from the track layer, such as NiO or other materials that can improve the spin transfer efficiency, so as to improve the spin transfer efficiency through the intercalation layer. It should be noted that when the intercalation layer is made of NiO, since only a thin layer of NiO is required to improve the spin transfer efficiency, the electrical connection between the MTJ film and the track layer will not be affected.

[0065] This embodiment does not limit the specific type of the hard mask layer. For example, the material of the hard mask layer may be amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass, or other materials that can be removed by chemical etching.

[0066] In this embodiment, the first stacked structure retained after the patterning process should cover the bottom electrode to ensure that the columnar structure can be connected to the bottom electrode.

[0067] This embodiment does not limit the specific method of performing the graphical processing, as long as the desired pattern can be obtained. For example, the hard mask layer can be etched to define the pattern of the hard mask layer; after the etching is completed, the intercalation layer and the MTJ film are etched to define the pattern of the intercalation layer and the MTJ film.

[0068] This embodiment does not limit the specific pattern of the MTJ film after the patterning process. The patterns of the MTJ film are different, and the types of MTJs formed accordingly are also different. For example, the surface of the MTJ film can be circular, elliptical or rectangular, forming a perpendicularly magnetized MTJ; or, the surface of the MTJ film can be elliptical or rectangular, forming an in-plane magnetized MTJ. In the perpendicularly magnetized MTJ, the magnetic moments of the reference layer and the free layer are arranged in a direction perpendicular to the film surface; in the in-plane magnetized MTJ, the magnetic moments of the reference layer and the free layer are arranged in a direction within the film plane. In addition, in this embodiment, the sidewalls of the MTJ film after the patterning process can be perpendicular to the substrate, or the surface of the substrate can be at a preset angle.

[0069] S102: depositing at least one dielectric layer on the surface of the substrate having the columnar structure, and exposing the surface of the hard mask layer.

[0070] This embodiment does not limit the specific method of exposing the surface of the hard mask layer, as long as the dielectric layer covering the surface of the hard mask layer can be removed, for example, chemical mechanical polishing can be used to polish until the surface of the hard mask layer is exposed.

[0071] This embodiment does not limit the specific number and type of deposited dielectric layers. Please refer to the following specific embodiments for details.

[0072] S103: After the surface of the hard mask layer is exposed, the hard mask layer is removed by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate.

[0073] This embodiment does not limit the specific method of removing the hard mask layer, as long as the hard mask layer can be chemically etched away, for example, a reaction gas or liquid may be introduced to chemically react with the hard mask layer to remove the hard mask layer. Further, according to the specific type of the hard mask layer, a corresponding reaction gas or liquid may be selected, for example, when the material of the hard mask layer is amorphous carbon, the reaction gas may be oxygen; when the material of the hard mask layer is germanium, the reaction gas may be H2O2.

[0074] This embodiment does not limit the specific method of forming the area of ​​the track layer to be deposited. Please refer to the following specific embodiments for details.

[0075] S104: depositing a track layer in the area where the track layer is to be deposited, to prepare a SOT-MRAM device.

[0076] This embodiment does not limit the specific type of the track layer. For example, the material of the track layer may be W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe or a topological insulator.

[0077] Furthermore, after depositing the track layer in the area to be deposited, the present embodiment may further include:

[0078] Depositing a third dielectric layer on the surface of the track layer, the track layer and the third dielectric layer forming a second stacked structure;

[0079] performing a patterning process on the second stacked structure;

[0080] After the patterning process, a fourth dielectric layer is deposited on the surface of the substrate;

[0081] A top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process; the top interconnect structure penetrates the third dielectric layer and is connected to the track layer.

[0082] This embodiment does not limit the specific pattern of the track layer after the patterning process, for example Figure 2 and Figure 3As shown, the shape of the track layer can be rectangular or L-shaped. It should be noted that in this embodiment, since the track layer and the MTJ pattern are defined separately, field-free flipping can be achieved. The top interconnect structure formed in this embodiment can be used for interconnection with other devices. When vias are used in the top interconnect structure, due to the height difference between the MRAM area and the logic area, the drilling depths of the two areas are different, and the third dielectric layer deposited on the surface of the track layer in this embodiment can play a role in compensating for the height difference between the MRAM area and the logic area.

[0083] This embodiment does not limit the specific type of the top interconnect structure, for example, the material of the top interconnect structure can be metal, or other conductive materials. This embodiment does not limit the specific structure of the top interconnect structure, for example, the top interconnect structure can include a top via; or the top interconnect structure can include a top via and a top conductive layer connected in sequence along the thickness direction.

[0084] Based on the above embodiments, the present invention first deposits an intercalation layer and a hard mask layer in sequence along the thickness direction on the surface of the MTJ film; then deposits a dielectric layer and exposes the hard mask layer; then causes the hard mask layer to undergo a chemical reaction, under which the hard mask layer has a relatively large selection ratio with other layers, so the hard mask layer can be accurately removed, so the process window advantage is more obvious compared to the traditional CMP method; at the same time, in the process of removing the hard mask layer, the presence of the intercalation layer can prevent the MTJ film from being oxidized, and the intercalation layer can be made of specific materials, thereby further enhancing the SOT efficiency. This process flow is simple to implement, and compared to the top-pinned SOT-MRAM device, the electrical and magnetic properties of the bottom-pinned SOT-MRAM device are more superior.

[0085] Please refer to Figures 4 to 10 , Figures 4 to 10 A schematic flow chart of a first method for preparing a SOT-MRAM device provided in an embodiment of the present invention. Different from the first embodiment of the method for preparing a SOT-MRAM device, this embodiment further specifically defines step S102 and step S103 on the basis of the first embodiment of the method for preparing a SOT-MRAM device, and the rest of the contents have been described in detail in the embodiment of the first method for preparing a SOT-MRAM device, and will not be repeated here.

[0086] In this embodiment, the method for preparing a SOT-MRAM device may include:

[0087] like Figure 4 As shown, an MTJ film 106, an intercalation layer 107 and a hard mask layer 108 are sequentially deposited on the surface of the substrate along the thickness direction to form a first stacked structure; the substrate includes a bottom electrode 102; the MTJ film 106 includes at least a reference layer, a barrier layer and a free layer sequentially arranged along a direction away from the substrate.

[0088] The substrate in this embodiment may be composed of a first bottom dielectric layer 101, a second bottom dielectric layer 103, a bottom interconnect structure and a bottom electrode 102; the bottom interconnect structure may include a bottom via 104 and a bottom conductive layer 105 sequentially connected along the thickness direction.

[0089] like Figure 5 As shown, the first stacked structure is patterned to form a columnar structure; the columnar structure is connected to the bottom electrode 102 .

[0090] like Figure 6 As shown, a first dielectric layer is deposited on the surface of the substrate having the columnar structure, and the surface of the hard mask layer 108 is exposed.

[0091] The first dielectric layer in this embodiment serves as a protective layer and will not be etched away during the process of chemically etching the hard mask layer 108. This embodiment does not limit the specific type of the first dielectric layer. For example, the material of the first dielectric layer may be SiN or SiO2. This embodiment does not limit the specific number of first dielectric layers. For example, a first dielectric layer may be deposited on the surface of the substrate along the thickness direction; or a first dielectric layer 103a and a second dielectric layer 101a may be deposited in sequence on the surface of the substrate along the thickness direction, and the materials of the two first dielectric layers may be different.

[0092] like Figure 7 As shown, after the surface of the hard mask layer 108 is exposed, the hard mask layer 108 is removed by causing a chemical reaction to expose the surface of the intercalation layer 107 to form a groove, so as to form a region on the surface of the substrate where the track layer 109 is to be deposited; the intercalation layer 107 is the bottom surface of the groove.

[0093] like Figure 8 As shown, the track layer 109 is deposited in the area where the track layer 109 is to be deposited, so as to prepare a SOT-MRAM device; the track layer 109 is connected to the insertion layer 107 .

[0094] Furthermore, after depositing the track layer 109 in the area where the track layer 109 is to be deposited, the present embodiment may further include:

[0095] like Figure 8 and Fig. 9 As shown, a third dielectric layer 103b is deposited on the surface of the track layer 109, and the track layer 109 and the third dielectric layer 103b constitute a second stacked structure; the second stacked structure is patterned; after the patterning, a fourth dielectric layer is deposited on the surface of the substrate.

[0096] like Fig.10As shown, a top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process to obtain a SOT-MRAM device; the top interconnect structure penetrates through the third dielectric layer 103 b and is connected to the track layer 109 .

[0097] In this embodiment, the top interconnect structure may include a top via 110 and a top conductive layer 111 that are sequentially connected along the thickness direction.

[0098] Please refer to Figures 11 to 20 , Figures 11 to 20 A flow chart of a second method for preparing a SOT-MRAM device provided in an embodiment of the present invention. Different from the first embodiment of the method for preparing a SOT-MRAM device, this embodiment further specifically defines step S102 and step S103 on the basis of the first embodiment of the method for preparing a SOT-MRAM device, and the rest of the contents have been described in detail in the first embodiment of the method for preparing a SOT-MRAM device, and will not be repeated here.

[0099] In this embodiment, the method for preparing a SOT-MRAM device may include:

[0100] like Fig.11 As shown, an MTJ film 106, an intercalation layer 107 and a hard mask layer 108 are sequentially deposited on the surface of the substrate along the thickness direction to form a first stacked structure; the substrate includes a bottom electrode 102; the MTJ film 106 includes at least a reference layer, a barrier layer and a free layer sequentially arranged along a direction away from the substrate.

[0101] The substrate in this embodiment may be composed of a first bottom dielectric layer 101, a second bottom dielectric layer 103, a bottom interconnect structure and a bottom electrode 102; the bottom interconnect structure may include a bottom via 104 and a bottom conductive layer 105 sequentially connected along the thickness direction.

[0102] like Fig.12 As shown, the first stacked structure is patterned to form a columnar structure; the columnar structure is connected to the bottom electrode 102 .

[0103] like Figures 13 to 15 As shown, a first dielectric layer and a second dielectric layer 112 are sequentially deposited along a thickness direction on a surface of a substrate having a columnar structure, and a surface of the hard mask layer 108 is exposed.

[0104] The first dielectric layer in this embodiment serves as a protective layer and will not be etched away during the process of chemically etching the hard mask layer 108. This embodiment does not limit the specific type of the first dielectric layer. For example, the material of the first dielectric layer may be SiN or SiO2. This embodiment does not limit the specific number of first dielectric layers. For example, a first dielectric layer may be deposited on the surface of the substrate along the thickness direction; or a first dielectric layer 103a and a second dielectric layer 101a may be deposited in sequence on the surface of the substrate along the thickness direction, and the materials of the two first dielectric layers may be different.

[0105] Furthermore, in this embodiment, the deposition height of the first dielectric layer can be flush with the height of the intercalation layer 107 or exceed the height of the intercalation layer 107 to avoid damaging the intercalation layer 107 during the process of removing the sidewall of the groove by grazing incidence etching.

[0106] This embodiment does not limit the specific type of the second dielectric layer 112 . For example, the material of the second dielectric layer 112 may be amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass, or other materials that can be removed by chemical etching.

[0107] like Fig.16 As shown, the hard mask layer 108 is removed by chemically reacting the hard mask layer 108, and the second dielectric layer 112 is removed by chemically reacting the second dielectric layer 112, exposing the surface of the intercalation layer 107 to form a groove; the intercalation layer 107 serves as the bottom surface of the groove.

[0108] The present embodiment does not limit the specific method of removing the second dielectric layer 112, as long as the second dielectric layer 112 can be chemically etched away, for example, a reaction gas or liquid may be introduced to chemically react with the second dielectric layer 112 to remove the second dielectric layer 112. Further, a corresponding reaction gas or liquid may be selected according to the specific type of the second dielectric layer 112, for example, when the material of the second dielectric layer 112 is amorphous carbon, the reaction gas may be oxygen; when the material of the second dielectric layer 112 is germanium, the reaction gas may be H2O2.

[0109] It should be noted that, when the second dielectric layer 112 and the hard mask layer 108 in this embodiment are made of the same material, the same reaction gas or liquid can be introduced to chemically react with the second dielectric layer 112 and the hard mask layer 108 at the same time, and the second dielectric layer 112 and the hard mask layer 108 are removed at the same time; when the second dielectric layer 112 and the hard mask layer 108 in this embodiment are made of different materials, different reaction gases or liquids can be introduced to remove the second dielectric layer 112 and the hard mask layer 108 step by step.

[0110] like Fig.17 As shown, the sidewall of the groove is removed to form a region on the surface of the substrate where a track layer 109 is to be deposited.

[0111] It should be noted that the sidewall of the groove in this embodiment refers to the residual first dielectric layer that is higher than the plane where the insertion layer 107 is located after being treated by chemical etching.

[0112] This embodiment does not limit the specific method of removing the sidewall of the groove, as long as the sidewall of the groove can be removed, for example, the sidewall of the groove can be removed by grazing incidence etching. It should be noted that grazing incidence etching etches the side faster and etches the bottom slower, thereby generating a certain selectivity, so that the intercalation layer 107 can be damaged as little as possible.

[0113] like Fig.18 As shown, the track layer 109 is deposited in the area where the track layer 109 is to be deposited, so as to prepare a SOT-MRAM device; the track layer 109 is connected to the insertion layer 107 .

[0114] Furthermore, after depositing the track layer 109 in the area where the track layer 109 is to be deposited, the present embodiment may further include:

[0115] like Fig.18 and Fig.19 As shown, a third dielectric layer 103b is deposited on the surface of the track layer 109, and the track layer 109 and the third dielectric layer 103b constitute a second stacked structure; the second stacked structure is patterned; after the patterning, a fourth dielectric layer is deposited on the surface of the substrate.

[0116] like Fig. 20 As shown, a top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process to obtain a SOT-MRAM device; the top interconnect structure penetrates through the third dielectric layer 103 b and is connected to the track layer 109 .

[0117] In this embodiment, the top interconnect structure may include a top via 110 and a top conductive layer 111 that are sequentially connected along the thickness direction.

[0118] An embodiment of the present invention further provides a SOT-MRAM device, which may include: a SOT-MRAM device prepared by the above-mentioned SOT-MRAM device preparation method.

[0119] Based on the above embodiments, the SOT-MRAM device of the present invention is prepared by the above SOT-MRAM device preparation method, so it also has the above beneficial effects.

[0120] The principles and implementation methods of the present invention are described herein using specific examples, and the various embodiments are in a progressive relationship. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. For those of ordinary skill in the art, without departing from the principle of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0121] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A method for preparing a SOT-MRAM device, characterized in that: include: Forming a columnar structure on the surface of the substrate; the columnar structure includes an MTJ film, an intercalation layer, and a hard mask layer sequentially arranged in a direction away from the substrate; The MTJ film at least includes a reference layer, a barrier layer and a free layer arranged in sequence in a direction away from the substrate; Depositing at least one dielectric layer on the surface of the substrate having the columnar structure, and exposing the surface of the hard mask layer; After the surface of the hard mask layer is exposed, the hard mask layer is removed by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate; The track layer is deposited in the area where the track layer is to be deposited, so as to prepare the SOT-MRAM device.

2. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The step of depositing at least one dielectric layer on the surface of the substrate having the columnar structure comprises: Depositing a first dielectric layer on the surface of the substrate having the columnar structure; Accordingly, the process of removing the hard mask layer by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate includes: The hard mask layer is removed by causing a chemical reaction to occur, exposing the surface of the intercalation layer to form a groove, so as to form the track layer region to be deposited on the surface of the substrate; the intercalation layer is the bottom surface of the groove.

3. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The step of depositing at least one dielectric layer on the surface of the substrate having the columnar structure comprises: Depositing a first dielectric layer and a second dielectric layer in sequence along a thickness direction on the surface of the substrate having the columnar structure; Accordingly, the process of removing the hard mask layer by causing a chemical reaction in the hard mask layer to form a track layer region to be deposited on the surface of the substrate includes: The hard mask layer is removed by chemically reacting the hard mask layer, and the second dielectric layer is removed by chemically reacting the second dielectric layer, exposing the surface of the intercalation layer to form a groove; the intercalation layer serves as the bottom surface of the groove; The sidewall of the groove is removed to form the track layer region to be deposited on the surface of the substrate.

4. The method for preparing a SOT-MRAM device according to claim 3, characterized in that: The step of removing the sidewall of the groove comprises: The sidewall of the groove is removed by grazing incidence etching.

5. The method for preparing a SOT-MRAM device according to claim 4, characterized in that: The deposition height of the first dielectric layer is flush with the height of the intercalation layer, or exceeds the height of the intercalation layer.

6. The method for preparing a SOT-MRAM device according to claim 3, characterized in that: The material of the second dielectric layer is amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass; Accordingly, removing the second dielectric layer by causing a chemical reaction in the hard mask layer includes: A reaction gas or liquid is introduced to chemically react with the second dielectric layer, thereby removing the second dielectric layer.

7. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The material of the hard mask layer is amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass; Accordingly, removing the hard mask layer by causing a chemical reaction in the hard mask layer includes: A reaction gas or liquid is introduced to chemically react with the hard mask layer to remove the hard mask layer.

8. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: After the track layer is deposited in the area where the track layer is to be deposited, the method further comprises: Depositing a third dielectric layer on the surface of the track layer, wherein the track layer and the third dielectric layer constitute a second stacked structure; performing a patterning process on the second stacked structure; After the patterning process, a fourth dielectric layer is deposited on the surface of the substrate; A top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process; the top interconnect structure penetrates through the third dielectric layer and is connected to the track layer.

9. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The exposing the surface of the hard mask layer comprises: The chemical mechanical polishing method is adopted to polish until the surface of the hard mask layer is exposed.

10. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The material of the track layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe or a topological insulator; The material of the intercalation layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, topological insulator or NiO.

11. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The shape of the track layer is rectangular or L-shaped.

12. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The surface of the MTJ film is circular, elliptical or rectangular, forming a perpendicularly magnetized MTJ; Alternatively, the surface of the MTJ film is elliptical or rectangular, forming an MTJ with in-plane magnetization.

13. The method for preparing a SOT-MRAM device according to claim 2 or 3, characterized in that: The material of the first dielectric layer is SiN or SiO2.

14. A SOT-MRAM device, characterized in that: include: A SOT-MRAM device prepared by the SOT-MRAM device preparation method according to any one of claims 1 to 13.

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