Test system and contact system for high voltage and high current testing of plurality of power semiconductor devices included in wafer

Abstract

A test system (100) for high voltage and high current testing, in particular for dynamic high voltage and high current testing, of power semiconductor devices included in a wafer is described, comprising a test machine, a needle-type probe card (500) and a contact system (200). The contact system (200) includes a wafer housing conductive portion (202) and a test circuit closed contact conductive portion (204). A test circuit closing contact conductive portion (204) of the contact system (200) has a shape and extension such that a respective straight and continuous current conduction path from each power semiconductor device to at least one test circuit closing terminal arranged along a predetermined immutable direction (504) is determined. Each current conduction path extends in a direction parallel or coincident with a predetermined immutable direction (504). A contact system (200) is also described.

Description

Technical Field

[0001] The present invention generally relates to the field of high voltage and high current testing of a plurality of power semiconductor devices included in a wafer; in particular, the present invention relates to a test system for high voltage and high current testing of a plurality of power semiconductor devices included in a wafer, in particular for testing dynamic parameters of such semiconductor devices. The present invention also relates to a contact system for use in such a test system. Background Art

[0002] In the field of semiconductor devices, it is practice to perform testing on electronic devices before they are appropriately packaged on a substrate or chip and sold for use in electrical / electronic applications.

[0003] It is currently known to perform tests on semiconductor devices for static parameters of the same device and to perform tests on semiconductor devices for dynamic parameters.

[0004] The above two tests are usually performed at different times during the manufacture of semiconductor devices.

[0005] Specifically, the tests for static parameters are performed under direct current.

[0006] In contrast, in tests for dynamic parameters, alternating electronic signals (eg, with state switching or polarity reversal) are applied to the semiconductor device.

[0007] In tests for evaluating and / or verifying the dynamic parameters of the presence switching, the problem of parasitic inductance arises. In fact, parasitic inductance during signal switching can lead to overvoltages that can damage both the tester and the semiconductor device under test.

[0008] As a result, tests used to evaluate dynamic parameters are very difficult to perform, especially those used to verify and / or evaluate the actual operation of the device under test, especially in the early stages of the manufacturing / production process.

[0009] Furthermore, the tests used to evaluate and / or verify dynamic parameters are even more complex when performed on power semiconductor devices. For power semiconductor devices, the tests are performed at high voltages and high currents; therefore, the powers involved are very high.

[0010] Therefore, even if very small parasitic inductances are present, overvoltages caused by these parasitic inductances during high voltage and high current testing can cause irreparable damage to the power semiconductor device under test.

[0011] Several functional tests of semiconductor electronic devices, in particular power devices, are known and abbreviated in the industry as RBSOA, FBSOA and SCSOA, wherein it is envisaged that such functional tests are performed using voltages in the order of kilovolts and currents of hundreds of amperes up to thousands of amperes kA.

[0012] There is an increasing need among power semiconductor device manufacturers to be able to detect possible failures in power semiconductor devices as early as possible during the manufacturing process of the power semiconductor devices. In particular, there is an increasing need to be able to perform tests on such power semiconductor devices while they are still in the early stages of the manufacturing process, ideally attempting to perform the tests directly on the semiconductor wafer on which a plurality of devices are manufactured, as is known to those skilled in the art.

[0013] In the prior art, there is no known test machine / system capable of performing high voltage and high current testing on power electronic devices while the devices are still combined with other electronic devices in a wafer, specifically for performing tests for evaluating and / or verifying the dynamic parameters of the power electronic devices before they are individually separated.

[0014] Contact systems for test machines equipped with a contact disk and a test circuit closing conductive plate are known in the art, in particular for static testing. In such known contact systems, the contact disk is electrically connected to the test circuit closing conductive plate only via a flexible wire that extends freely between the contact disk and the test circuit closing conductive plate.

[0015] However, the use of such wires for connecting the contact pads and conducting the test circuit closure makes the contact system unsuitable for high voltage and high current testing of a plurality of power semiconductor devices, in particular for testing dynamic parameters.

[0016] The use of such wires results in the generation of high parasitic inductances during the testing of dynamic parameters.

[0017] Currently, the most modern power semiconductor devices are designed to be faster in terms of switching time. Fast switching time advantageously reduces energy dissipation. Due to their fast switching time, these semiconductor devices should therefore be tested with faster switching.

[0018] Disadvantageously, since the known contact systems just described generate high parasitic inductances during dynamic parameter testing, they may not be suitable for this type of testing.

[0019] Indeed, if the parasitic inductance is high, it is not possible to power the power semiconductor device and it is also not possible to test the power semiconductor device at the desired switching speed. Summary of the invention

[0020] An object of the present invention is to provide a test system and a contact system for use in such a test system, which test system is capable of performing high voltage and high current testing, in particular dynamic high voltage and high current testing, on a plurality of power semiconductor devices included in a wafer.

[0021] Another object of the invention is to provide a test system and a contact system for use in such a test system which can perform dynamic high voltage and high current tests even at high desired switching speeds.

[0022] According to a first aspect of the invention, the above and other objects and advantages are achieved by a test system for high voltage and high current testing of a plurality of power semiconductor devices comprised in a wafer having the features defined in claim 1, and according to another aspect of the invention by a contacting system having the features defined in claim 15. Preferred embodiments of the invention are defined in the dependent claims, the content of which shall be understood as an integral part of the present description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The functions and structural features of some preferred embodiments of the system and contact system for high voltage and high current testing of a plurality of power semiconductor devices included in a wafer according to the present invention will now be described. With reference to the accompanying drawings, in which:

[0024] - Figure 1 An exemplary external structure of a test system for performing high voltage and high current testing on a plurality of power semiconductor devices included in a wafer is shown;

[0025] - Figure 2 An exemplary embodiment of a contact system for a test system according to the present invention is shown;

[0026] - Figure 3 is an exploded view of the contact system, wherein the test circuit closing contact conductive portion and the wafer housing conductive portion are two distinct components;

[0027] - Figure 4 An exemplary embodiment of a processing system according to the present invention is shown;

[0028] - Figure 5a An exemplary needle-type probe card is shown;

[0029] - Figure 5b An exemplary needle probe card is shown when connected to a test circuit closed terminal;

[0030] - Figure 5c Shows that when the contact system contacts the test circuit closed terminal, Figure 5b Needle probe card in

[0031] - Figure 6 are examples of possible movements of the contact system performed by the handling system according to the invention. DETAILED DESCRIPTION

[0032] Before explaining in detail multiple embodiments of the present invention, it should be clarified that the application of the present invention is not limited to the design details and the configuration of the components presented in the following description or shown in the accompanying drawings. The present invention may assume other embodiments and be implemented or constructed in different ways in practice. It should also be understood that the wording and terminology have descriptive purposes and should not be understood as limiting. The use of "comprises" and "includes" and their variations is intended to cover the elements listed below and their equivalents, as well as additional elements and their equivalents.

[0033] Embodiments of a test system for performing high voltage and high current testing, particularly high voltage and high current dynamic testing, on a plurality of power semiconductor devices included in a wafer are described below.

[0034] In one embodiment, the test system 100 includes a test machine arranged to perform predetermined high voltage and high current test functions on a plurality of power semiconductor devices.

[0035] For example, the predetermined test function may perform tests known by the abbreviations RBSOA, FBSOA, and SCSOA.

[0036] For example, the current supplied to the power semiconductor device under test may be determined by a predetermined high voltage, high current test function performed by a test machine.

[0037] The test system 100 also includes a needle probe card 500 arranged to be connected to such a test machine. The needle probe card 500 includes a plurality of needles 502 adapted to contact at least one power semiconductor device under test when a plurality of power semiconductor devices are included in the wafer W. Each needle is adapted to allow current to flow through the at least one power semiconductor device under test. Figure 5a An exemplary needle probe card 500 is shown in FIG.

[0038] For example, all power semiconductor devices of the wafer W disposed on the wafer housing conductive portion 202 may be contacted with the plurality of needles 502 at least one at a time for testing.

[0039] For example, during testing, multiple needles 502 (or at least a portion of the multiple needles) may contact only one power semiconductor device at a time, or multiple needles 502 (or at least a portion of the multiple needles) may contact a subset of power semiconductor devices in multiple integral power semiconductor devices at a time.

[0040] For example, in the field of testing for power semiconductor devices, the needle probe card 500 can contact multiple needles 502, wherein the current can flow on the emitter or anode of at least one power semiconductor device under test. The needle probe card 500 may include a large number of needles 502 so that very high currents can be applied to the power semiconductor device, while being able to utilize the maximum possible area of ​​the semiconductor device to reduce the current density per unit area of ​​the device and distribute the current to several needles. The needle probe card 500 may also include an inherent safety system that can monitor the current entering the probe card. If the total input current of the needle probe card 500 exceeds a predetermined DC value, the safety system may be able to interrupt the input current of the needle probe card 500. The needle probe 500 may also be coupled / associated with an appropriate safety system (such as the safety system described in international patent application WO2021240431), whose owner is the same as the owner of the present patent application.

[0041] The testing system further includes a contact system 200 . Figure 2 2. The contact system 200 is shown by way of example in FIG. Figure 2 The left side of FIG. 2 shows a perspective view of a contact system 200 , while the right side shows a top view of the same contact system 200 .

[0042] The contact system 200 includes a wafer housing conductive portion 202 and a test circuit closure contact conductive portion 204 .

[0043] The wafer housing conductive portion 202 is configured to accommodate a wafer W to be contacted by a plurality of needles 502 of a needle probe card 500 during testing.

[0044] For example, the wafer housing conductive portion 202 may extend along a predetermined support plane.

[0045] The test circuit closure contact conductive portion 204 is electrically connected to the wafer housing conductive portion 202 .

[0046] The test system 100 further includes at least one test circuit closing terminal T.

[0047] For example, Figure 5a As can be observed in FIG. 5 , the at least one test circuit closing terminal T is arranged along a predetermined invariable direction 504 and is at a predetermined invariable distance d1 from the plurality of needles 502 of the needle type probe card 500 .

[0048] Preferably, if Figure 5a It can also be observed that there can also be a plurality of test circuit closing terminals T, T', T" arranged along corresponding predetermined directions 504, 504', 504".

[0049] For example, the at least one test circuit closing terminal T may include one or more spring pins.

[0050] In use, at least one test circuit closing terminal T is arranged to be in contact with a test circuit closing contact conducting portion 204 of the contact system 200 .

[0051] At least one test circuit closing terminal T is coupled to the test machine via a conductive path 506 arranged along a predetermined invariable direction 504 .

[0052] For example, as explained in detail in the following description, at least one test circuit closing terminal T may be directly coupled to the test machine through the conductive path 506, or may be indirectly coupled to the test machine through a needle probe card. In the second case, at least one test circuit closing terminal T may be connected to a needle probe card through the conductive path 506, and the needle probe card may in turn be connected to the test machine.

[0053] At least a portion of the conductive path 506 facing the test circuit closing contact conductive portion 204 is straight and parallel to the test circuit closing contact conductive portion 204 of the contact system 200 .

[0054] For example, preferably, the portion of the conductive path 506 facing the test circuit closure contact portion 204 may be spaced apart from the conductive portion by a distance between a fraction of a millimeter and several millimeters.

[0055] The test circuit closing contact conducting portion 204 of the contact system 200 has a shape and an extension such that it determines a respective straight and continuous current conduction path from each power semiconductor device to the at least one test circuit closing terminal T.

[0056] Each current conducting path A extends along a direction parallel to or coincident with the predetermined invariable direction 504 .

[0057] In other words, each straight current conduction path A may extend in a direction parallel to or coincident with the predetermined invariable direction 504 , along which the test circuit closing terminal T coupled to the test machine via the conductive path 506 is arranged.

[0058] Advantageously, since 1) a portion of the conductive path 506 facing the test circuit closed contact portion 204 is straight and parallel to the test circuit closed contact conductive portion 204 of the contact system, and 2) the current conduction path A is straight and extends in a direction parallel to or coinciding with the predetermined invariable direction 506 in which the conductive path 506 in which the current flows is arranged, parasitic inductances are compensated and kept at a low level, so that dynamic testing can be performed even on power semiconductor devices.

[0059] As is known in the art, inductance increases as the area between conductors increases. Since the current conducting path A and the conductive path 506 are parallel to each other, the area between the conductors decreases, resulting in a decrease in parasitic inductance.

[0060] exist Figure 1 In the figure, a possible external structure of the test system 100 just described is shown by way of example. The structure may include an external housing that may contain elements of the test system. For example, block 101 ("test machine") may contain a test machine, and block 103 ("chuck handler") may include a contact system, a test circuit closing terminal, and a needle probe card. Between blocks 101 and 102, a block 102 ("probe card interface") may also be provided, which may include a needle probe card interface module. For example, block 102 may be associated with block 101 or included in the block.

[0061] Preferably, the contact system 200 may be arranged to:

[0062] a) receiving a current output from at least one power semiconductor device under test; or

[0063] b) Transmitting the current to be supplied as input to at least one power semiconductor device under test.

[0064] In case a), the test circuit closing terminal T may be arranged to receive a current flowing into the contact system.

[0065] In case b), the test circuit closing terminal T may be arranged to supply current to the contact system 200 .

[0066] In other words, when the power semiconductor device is put to test, current entering or flowing out of it will be allowed to flow along the associated straight and continuous current conduction path A towards the test circuit closed terminal T in the test circuit closed contact conductive portion 204 of the contact system 200 .

[0067] For each power semiconductor device, it may happen that the current entering or flowing out of the tested power semiconductor device may flow along the associated straight current conduction path A in the test circuit closing contact conducting portion 204 of the contact system 200 to the test circuit closing terminal T.

[0068] Preferably, if Figure 5b As can be seen in FIG. 1 , a first end 506 ′ of the conductive path 506 may be arranged to be connected to at least one test circuit closing terminal T. A second end 506 ″ of the conductive path 506 opposite to the first end may be arranged to be connected to a needle probe card 500 connected to a test machine. Figure 5c It shows that when the contact system 200 contacts the test circuit closing terminal T, Figure 5bA needle-type probe card 500 is shown by way of example. Figure 5c The left side of the figure shows a perspective view of the contact system and the needle probe card, while Figure 5c The right side shows a side view of the contact system and the needle probe card.

[0069] In an alternative not shown in the figures, a first end of the conductive path may be arranged to be connected to at least one test circuit closing terminal. A second end of the conductive path opposite the first end may be arranged to be directly connected to a test machine.

[0070] For either possibility, conductive pathway 506 may include one or more electrical cables.

[0071] For example, all cables may be embedded and encapsulated in an insulating sheath. The insulating sheath may be made of a non-deformable material because the position of the test circuit closing terminal T relative to the plurality of needles 502 of the needle probe card 500 is immutable.

[0072] Preferably, the test circuit closing contact conductive portion 204 and the wafer housing conductive portion 202 can be made into one piece.

[0073] Preferably, if Figure 3 In an alternative embodiment, the test circuit closing contact conductive portion 204 and the wafer housing conductive portion 202 of the contact system 200 can be at least two different components. In this case, the test circuit closing contact conductive portion 204 can be stably combined with the wafer housing conductive portion 202.

[0074] For example, to achieve a stable bond, the test circuit closing contact conductive portion 204 may be stably coupled to the wafer housing conductive portion 202 by appropriate coupling or fastening means 206 (eg, by an interlocking device or screws).

[0075] Preferably, the test circuit closing contact conductive portion 204 may include a through hole 208 or housing arranged to receive the wafer housing conductive portion 202 .

[0076] Preferably, the wafer housing conductive portion 202 may be included in the contact pad 300 .

[0077] For example, the contact tray may be of any type known in the art.In general, the contact tray is usually configured to accommodate a wafer to be tested.

[0078] For example, but not necessarily, the wafer housing conductive part 202 (e.g., contact plate) can be provided with a suction hole, for example, connected to a pump. During the test, the air sucked by the pump through the suction hole can be used to keep the wafer in a predetermined position. In fact, any displacement of the wafer W during the test may cause damage to the wafer and the test machine used to perform the test. For example, the suction hole can be formed in the support surface of the wafer housing conductive part 202. Pulling the wafer W to the wafer housing conductive part 202 can also reduce the contact resistance.

[0079] For example, a heating system may be associated with the wafer housing conductive portion 202. Such a heating system may be arranged to heat the wafer housing conductive portion 202. For example, the heating system may bring the wafer to a temperature of approximately 175° C., since dynamic testing is typically performed at this temperature (i.e., the junction temperature indicated by the data sheet of the power semiconductor device).

[0080] Preferably, the test circuit closing contact conductive portion 204 and the wafer housing conductive portion 202 may be arranged on respective planes parallel to each other, or both may be arranged on a single plane (eg, coincident with the wafer housing plane 202).

[0081] Preferably, such as Figure 2 and Figure 3 As can be seen in FIG. 2 , the contact system 200 may generally have a triangular shape. One or more vertices of the triangle may be rounded. The wafer housing conductive portion 202 of the contact system 200 may be arranged at one of the vertices of the triangle.

[0082] In an exemplary embodiment, the contact system 200 may have an isosceles triangle shape with a rounded vertex. In this case, the wafer housing conductive portion 202 may be arranged at a vertex of the triangle, the vertex being opposite to the base of the triangle.

[0083] Obviously, in different implementations, the shape of the contact system 200 may also be different, such as a rectangle or a square.

[0084] Preferably, the test circuit closure contact conductive portion 204 may be made of the same conductive material as the wafer housing conductive portion 202. The test circuit closure contact conductive portion 204 may have a thickness in the range of several millimeters.

[0085] Preferably, the test system 100 may include a handling system 400 arranged to move the contact system so that all power semiconductor devices of the wafer W arranged on the wafer housing conductive portion 202 are contacted with the plurality of needles 502 at least one at a time to be tested.

[0086] Figure 4 An exemplary embodiment of a processing system is shown in FIG.

[0087] The processing is performed in such a way that at any position to which the contact system 200 is moved by the processing system 400 , at least one test circuit closing terminal T is arranged in contact with the test circuit closing contact conductive portion 204 of the contact system 200 .

[0088] For example, in order to move the contact system 200, appropriate guides 402 may be provided and the movement may be generated by one or more electric motors M1, M2.

[0089] Preferably, if Figure 5c and Figure 6 As can be observed in , the handling system can be arranged to move the contact system according to three movement directions x, y, z that are orthogonal to each other.

[0090] Specifically, Figure 5c The direction z along which the contact system can move is shown. Figure 6 The directions of movement x and y are shown, along which the contact system can be moved.

[0091] For example, Figure 6 The center of shows the situation where the center O of the wafer housing conductive part 202 of the contact system is brought to the intersection of the movement directions x and y. Figure 6 The right side of FIG. 1 shows the positive displacement of the contact system according to the movement direction x relative to the intersection of the movement directions x and y. Figure 6 The left side of FIG. 1 shows a negative displacement of the contact system according to the movement direction x relative to the intersection of the movement directions x and y. Figure 6 The top part of FIG. 1 shows a negative displacement of the contact system according to the movement direction y relative to the intersection of the movement directions x and y. Figure 6 The bottom of the diagram shows the positive displacement of the contact system according to the movement direction y relative to the intersection of the movement directions x and y. Figure 6 , the positions of the needle probe card 500, the test circuit closing terminal T, and the conductive path 506 do not change in any of the four movement examples shown.

[0092] Preferably, the handling system 400 may be arranged to move the contacting system 200 according to a pre-established path.

[0093] Preferably, the pre-established paths may be stored in a suitable storage medium associated with or included in the test system 100 .

[0094] For example, the storage medium may be a memory such as:

[0095] - non-volatile memory, i.e. memory that retains information in the memory even in the absence of power (examples of non-volatile memory may be ROM, flash memory, most magnetic memories, etc.); and

[0096] - Volatile memory (temporary memory), which, unlike non-volatile memory, requires a continuous power supply to keep data stored (examples of non-volatile memory can be RAM [DRAM or SRAM], T-RAM, Z-RAM and TT-RAM).

[0097] For example, the path may be appropriately defined by the user according to the type of test to be performed or the shape of the wafer W.

[0098] Alternatively, the pre-established path may be determined by a predetermined high voltage, high current test function performed by the tester. In other words, the path may be automatically determined by a predetermined wafer mapping function performed by the tester.

[0099] In another aspect, the invention relates to a contact system 200 for use in a testing system 100 according to any of the embodiments described above.

[0100] The contact system includes:

[0101] - Wafer housing conductive portion 202; and

[0102] The test circuit is closed contacting the conductive part 204 .

[0103] The wafer housing conductive portion 204 is configured to accommodate a wafer W to be contacted by the plurality of needles 502 of the needle probe card 500 during testing.

[0104] The test circuit closure contact conductive portion 204 is electrically connected to the wafer housing conductive portion 202 .

[0105] In use, the test circuit closing contact conductive portion 204 is arranged to contact the test circuit closing terminal T of the test system 100, so that the test circuit closing contact conductive portion 204 of the contact system 200 is parallel to the conductive path 506 of the test system that couples at least one test circuit closing terminal T of the test system 100 to the test machine of the test system 100.

[0106] Therefore, the advantage achieved is that a test system and a contact system for use in such a test system are provided, which test system is capable of reducing parasitic inductance that may be generated when high voltage and high current tests (specifically dynamic high voltage and high current tests) are performed on multiple semiconductor devices included in a wafer, so that they can be implemented even when power semiconductor devices and other electronic devices are still embedded in the wafer.

[0107] An additional advantage is that a solution is provided for testing power semiconductor devices at a desired switching speed.

[0108] According to the present invention, various aspects and embodiments of a test system and a contact system for high voltage and high current testing of a plurality of power semiconductor devices included in a wafer have been described. It should be understood that each embodiment can be combined with any other embodiment. In addition, the present invention is not limited to the described embodiments, but can be varied within the scope defined by the appended claims.

Claims

1. A test system (100) for performing high voltage and high current testing on a plurality of power semiconductor devices included in a wafer (W), in particular for dynamic high voltage and high current testing, comprising: - a testing machine arranged to perform predetermined high voltage and high current test functions on the plurality of power semiconductor devices; - a needle probe card (500) arranged to be connected to the test machine; Wherein, the needle-type probe card (500) comprises: - a plurality of needles (502) adapted to contact at least one power semiconductor device under test when said plurality of power semiconductor devices are included in the wafer W, each needle being adapted to allow current to flow through said at least one power semiconductor device under test; The test system further comprises: - a contact system (200) comprising a wafer housing conductive portion (202) and a test circuit closing contact conductive portion (204); The wafer housing conductive portion (202) is configured to accommodate a wafer (W) to be contacted via the plurality of needles (502) of the needle probe card (500) during the test; The test circuit closed contact conductive portion (204) is electrically connected to the wafer housing conductive portion (202); The test system (100) further comprises at least one test circuit closing terminal (T), the at least one test circuit closing terminal being arranged along a predetermined invariable direction (504) and being at a predetermined invariable distance (d1) from the plurality of needles (502) of the needle probe card (500); The at least one test circuit closing terminal (T) is arranged to be in contact with the test circuit closing contact conductive portion (204) of the contact system (200); The at least one test circuit closing terminal (T) is coupled to the test machine via a conductive path (506) arranged along the predetermined invariable direction (504); A portion of the conductive path (506) facing the test circuit closing contact portion (204) is straight and parallel to the test circuit closing contact conductive portion (204) of the contact system (200); The test circuit closing contact conductive portion (204) of the contact system has a shape and extension such that a respective straight and continuous current conduction path (A) is determined from each power semiconductor device to the at least one test circuit closing terminal (T); Each current conducting path (A) extends along a direction parallel to or coincident with the predetermined invariable direction (504).

2. The test system according to claim 1, wherein: The contact system (200) is arranged to: - receiving a current flowing from the at least one power semiconductor device under test; or - delivering the current to be supplied as input to the at least one power semiconductor device under test; When the contact system (200) is arranged to receive a current flowing out of the at least one power semiconductor device under test, the test circuit closing terminal (T) is arranged to receive the current flowing into the contact system (200); When the contact system (200) is arranged to deliver the current to be supplied as input to the at least one power semiconductor device under test, the test circuit closing terminal (T) is arranged to supply the current to the contact system (200).

3. The test system according to claim 1 or 2, wherein: - a first end (506') of the conductive path (506) is arranged to be connected to the at least one test circuit closing terminal (T); and A second end (506") of the conductive path (506), opposite to the first end (506'), is arranged to be connected to the needle probe card (500).

4. A test system according to any one of the preceding claims, wherein: The test circuit closing contact conductive part (204) and the wafer housing conductive part (202) are made into one piece.

5. The test system according to any one of claims 1 to 3, wherein: The test circuit closing contact conductive portion (204) and the wafer housing conductive portion (202) are made of at least two separate components; The test circuit closed contact conductive part (204) is stably connected to the wafer housing conductive part (202).

6. The test system according to claim 5, wherein: The test circuit closed contact conductive portion (204) includes a through hole (208) or housing arranged to receive the wafer housing conductive portion (202).

7. A test system according to any one of the preceding claims, wherein: The test circuit closing contact conductive portion (204) and the wafer housing conductive portion (202) are arranged on respective planes parallel to each other, or are both arranged on a single plane.

8. A test system according to any one of the preceding claims, wherein: The contact system (200) has substantially a triangular shape; wherein one or more vertices of the triangle are rounded; Therein, the wafer housing conductive portion (202) of the contact system is arranged at one of the vertices of the triangle.

9. A test system according to any one of the preceding claims, wherein: The test circuit closing contact conductive portion (204) is made of the same conductive material as the wafer housing conductive portion (202).

10. A test system according to any one of the preceding claims, wherein: The wafer housing conductive portion (202) is included in a contact pad (300).

11. A test system according to any one of the preceding claims, comprising a handling system (400) arranged to move the contact system (200) so that all power semiconductor devices of the wafer arranged on the conductive portion of the wafer housing are contacted at least one at a time with the plurality of needles (502) and are thereby tested; in, At any position to which the contact system (200) is moved by the handling system, the at least one test circuit closing terminal (T) is arranged to be in contact with the test circuit closing contact conductive portion (204) of the contact system (200).

12. The test system according to claim 11, wherein: The handling system (400) is arranged to move the contact system according to three movement directions (x, y, z) that are orthogonal to one another.

13. The test system according to claim 11 or 12, wherein: The handling system (400) is arranged to move the contact system (200) according to a pre-established path.

14. The test system according to claim 13, wherein: The pre-established path is stored in a suitable storage device associated with or included in the test system; or, The pre-established path is determined by a predetermined wafer mapping function performed by the test machine.

15. A contact system (200) for use in a test system (100) according to any one of the preceding claims, comprising: - Wafer housing conductive part (202); as well as - the test circuit closes the contact conductive part (204); The wafer housing conductive portion (202) is configured to accommodate a wafer (W) to be contacted via a plurality of needles (502) of a needle probe card (500) during the test; The test circuit closed contact conductive portion (204) is electrically connected to the wafer housing conductive portion (202); In use, the test circuit closing contact conductive part (204) contacts the test circuit closing terminal (T) of the test system (100), so that the test circuit closing contact conductive part (204) of the contact system is parallel to the conductive path (506) of the test system that couples the at least one test circuit closing terminal (T) of the test system to the test machine of the test system.

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