Multi-node real-time power system simulation optimization system and simulation optimization method

Abstract

The invention discloses a multi-node real-time power system simulation optimization system, which is characterized in that a circuit simulation model of multiple converters is stored in an FPGA (Field Programmable Gate Array) acceleration card, and a resolving module adopts pipeline optimization, systolic array matrix multiplication and time division multiplexing computing resources, so that the consumption of the computing resources is reduced, and the time sequence performance is improved. The FPGA acceleration card is in two-way connection with the simulation main controller to perform data interaction, and the FPGA acceleration card performs identification, splicing and serial-parallel conversion on data transmitted by the simulation main controller so as to accord with the assembly line time sequence of the resolving module. According to the invention, hardware-in-the-loop real-time simulation of a multi-node power grid system can be formed with the simulation main controller and a real power grid system, the scale of a circuit simulation model can be improved by increasing the number of FPGA acceleration cards, and simulation models of a plurality of converters can be deployed on one FPGA acceleration card. And the electrical behaviors of the plurality of converters are accurately simulated in real time, so that the stable operation of the complex topology multi-node power grid system can be ensured.

Description

Technical Field

[0001] The present invention belongs to the field of power system simulation, and in particular relates to a multi-node real-time power system simulation optimization system and a simulation optimization method. Background Art

[0002] Against the background of carbon neutrality, new energy power generation equipment and new energy electrical appliances are developing rapidly, and the topology of modern power grid systems is becoming more and more complex. In order to monitor ultra-large-scale complex topology power grid systems in real time, it is necessary to run hardware in-the-loop (HIL) simulation synchronously during the actual operation of the power grid system, conduct high-speed data communication with the power grid system, calculate and analyze the data in the power grid system, check the fault points of each topological component in real time, and intervene in time when the fault occurs to ensure the accurate and stable operation of large-scale power network systems.

[0003] In recent years, due to the rapid development of semiconductor power devices, a large number of lightweight high-frequency power electronic switching devices have been connected to the power grid system, and the frequency can easily reach tens of kilohertz. In order to monitor high-frequency power electronic devices in real time, the power grid hardware-in-the-loop simulation system needs to have powerful computing power to achieve microsecond-level small-step simulation. However, due to the limitation of serial instruction set efficiency, the traditional CPU-based hardware-in-the-loop system cannot achieve microsecond-level multi-device real-time small-step simulation. Field Programmable Gate Array (FPGA) has developed very rapidly. The current international advanced FPGA chips have a super-large scale of tens of millions of gates, and DSP computing resources can reach more than 10K. Combined with the advantages of FPGA programmability, high clock frequency, strong parallel computing capability and ultra-low latency, it can meet the deployment of simulation computing models for large-scale high-frequency devices with small steps.

[0004] However, the mainstream modeling algorithms for high-frequency power electronic systems, such as the leapfrog method, the node voltage method, and the state space method, have problems such as time-varying admittance matrices, strong data dependencies, complex circuit element types, simulation data oscillations, and inconsistent simulation steps for different devices. As a result, when deploying multi-converter simulation models, the FPGA hardware consumes a lot of resources. Excessive resource usage will lead to layout and routing congestion, which will significantly reduce timing performance. Summary of the invention

[0005] The present invention aims to provide a multi-node real-time power system simulation optimization system to solve the problems of high resource consumption and high delay in real-time simulation of large-scale power electronic systems in the prior art.

[0006] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0007] A multi-node real-time power system simulation and optimization system, which is composed of a data interaction system consisting of an FPGA accelerator card, a simulation main controller and a real power grid system, realizes hardware-in-the-loop simulation of large-scale power grid systems. The FPGA accelerator card accelerates the simulation of multi-converter power grid systems with complex topology to achieve real-time data interaction with the simulation main controller.

[0008] The simulation main controller processes the converter data of the real power grid system, prepares simulation variables and switch variables, and transmits the variables to the FPGA acceleration card via Ethernet. The FPGA acceleration card performs simulation acceleration of multiple converters.

[0009] The real power grid system is bidirectionally connected to the simulation main controller, and the FPGA acceleration card is bidirectionally connected to the simulation main controller.

[0010] The simulation model step size deployed by the FPGA acceleration card is generally greater than or equal to 1 microsecond.

[0011] The FPGA accelerator card simulates the multi-converter power grid system as follows:

[0012] The simulation main controller and the FPGA acceleration card shake hands through Ethernet. The simulation main controller sends the initialization parameter matrix data packet of the real power grid system to the FPGA acceleration card. The FPGA acceleration card performs Ethernet data caching and clock domain conversion through asynchronous FIFO. The Xilinx official IP core is adopted, using a dual-port asynchronous FIFO, with a data write frequency of 125MHz and a data read frequency of 100MHz.

[0013] The simulation main controller sends the switch variable data packet of the real power grid system to the FPGA acceleration card, and the FPGA acceleration card performs Ethernet data caching and clock domain conversion through asynchronous FIFO; the simulation main controller sends different types of data packets to the FPGA. For the initialization parameter matrix data packet, the message header is 0x5a5a; for the switch variable data packet of the real power grid system, the message header is 0x55aa. The data packet identification and verification module identifies different message headers and performs different variable splicing processing respectively; for the initialization parameter matrix data packet, the simulation main controller sends it multiple times and verifies whether the data received each time is consistent with the data received last time. If it is inconsistent, it means that an error occurred during the transmission process.

[0014] The data preprocessing module deployed by the FPGA acceleration card completes the splicing of serial Ethernet byte data to simulation variable data, and then distributes the simulation variables of multiple converters to the solution module in a pipeline manner;

[0015] In the solution module, the DSP multiplier is time-division multiplexed, and the pipeline completes the calculation of historical variables, and then the historical variable results are serially converted to parallel to further complete the iterative calculation of the current vector; the current vector and admittance matrix parameters after the iterative calculation are serially transmitted to the matrix-vector multiplication module, and the matrix-vector multiplication module adopts a pulsating array. The DSP multiplier completes the calculation after multiple clock cycles to obtain a serial voltage vector;

[0016] The result verification module performs abnormal data detection and Ethernet data packet preparation on the serial voltage vector, sends it to the asynchronous FIFO module for clock domain conversion, and then transmits the packaged result to the simulation main controller through the Ethernet protocol stack.

[0017] Furthermore, the Ethernet transmission scheme adopts the User Datagram Protocol (UDP), and the Ethernet port of the FPGA acceleration card is driven by a Gigabit Ethernet physical layer chip.

[0018] Furthermore, the user datagram protocol is transmitted in bytes, that is, one byte of data is transmitted in each Ethernet working clock cycle.

[0019] Furthermore, the data preprocessing module is composed of multiple FIFOs. When initializing the Ethernet datagram reception, the variable-width FIFO is enabled to process byte data based on the little-endian priority principle, achieving 8-bit input and 64-bit output, and completing the initialization variable splicing; when receiving the switch signal Ethernet data packet, the ping-pong cache structure is enabled, and the two registers in each ping-pong cache structure are simultaneously in the read or write state in each clock cycle, exchanging the memory area for high-speed data reading and writing speed, and quickly obtaining the switch signal variable; after completing the variable splicing of each type of Ethernet data packet, a parallel-to-serial state machine is used to pass the variable to the solution module.

[0020] Furthermore, the solution module adopts a method of time-division multiplexing of computing resources according to the variables transmitted serially, and N branches calculate the same historical variable within N clock cycles; a pipeline form is used to complete the transmission of data streams between different historical variables, and serial historical variable data is calculated; the calculated historical variables of each branch are converted into parallel through a shift register for iterative calculation of the current vector.

[0021] Furthermore, the solution module adopts a matrix-vector multiplication module based on a pulsating array to perform multiplication operations of the admittance matrix and the current vector. The admittance matrix and the current vector are stored in registers in row priority, and the shift register array is enabled to serially input the admittance matrix parameters and current vector of each column into the multiplication and addition calculation module. For the M×M-dimensional admittance matrix and M-dimensional current vector, M multiplication and addition calculation modules form a multiplier array, and the calculated M-dimensional voltage vector results are output in parallel after M cycles.

[0022] Furthermore, the result verification module performs abnormal data detection on the voltage vector result calculated by the solution module. If the result data is abnormal, an abnormal message is sent to the simulation main controller. If the result data is correct, it is sent to the simulation main controller to the asynchronous FIFO, performs clock domain conversion, and then passes through the Ethernet protocol stack.

[0023] Furthermore, the simulation main controller parses the data sent back by the FPGA acceleration card and interacts with the real power grid system to ensure the stable operation of the real power grid.

[0024] A multi-node real-time power system simulation optimization method, the method comprising:

[0025] Obtaining converter data of the power grid system;

[0026] preparing simulation variables and switching variables for the converter data;

[0027] The simulation of the multi-converter is accelerated according to the simulation variables and the switch variables.

[0028] Further, performing simulation acceleration of the multi-converter according to the simulation variables and the switch variables includes:

[0029] Perform clock domain conversion on the received converter data;

[0030] Performing data packet identification and verification on the converter data;

[0031] The verified converter data is spliced ​​from serial Ethernet byte data to simulation variable data, and then the simulation variable data of multiple converters are pipelined to complete the calculation of historical variables, and the historical variable results are converted from serial to parallel to complete the iterative calculation of the current vector; according to the current vector and admittance matrix parameters after the iterative calculation, a pulsating array is used to complete the calculation after multiple clock cycles to obtain a serial voltage vector.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] (1) The present invention realizes the application acceleration of the multi-node power simulation system, adopts the resource reuse technology to significantly reduce the computing resources required for a single converter model, and supports the deployment of multiple converter models on a single FPGA board.

[0034] (2) The present invention adopts pipeline parallel design technology to improve the working clock frequency of the simulation module, meet the real-time and simulation accuracy requirements of multiple converters, and can realize the needs of real-time simulation acceleration of large-scale power grid systems.

[0035] (3) The present invention verifies the received network data packets and can detect communication problems in the transmission in a timely manner, thereby realizing stable data interaction between the FPGA acceleration card and the simulation main controller, and can realize efficient and stable interaction of simulation results and monitor the actual power grid operation status in real time.

[0036] (4) The present invention uses an Ethernet interface to connect to the simulation main controller, supports multiple FPGAs to connect to the simulation main controller, has scalability, and can increase the simulation scale of the real power grid system by increasing the number of FPGA boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the multi-converter power system simulation acceleration steps of the present invention;

[0038] Figure 2 It is a top-level connection diagram of the present invention in a real power grid-in-the-loop simulation system;

[0039] Figure 3 This is a schematic diagram of module connections of the FPGA acceleration card of the present invention;

[0040] Figure 4 A schematic diagram of the optimization strategy of the data preprocessing module for variable data according to the present invention;

[0041] Figure 5 This is a schematic diagram of a specific implementation architecture of the solution module of the present invention.

[0042] In the figure, 100, real power grid system, 200, simulation main controller, 300, FPGA acceleration card,

[0043] 301. Ethernet protocol stack, 302. Asynchronous FIFO module, 303. Data packet identification and verification module, 304. Data preprocessing module, 305. Resolution module, 306. Result verification module.

[0044] 401, variable width FIFO, 402, ping-pong buffer module, 403, variable register, 404, state machine control module,

[0045] 405. Historical voltage calculation module, 406. Historical current calculation module, 407. Intermediate historical variable calculation module, 408. Shift register sequence, 409. Current iteration calculation module, 500. Pulsating array matrix vector multiplication module. DETAILED DESCRIPTION

[0046] In order to deepen the recognition and understanding of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0047] Embodiment 1: A multi-node real-time power system simulation optimization system, the specific simulation deployment acceleration optimization steps are as follows Figure 1 As shown; the top-level system connections and data interaction relationships are as follows Figure 2 As shown; the modules in the FPGA accelerator card are connected as follows Figure 3 As shown; the specific optimization strategy of the data preprocessing module for variable data is as follows Figure 4 As shown; the specific optimization architecture of the solution module is as follows Figure 5 shown.

[0048] The real power grid system 100 and the simulated main controller 200 perform bidirectional data interaction, and the FPGA acceleration card 300 and the simulated main controller 200 perform bidirectional data interaction. Specifically, the FPGA acceleration card 300 and the simulated main controller complete bidirectional high-speed data interaction within 50 microseconds.

[0049] In the multi-node real-time power system simulation optimization system, a plurality of solution modules 305 are stored in the FPGA acceleration card 300 to meet the needs of multi-converter power system simulation. Preferably, the FPGA acceleration card 300 instantiates and deploys five solution modules 305 .

[0050] Preferably, in this example, the simulation step size of the power system simulation model deployed by the solution module 305 is 1 microsecond, and the number of iterative calculations is 50 times.

[0051] The simulation main controller 200 collects circuit information from the real power grid system 100 and prepares simulation variables and switch variables. The specific simulation process is as follows:

[0052] The simulation main controller 200 and the FPGA acceleration card 300 shake hands through Ethernet. The simulation main controller 200 sends an initialization parameter matrix data packet of the real power grid system with a message header of 0x5a5a to the FPGA acceleration card 300. The FPGA acceleration card 200 performs Ethernet data caching and clock domain conversion through the asynchronous FIFO 302.

[0053] The simulation main controller 200 sends a switch variable data packet of a real power grid system with a message header of 0x55aa to the FPGA acceleration card 300, and the FPGA acceleration card 300 performs Ethernet data caching and clock domain conversion through the asynchronous FIFO 302;

[0054] The data preprocessing module 304 deployed by the FPGA acceleration card 300 identifies different message headers to distinguish the types of Ethernet data packets, completes the splicing of serial Ethernet byte data to simulation variable data, and then distributes the simulation variables of multiple converters to the solution module 305 in a pipelined manner;

[0055] In the solution module 305, the DSP multiplier is time-division multiplexed, and the pipeline completes the calculation of the historical variables, and then the historical variable results are serially converted to parallel, and the iterative calculation of the current vector is further completed; the current vector and the admittance matrix parameters after the iterative calculation are serially transmitted to the pulsating array matrix vector multiplication module 500, and the DSP multiplier completes the calculation after multiple clock cycles to obtain a serial voltage vector;

[0056] The result checking module 306 performs abnormal data detection and Ethernet data packet preparation on the voltage vector, sends it to the asynchronous FIFO module 302 for clock domain conversion, and then transmits the packaged result to the simulation main controller 200 through the Ethernet protocol stack.

[0057] Specifically, the clock domain of the Ethernet protocol stack is 125 MHz, the clock domain of the solution module is 150 MHz, and the asynchronous FIFO 302 performs conversion between the two clock domains.

[0058] Specifically, the variable width FIFO 401 in the data preprocessing module 304 is used to process the initialization parameter matrix data with a message header of 0x5a5a, with the little-endian priority principle, 8-bit Ethernet byte data input, and 64-bit variable data stored in the variable register 403; the ping-pong cache module 402 will be in the read and write state at the same time in each clock cycle, splicing the switch signal variables, exchanging the memory area for high-speed data reading and writing speed, and quickly cache the merged switch variable signal into the variable register 403; the variable register 403 outputs the spliced ​​variable data in parallel, and the state machine control module 404 outputs the parallel variable data to the solution module 305 according to the pipeline timing required by the solution module.

[0059] Specifically, after the solution module 305 receives the variable data transmitted by the data preprocessing module 304, the historical voltage calculation module 405, the historical current calculation module 406 and the intermediate historical variable calculation module 407 are calculated in a three-stage pipeline. The calculation delay between each module historical voltage calculation module 405, the historical current calculation module 406 and the intermediate historical variable calculation module 407 is 2 clock cycles. After the solution module 305 is enabled, the pipeline starts to output the historical voltage result after 2 clock cycles, the pipeline outputs the historical current result after 4 clock cycles, and the pipeline outputs the intermediate historical variable result after 6 clock cycles. Specifically, the number of branches of the circuit simulation model in this example is 14, and the total time consumed in the pipeline calculation of historical voltage variables, historical current variables and intermediate historical variables is 18 clock cycles.

[0060] Specifically, after the solution module 305 completes the pipeline calculation of the historical voltage variables, the historical current variables and the intermediate historical variables, the shift register sequence 408 converts the results obtained by the pipeline into parallel intermediate variable results. The current iteration calculation module 409 iterates through 14 clock cycles to obtain the current vector result, which is serially output to the pulsating array matrix-vector multiplication module 500.

[0061] Specifically, the shift register sequence 408 stores the admittance matrix parameters of the initialization data packet and inputs them serially into the systolic array matrix-vector multiplication module 500 .

[0062] Specifically, the dimension of the admittance matrix is ​​8×8, and the current vector is ultimately an 8-dimensional vector.

[0063] Specifically, the pulsating array matrix vector multiplication module 500 instantiates 8 multiplication and addition calculation modules to form a pulsating array, calculates a multiplication and addition once in each cycle, and outputs the calculated 8-dimensional voltage vector in parallel after 8 cycles.

[0064] Specifically, when the number of iterative calculations reaches 50, the voltage vector result obtained by the 50th iterative calculation is used as the final simulation result, and the solution module 305 transmits it to the result verification module 306.

[0065] Specifically, the result verification module 306 performs result abnormality detection on the voltage vector. If an error occurs, the error identifier 0x5555 is transmitted to the asynchronous FIFO 302 and returned to the simulation main controller 200 through the Ethernet protocol stack 301; if no error occurs, the voltage vector result is transmitted to the asynchronous FIFO 302 and returned to the simulation main controller 200 through the Ethernet protocol stack 301.

[0066] Specifically, the number of single calculation cycles of the solution module 305 is composed of the following parts: the historical voltage calculation module 405, the historical current calculation module 406 and the intermediate historical variable calculation module 407 take 18 clock cycles, the shift register sequence 408 takes 1 clock cycle, the current iteration calculation module 409 takes 14 clock cycles, and the pulsating array matrix-vector multiplication module 500 takes 8 clock cycles. The total time consumption is 18+1+14+8=51 clock cycles.

[0067] Specifically, after 50 iterations, the time taken by the solution module is 51*50=2550 clock cycles. Calculated at a working frequency of 150 MHz, the time taken for 2550 clock cycles is 2550*6.67=17008 nanoseconds=17.008 microseconds.

[0068] Specifically, the single Gigabit Ethernet communication time between the simulated main controller 200 and the FPGA acceleration card 300 is about 12 microseconds, and the total time for the single simulated data interaction between the main controller 200 and the FPGA acceleration card 300 is about 17.009+12=29.008 microseconds, meeting the real-time simulation requirement within 50 microseconds.

[0069] Embodiment 2: A multi-node real-time power system simulation optimization method, the method comprising:

[0070] Obtaining converter data of the power grid system;

[0071] preparing simulation variables and switching variables for the converter data;

[0072] The simulation of the multi-converter is accelerated according to the simulation variables and the switch variables.

[0073] Further, performing simulation acceleration of the multi-converter according to the simulation variables and the switch variables includes:

[0074] Perform clock domain conversion on the received converter data;

[0075] Performing data packet identification and verification on the converter data;

[0076] The verified converter data is spliced ​​from serial Ethernet byte data to simulation variable data, and then the simulation variable data of multiple converters are pipelined to complete the calculation of historical variables, and the historical variable results are converted from serial to parallel to complete the iterative calculation of the current vector; according to the current vector and admittance matrix parameters after the iterative calculation, a pulsating array is used to complete the calculation after multiple clock cycles to obtain a serial voltage vector.

[0077] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The schemes in the embodiments of the present invention may be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0078] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0079] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0081] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0082] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A multi-node real-time power system simulation and optimization system, characterized in that: include: The simulation main controller is used to process the converter data of the power grid system and prepare simulation variables and switch variables; FPGA accelerator card, used to accelerate the simulation of multi-converter based on simulation variables and switch variables.

2. A multi-node real-time power system simulation and optimization system according to claim 1, characterized in that: The simulation main controller is specifically used to transmit the initial simulation variables to the FPGA acceleration card via Ethernet; The FPGA acceleration card includes an Ethernet protocol stack module, an asynchronous FIFO module, a data packet identification and verification module, a data preprocessing module, a solution module and a result verification module, wherein the asynchronous FIFO module is used to cache the data sent by the simulation main controller and convert the solution module clock domain; the data packet identification and verification module is used to perform data packet identification and verification on the data cached by the asynchronous FIFO module, and the verified data enters the data preprocessing module, and the data preprocessing module completes the splicing of serial Ethernet byte data to simulation variable data, and then distributes the simulation variable data of multiple converters to the solution module in a pipeline manner; In the solution module, the DSP multiplier is time-division multiplexed, and the pipeline completes the calculation of historical variables, converts the historical variable results serially into parallel, and completes the iterative calculation of the current vector; the current vector and admittance matrix parameters after the iterative calculation are serially transmitted to the matrix-vector multiplication module, and the matrix-vector multiplication module adopts a pulsating array. The DSP multiplier completes the calculation after multiple clock cycles to obtain a serial voltage vector; the result verification module performs abnormal data detection and Ethernet data packet preparation on the serial voltage vector, sends it to the asynchronous FIFO module for clock domain conversion, and then transmits the packaged result to the simulation main controller through the Ethernet protocol stack.

3. A multi-node real-time power system simulation and optimization system according to claim 2, characterized in that: The data packet identification and verification module performs data packet identification and verification on the data cached by the asynchronous FIFO module, as follows: the simulation main controller sends different types of data packets to the FPGA. For the initialization parameter matrix data packet, the message header is 0x5a5a; for the switch variable data packet of the real power grid system, the message header is 0x55aa. The data packet identification and verification module identifies different message headers and performs different variable splicing processing respectively; For the initialization parameter matrix data packet, the simulation main controller sends it multiple times and verifies whether the data received each time is consistent with the data received last time. If it is inconsistent, it means that an error occurs during the transmission process.

4. A multi-node real-time power system simulation and optimization system according to claim 2, characterized in that: The data preprocessing module is composed of multiple FIFOs. When the Ethernet data packet is initialized, the variable-width FIFO is enabled to process the byte data and complete the initialization simulation variable splicing based on the little-endian priority principle. When the switch signal Ethernet data packet is received, the ping-pong cache structure is enabled. The two registers in each ping-pong cache structure are in the read and write states at the same time in each clock cycle, and the memory area is exchanged for the data reading and writing speed to quickly obtain the switch signal variable. After the variable splicing is completed in each type of Ethernet data packet, the parallel-to-serial state machine is used to pass the variable to the solution module.

5. A multi-node real-time power system simulation and optimization system according to claim 2, characterized in that: The solution module adopts the method of time-division multiplexing of computing resources according to the variables transmitted serially, and N branches calculate the same historical variable within N clock cycles; the data stream is transmitted between different historical variables in the form of a pipeline, and serial historical variable data is calculated; the calculated historical variables of each branch are converted into parallel through a shift register for iterative calculation of the current vector.

6. A multi-node real-time power system simulation and optimization system according to claim 2, characterized in that: The solution module adopts a matrix-vector multiplication module based on a pulsating array to perform multiplication operations on the admittance matrix and the current vector. The admittance matrix and the current vector are stored in registers in a row-first manner, and the shift register array is enabled to serially input the admittance matrix parameters and the current vector of each column into the multiplication-addition calculation module. For an M×M-dimensional admittance matrix and an M-dimensional current vector, M multiplication-addition calculation modules form a multiplier-adder array, and the calculated M-dimensional voltage vector results are output in parallel after M cycles.

7. A multi-node real-time power system simulation and optimization system according to claim 2, characterized in that: The result verification module performs abnormal data detection on the voltage vector result calculated by the solution module. If the result data is abnormal, an abnormal message is sent to the simulation main controller. If the result data is correct, it is sent to the asynchronous FIFO of the simulation main controller for clock domain conversion and then passed through the Ethernet protocol stack.

8. A multi-node real-time power system simulation and optimization system according to claim 1, characterized in that: The real power grid system is bidirectionally connected to the simulation main controller, and the FPGA acceleration card is bidirectionally connected to the simulation main controller. The simulation model step size deployed by the FPGA acceleration card is greater than or equal to 1 microsecond, more than 10 converter models are deployed, and online parameter change simulation is supported.

9. A multi-node real-time power system simulation optimization method, characterized in that: include: Obtaining converter data of the power grid system; preparing simulation variables and switching variables for the converter data; The simulation of the multi-converter is accelerated according to the simulation variables and the switch variables.

10. A multi-node real-time power system simulation method according to claim 9, characterized in that: The method of accelerating the simulation of the multi-converter according to the simulation variables and the switch variables includes: Perform clock domain conversion on the received converter data; Performing data packet identification and verification on the converter data; The verified converter data is spliced ​​from serial Ethernet byte data to simulation variable data, and then the simulation variable data of multiple converters are pipelined to complete the calculation of historical variables, and the historical variable results are converted from serial to parallel to complete the iterative calculation of the current vector; according to the current vector and admittance matrix parameters after the iterative calculation, a pulsating array is used to complete the calculation after multiple clock cycles to obtain a serial voltage vector.

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