Layer sensing write-in method based on balance of interlayer durability of 3D NAND flash memory

Abstract

The invention discloses a layer perception write-in method based on balance of 3D NAND flash memory interlayer durability, and relates to the technical field of solid state disks, the method comprises the following steps: introducing a write skip unit and a layer perception table, using a flash memory conversion layer to select active pages for a write request in sequence, and determining the level to which the active pages belong; based on the layer perception table, the skipping probability of the corresponding layer of the active page is searched, and the obtained skipping probability is transmitted to a write skipping unit; and the write skipping unit judges whether write skipping operation is executed or not according to the skipping probability transmitted by the layer perception table until a target address is found and returned to the flash translation layer. Therefore, by adopting the method, the increase of BER (Bit Error Rate) of the bottom layer page is effectively slowed down, the inter-layer bit error rate difference is balanced, the bottom layer page is more likely to execute write skip operation, the target address is repositioned to the page with higher durability, and the service life of the 3D NAND flash memory is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of solid-state hard disks, and in particular to a layer-aware writing method based on balancing the durability between layers of a 3D NAND flash memory. Background Art

[0002] With the rapid development of artificial intelligence, cloud computing and Internet of Things technologies, the scale of global data is experiencing explosive growth. In order to meet the demand for larger storage capacity, flash memory suppliers have been actively increasing the number of vertical layers to adapt to this demand. As a result, the structure of flash memory has gradually shifted from 2D NAND to 3D NAND. However, compared with 2D NAND flash memory, the manufacturing process of 3D NAND is more complicated. Specifically, since 3D NAND flash memory is manufactured using a vertical continuous etching process from the top layer to the bottom layer, there are huge process differences between the stacked layers, and the process differences lead to inconsistent wear rates of each flash memory unit; according to the durability characteristics, all stacked layers can be roughly divided into the bottom layer, the middle layer and the top layer, among which the BER growth rate of the bottom page is much higher than that of the other two layers. The main reason that restricts the life of 3D NAND SSD is that the BER growth rate of the bottom page is much higher than that of the other two layers, causing the block to be regarded as a bad block by the FTL more quickly, seriously affecting the life of 3D NAND flash memory.

[0003] Currently, there are studies on extending the life of flash memory by continuing to use flash memory blocks after they have become bad blocks. However, the BER of the bottom layer is greater than that of the middle and top layers, and the BER of pages in the same layer is similar, which means that when the pages belonging to the bottom layer in a block exceed the BER, other pages at the bottom layer will also exceed the error correction capability of ECC, which will cause the number of bad pages in the block to reach the preset threshold very quickly. This technology is not ideal in extending the life of flash memory. On the other hand, there are studies on reducing the erase voltage of pages with larger BER to slow down the BER growth rate of these pages. This method effectively delays the time when the block becomes a bad block. However, since the reduced effective erase voltage is only 3V, the effect of extending the life is also limited.

[0004] Therefore, it is necessary to propose a new layer-aware write strategy that uses write skip operations with different probabilities for pages in different layers according to the wear characteristics between stacked layers to extend the life of 3D NAND flash memory. Summary of the invention

[0005] The purpose of the present invention is to provide a layer-aware write method based on balancing the durability between layers of 3D NAND flash memory, which can perform a write skip operation on the bottom layer with the worst durability with a higher probability, thereby achieving durability balance between layers.

[0006] To achieve the above object, the present invention provides a layer-aware writing method based on balancing the durability between 3D NAND flash memory layers, comprising the following steps: Using the flash translation layer to sequentially select active pages for write requests and determine the tier to which they belong; Based on the layer-aware table, the skip probability of the corresponding layer of the active page is searched, and the obtained skip probability is passed to the write skip unit; The write skip unit determines whether to perform a write skip operation according to the skip probability transmitted by the layer perception table, until the target address is found and returned to the flash translation layer.

[0007] Preferably, the layers to which the active page belongs include a bottom layer, a middle layer and a top layer, and different write skip probabilities are set for each layer and stored in a layer-aware table.

[0008] Preferably, the layers are arranged in order from high to low according to the write skip probability, namely, the bottom layer, the top layer and the middle layer.

[0009] Preferably, when the write skip unit determines to perform a write skip operation, the current active page is sequentially shifted back by one page, and the process is repeated until the write skip operation is not performed and the current active page is used as the target address.

[0010] Therefore, the present invention adopts the above-mentioned layer-aware write method based on balancing the durability between layers of 3D NAND flash memory, which has the technical effect of taking into account the bit error rate characteristics between layers of 3D NAND flash memory, effectively slowing down the growth of the BER of the bottom page, and transferring the pressure to the top and middle layer pages, so that the top and middle layer pages are also fully utilized, balancing the bit error rate differences between layers, and significantly extending the life of the 3D NAND flash memory.

[0011] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 LA-Write overall architecture diagram in an embodiment of a layer-aware writing method based on balancing the durability between 3D NAND flash memory layers; Figure 2 It is a schematic diagram of the execution flow of Write-SkipUnit in an embodiment of a layer-aware write method based on balancing the durability between 3D NAND flash memory layers. DETAILED DESCRIPTION

[0013] The present invention can be explained in more detail by the following examples. The purpose of disclosing the present invention is to protect all changes and improvements within the scope of the present invention. The present invention is not limited to the following examples.

[0014] like Figure 1As shown, the layer-aware write method (LA-Write) based on balancing the durability between 3D NAND flash memory layers provided by the present invention includes two parts: a layer-aware table (Layer-Aware Table) and a write-skip unit (Write-Skip Unit). When the flash translation layer (FTL) selects an active page as a target write page for an incoming write request, the traditional write strategy follows the selection of the FTL and directs the write request to the active page selected by the FTL, while the target page of the write may be changed in this embodiment.

[0015] In this embodiment, the SSD controller introduces a layer-aware write method, which first determines which layer the active page selected by the FTL belongs to, and then queries the Layer-Aware Table to obtain the probability according to the layer, and then the write skip unit will obtain the final target write page of the write request according to the probability. In actual operation, the role of LA-Write is to guide more write operations to the layer with stronger durability, reduce the burden on the layer with weaker durability, and balance the persistence of pages between layers.

[0016] Since the wear of the flash memory is mainly caused by repeated write and erase operations, the wear of the pages can be reduced by reducing the write operations on the pages with poor durability, thereby extending the life of the flash memory. Therefore, in this embodiment, a write skip unit is introduced in the sensing write method to achieve the purpose of extending the life of the flash memory. The specific process is as follows: The write skip unit uses the probability transmitted by the layer perception table to determine whether to perform a write skip operation. Among them, write skip means that the target address of the write request will skip the current active page and move back one page in sequence. The write skip unit will repeat this process until it chooses not to perform a write skip. At this time, the target address of the write request is determined, which is the current active page, that is, the target write page. From the first time the layer perception table transmits the probability to the write skip unit to the write skip unit determining the final physical address of the write request, the entire process operates as follows: Figure 2 As shown. Figure 2 In the example, the VALID page indicates a valid data page that has been written, the ACTIVE page is a target address page that the FTL allocates to a write request in a traditional write operation, and in this embodiment, it can be understood as the current target address, the SKIPPED page indicates a page that is skipped using a write skip operation, and the CLEAN page is a page that is neither written nor skipped. The specific operations are as follows: (1) First, P0 and P1 are used as VALID pages, which means that data has been written to these two physical pages. Since the pages in a block must be written sequentially, the FTL uses P2 as the active page and executes the write skip process of this write request starting from P2.

[0017] (2) LA-Write finds the probability of performing a write skip on the current target address (i.e., P2) from the Layer-Aware Table and passes it to the Write-Skip Unit. The Write-Skip Unit then decides to perform a write skip operation on P2 based on the probability, and the ACTIVE page is moved to P3 in sequence.

[0018] (3) Since the Write-Skip Unit performed a write skip last time, the write skip process will continue. The Write-Skip Unit again decides to perform a write skip on P3 based on the probability, and the ACTIVE page is moved to P4 in sequence.

[0019] (4) Continue to execute the process on P4. At this time, the Write-Skip Unit decides not to perform a write skip based on the probability, so P4 is the final physical address of the write request, and the write skip process for the write request is completed. The next write request will start the write skip process from P5.

[0020] In the same write environment, in the traditional sequential write process, FTL will directly use P2 as the physical address of this write request, and after executing LA-Write, the physical address of the write request becomes P4. Among them, since the write skip unit chooses to perform a write skip operation on P2 and P3, these two pages may be at the bottom layer of the 3D NAND flash memory. As more writes / erases occur, the number of write operations performed on the bottom layer will be significantly less than that of other layers, which extends the life of the bottom layer page and also extends the life of the entire block.

[0021] Next, this embodiment will introduce another important implementation of LA-Write, namely Layer-Aware Table. Since the growth rate of the bottom layer bit error probability (BER) is much faster than that of other stacked layers, when the BER of the bottom layer page exceeds the error correction capability of ECC, the BER of the middle and top layer pages is far from reaching the upper limit of the error correction capability of ECC. This extreme imbalance in durability between layers will seriously affect the life of the entire block. Based on this, this embodiment designs the Layer-Aware Table to alleviate the growth rate of the BER of the bottom layer pages. The Layer-Aware Table stores the probability of performing a write skip operation on the pages of each layer, and the specific probability settings are: 20% for the bottom layer, 5% for the middle layer, and 10% for the top layer.

[0022] The reasons for setting the probability values ​​of each layer in the Layer-Aware Table are as follows: First, if the probability is set too high, too many write skip operations will occur when processing write requests, which will reduce the available space in the flash memory, lead to garbage collection, and increase the loss pressure of the flash memory block. If the probability is set too low, the number of times the bottom page triggers a write skip operation will be reduced, the durability difference between the bottom layer and other layers cannot be alleviated, and the growth rate of the bottom layer page bit error rate cannot be effectively alleviated. This embodiment sets the probabilities of the bottom layer, top layer, and middle layer to 20%, 10%, and 5%, respectively, which is most suitable for balancing the durability between different layers in the block.

[0023] The write skip unit decides whether to perform a write skip based on the probability in this table. In other words, as long as the probability of performing a write skip operation on the bottom layer is set to the highest, the probability of the middle layer is set to the lowest, and the probability of the top layer is set between the two, the number of write skips performed on the bottom page will increase accordingly, and more write operations will be directed to the middle and top layers with better durability, which will balance the durability of different layers and extend the life of the SSD.

[0024] In summary, the workflow of LA-Write can be roughly divided into two steps. First, LA-Write searches for the probability of the corresponding entry in the Layer-Aware Table; then, the Write-Skip Unit in LA-Write will perform the write skip process to obtain the final target address, as follows: (1) LA-Write will first determine which of the three layers the active page determined by FTL for this write request belongs to, and then will look up the probability of the corresponding layer in the Layer-Aware Table. After completing the above steps, LA-Write obtains the probability of executing the write skip for the first time in the write skip process.

[0025] (2) When executing the write skip process, if the Write-Skip Unit decides to perform a write skip operation this time, the final physical write address cannot be determined after the write skip is executed, and LA-Write moves the active page to the next page in sequence; then, LA-Write determines which layer the current active page belongs to, and searches the Layer-Aware Table for the corresponding probability based on the layer number, and uses this probability to decide whether to perform a write skip this time. Repeat the above process until it decides not to perform a write skip operation. At this time, LA-Write determines that the current active page is the final target address and returns it to the FTL.

[0026] LA-Write reduces the wear pressure of the page by probabilistically performing write skips on the physical page. Since the probability settings of different layers in the Layer-Aware Table are different, and these probabilities determine the number of write skips performed on each layer, the wear pressure of each layer is alleviated to different degrees. In LA-Write, it is more likely to relocate the target page with poor durability allocated by the FTL to a page with stronger durability, which will reduce the wear on the layer with poor durability and narrow the life gap between different layers, ultimately extending the life of the SSD.

[0027] Therefore, the present invention adopts the above-mentioned layer-aware writing method based on balancing the durability between layers of 3D NAND flash memory, which effectively slows down the growth of the BER of the underlying page, balances the difference in bit error rate between layers, and can significantly extend the life of the 3D NAND flash memory.

[0028] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A layer-aware writing method based on balancing the durability between layers of 3D NAND flash memory, characterized in that: The following steps are involved: Using the flash translation layer to sequentially select active pages for write requests and determine the tier to which they belong; Based on the layer-aware table, the skip probability of the corresponding layer of the active page is searched, and the obtained skip probability is passed to the write skip unit; The write skip unit determines whether to perform a write skip operation according to the skip probability transmitted by the layer perception table, until the target address is found and returned to the flash translation layer.

2. The layer-aware writing method based on balancing the durability between layers of 3D NAND flash memory according to claim 1 is characterized in that: The layers to which the active page belongs include the bottom layer, the middle layer, and the top layer. Different write skip probabilities are set for each layer and stored in the layer-aware table.

3. The layer-aware writing method based on balancing the durability between layers of 3D NAND flash memory according to claim 2 is characterized in that: The layers are arranged in order from high to low according to the write skip probability: bottom layer, top layer, and middle layer.

4. The layer-aware writing method based on balancing the durability between 3D NAND flash memory layers according to claim 1 is characterized in that: When the write skip unit determines to perform a write skip operation, the current active page is sequentially shifted back by one page, and the process is repeated until the write skip operation is not performed and the current active page is used as the target address.

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