PCIe test system, method, device and medium

Abstract

The invention relates to the technical field of FPGA testing, in particular to a PCIe testing system, method and device and a medium, and the method comprises the steps: obtaining connection state information, and sending test data to a PCIe management and control component under the condition that the connection state information is connection success; acquiring first completion mark information, performing first expected analysis on the first completion mark information, and acquiring second completion mark information under the condition that a first analysis result obtained by analysis is in accordance with expectation; and performing second expected analysis on the second completion mark information to obtain a second analysis result for reflecting RP and EP test conditions, thereby reducing test time consumption of PCIe in the FPAG and improving test efficiency.

Description

Technical Field

[0001] The present application relates to the field of FPGA testing technology, and in particular to a PCIe testing system, method, device, and medium. Background Art

[0002] With the development of technology, traditional PCIe chips are increasingly used in FPGAs. Traditional testing methods usually measure RP and EP separately during the test process, which not only increases equipment investment but also prolongs the test cycle.

[0003] In the current testing process, to fully verify functionality, detailed testing of both the RP and EP modes is required. However, for the same chip, both RP and EP modes must be tested, and the test equipment must frequently switch between test configurations and test environments. This results in extremely low resource utilization, unnecessary waste of resources, and even affects test efficiency, making testing time longer. These issues need to be addressed. Summary of the Invention

[0004] In order to reduce the time consumption for testing PCIe in FPAG and improve testing efficiency, the present application provides a PCIe testing system, method, device and medium, which adopt the following technical solutions:

[0005] In a first aspect, the present application provides a PCIe test system, comprising:

[0006] A PCIe management and control component is configured to obtain test data of a test terminal component, parse the test data to obtain first TLP message information and second TLP message information, perform a first test operation according to the first TLP message information, and obtain first completion flag information;

[0007] The PCIe device-side component is configured to obtain second TLP message information of the PCIe control component, perform a second test operation according to the second TLP message information, and obtain second completion flag information;

[0008] The test terminal component is used to obtain connection status information, and when the connection status information indicates a successful connection, send test data to the PCIe control component; obtain first completion flag information, perform a first expected analysis on the first completion flag information, and when the first analysis result obtained by the analysis is in line with expectations, obtain second completion flag information; perform a second expected analysis on the second completion flag information to obtain a second analysis result used to reflect the RP and EP test conditions.

[0009] Preferably, the PCIe management and control component includes:

[0010] Serial port parsing module, used to parse the test data according to the serial port protocol to obtain valid serial port information;

[0011] The instruction conversion module is used to control the reading and writing of TLP according to the internally defined user register to obtain instruction information.

[0012] Preferably, the PCIe management and control component further includes:

[0013] The RP TLP sending processing module is used to send the corresponding first TLP message information and second TLP message information to the RP controller according to the instruction information;

[0014] The RP controller is configured to send the second TLP message information to the opposite-end EP device and obtain processing status information of the opposite-end EP device.

[0015] Preferably, the PCIe management and control component further includes:

[0016] The RP TLP receiving and processing module is used to obtain processing status information and obtain first completion flag information according to the processing status information.

[0017] Preferably, the PCIe device-side components include:

[0018] The EP TLP sending and receiving processing module is used to obtain the second TLP message information of the EP controller, perform a parsing operation on the second TLP message information, and obtain second completion flag information during the parsing process, where the second completion flag information includes CPL message information and CPLD message information;

[0019] The EP controller is used to obtain the second TLP message information of the PCIe control component, transmit the second TLP message information to the EP TLP sending and receiving processing module, and send the received CPL message information and CPLD message information to the opposite RP device.

[0020] Preferably, it also includes:

[0021] The clock divider module is used to obtain the 25MHz system clock signal and build the serial port processing clock and user clock for data processing based on the 25MHz system clock signal.

[0022] Preferably, the PCIe management and control component further includes:

[0023] Clock configuration module, used to initialize and configure the clock chip.

[0024] In a second aspect, the present application provides a PCIe testing method, comprising:

[0025] Obtain connection status information, and if the connection status information indicates a successful connection, send test data to the PCIe control component;

[0026] Acquire first completion mark information, perform a first expectation analysis on the first completion mark information, and acquire second completion mark information if the first analysis result obtained by the analysis is consistent with the expectation;

[0027] A second expected analysis is performed on the second completion mark information to obtain a second analysis result reflecting the RP and EP test conditions.

[0028] In a third aspect, the present application provides a test terminal device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the PCIe test method as described above.

[0029] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the PCIe test method as described above when running.

[0030] In summary, compared with the prior art, the technical solution provided by this application has at least the following beneficial effects:

[0031] The present application connects a test terminal component with a PCIe control component, connects a PCIe control component with a PCIe device-side component, and controls the PCIe control component and the PCIe device-side component to execute test steps through the test terminal component, so that all components of the test system operate in the same operating environment, and simultaneously complete the test of the PCIe control component and the PCIe device-side component. After the test, the test terminal component analyzes the flag information obtained from the test to obtain a first analysis result and a second analysis result, thereby judging the test status of the PCIe system and completing data testing and verification. In the same test environment, there is no need to frequently switch hardware or software settings, thereby reducing the time consumption of PCIe testing in FPAG and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a module diagram of a PCIe test system described in an embodiment of the present application.

[0033] Figure 2 It is a schematic diagram of the system modules of RC docking EP described in an embodiment of the present application.

[0034] Figure 3 This is a schematic diagram of the module topology of the RP connected to the EP described in the embodiment of the present application.

[0035] Figure 4 This is a flow chart of a PCIe testing method described in an embodiment of the present application.

[0036] Description of reference numerals:

[0037] 1. PCIe control and management components; 2. PCIe device-side components; 3. Test terminal components. DETAILED DESCRIPTION

[0038] The following combination Figure 1-Figure 4 To further explain the present application in detail, the terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to be limiting.

[0039] FPGA, short for Field Programmable Gate Array, is a further development of programmable devices such as Programmable Array Logic (PAL) and General Array Logic (GAL). It emerged as a semi-custom circuit within the field of Application-Specific Integrated Circuits (ASICs), addressing both the shortcomings of custom circuits and the limited gate count of existing programmable devices. Three types of PCIe are generally available within FPGAs. PCIe, short for Peripheral Component Interconnect Express, is a high-speed serial computer expansion bus standard that replaced the older Peripheral Component Interconnect (PCI) and Accelerated Graphics Port (AGP) bus standards. It features high-speed, point-to-point, dual-channel, high-bandwidth transmission. Connected devices are allocated dedicated channel bandwidth and do not share bus bandwidth. It primarily supports active power management, error reporting, and end-to-end reliable transmission. Depending on the usage scenario, users can configure PCIe within the FPGA as a Root Port (RP), Endpoint (EP), or Legacy Endpoint. Legacy Endpoints function similarly to Endpoints, but differ significantly from Root Ports. The RP, as part of the CPU-side Root Complex (RC), connects to the downstream Switch or Endpoint and transmits PCIe link data to the RC. The EP device, typically a separate device, acts like an interrupt node, receiving commands and data transfer requests from the RC. Traditional testing methods typically measure the RP and EP independently, increasing equipment investment and extending test cycles. Therefore, an optimized PCIe test system is provided.

[0040] Reference Figure 1 , a PCIe test system involved in this application specifically includes:

[0041] A PCIe management and control component is configured to obtain test data of a test terminal component, parse the test data to obtain first TLP message information and second TLP message information, perform a first test operation according to the first TLP message information, and obtain first completion flag information;

[0042] The PCIe device-side component is configured to obtain second TLP message information of the PCIe control component, perform a second test operation according to the second TLP message information, and obtain second completion flag information;

[0043] The test terminal component is used to obtain connection status information, and when the connection status information indicates a successful connection, send test data to the PCIe control component; obtain first completion flag information, perform a first expected analysis on the first completion flag information, and when the first analysis result obtained by the analysis is in line with expectations, obtain second completion flag information; perform a second expected analysis on the second completion flag information to obtain a second analysis result used to reflect the RP and EP test conditions.

[0044] Specifically, in order to solve the problem of frequent switching during RP and RP testing, the present application connects the test terminal component and the PCIe control component, and the PCIe control component and the PCIe device-side component, so that the components related to the test system are all set in the same test environment. The PCIe control component and the PCIe device-side component are specifically components on the same board that are set to different modes. The board is connected to a test terminal, such as a computer, and then different FPGA bit stream files are downloaded to configure it into RP and EP modes, and then connected using a PCIe extension cable through a gold finger. The test terminal component and the PCIe control component are connected via a serial bus to Type-C cable. Each board is provided with a chip that converts USB to Type-C and then to a serial port. When powered on, the USBTYPE-C bus is connected to the test terminal component and is recognized as a COM port. The test terminal component can initiate various serial port instructions for register reading and writing to the PCIe RP in the RP board through the serial port, and the RP converts these register operations into PCIe TLP transactions. The test terminal component controls the PCIe control component and the PCIe device-side component to execute the test steps, so that the components of the test system all operate in the same operating environment, and the test of the PCIe control component and the PCIe device-side component is completed at the same time. The test terminal component first obtains the connection status information of the PCIe control component and the PCIe device-side component, and performs further test data sending operations when the test shows that the connection is successful. Otherwise, it continues to judge the connection status information until both are displayed as successful connections. The PCIe control component parses the test data to obtain the first TLP message information for testing and judging the RP board and the second TLP message information for testing and judging the EP board. The second TLP message information is transmitted to the EP board through the gold finger and the flexible cable. After processing, the EP board transmits the information back to the RP board through the gold finger and the flexible cable, and finally transmits it to the test terminal component for analysis and judgment. After the test, the test terminal component analyzes the flag information obtained from the test to obtain the first analysis result and the second analysis result, thereby judging the test status of the PCIe system and completing data testing and verification. In the same test environment, there is no need to frequently switch hardware or software settings, which reduces the test time of PCIe in FPAG and improves test efficiency.

[0045] As one implementation method, it also includes:

[0046] The clock divider module is used to obtain the 25MHz system clock signal and build the serial port processing clock and user clock for data processing based on the 25MHz system clock signal.

[0047] Reference Figure 2 and Figure 3Specifically, in the system testing PCIe in FPGA, the reference clock and reset signal affect the stability of PCIe data transmission. In the embodiment of the present application, the boards corresponding to RP mode and EP mode are both equipped with a high-precision, low-jitter NCS23345 clock chip and a 25MHz single-ended crystal oscillator, where the 25MHz crystal oscillator provides the system clock for the FPGA, and the NCS23345 clock chip outputs a stable 100MHz reference clock after being programmed by the FPGA. The 100MHz output of the NCS23345 is input to the reference clock input pins REFCLK0P_94 and REFCLK0N_94 of the local SERDES channel, and at the same time, it is shared with the input of the opposite-end PCIe reference clock through the gold finger PCIe_X4 reference clock pins REFCLK+ and REFCLK-, so that the PCIe reference clocks in the system are homologous. SERDES is the abbreviation of SERializer and DESerializer. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals. After passing through transmission media such as optical cables or copper wires, the high-speed serial signals are finally converted back into low-speed parallel signals at the receiving end.

[0048] The clocks within the FPGA include the serial port processing clock uart_clk and the user clock tl_clk_user. The 25MHz system clock generated by the on-board crystal oscillator is generated after passing through the clock division module and is used for serial port data parsing and user data processing.

[0049] As one implementation method, the PCIe control component further includes:

[0050] Clock configuration module, used to initialize and configure the clock chip.

[0051] Specifically, the FPGA in this embodiment employs a simultaneous RP and EP reset mechanism for the reset signal. While the RP is being reset, the EP is also reset via the gold finger PERSET. Resetting the RP also resets the EP, ensuring a thorough reset and conforming to the reset procedure used when connected to a computer. The NCS2345 clock configuration module in the RP is used to initialize and configure the NCS2345 clock chip, enabling it to generate a 100MHz reference clock.

[0052] In one implementation, the PCIe control component includes:

[0053] Serial port parsing module, used to parse the test data according to the serial port protocol to obtain valid serial port information;

[0054] The instruction conversion module is used to control the reading and writing of TLP according to the internally defined user register to obtain instruction information.

[0055] Specifically, the test terminal component of the present embodiment, i.e., a computer, initiates serial port commands through the serial port. These commands are processed by the serial port chip and ultimately exchange data with the serial port parsing module within the FPGA via the serial port receive port and the serial port transmit port. The serial port parsing module parses the valid serial port information according to the serial port protocol and passes the extracted information to the instruction conversion module. The instruction conversion module then controls the reading and writing of TLPs based on internally defined user registers.

[0056] As one implementation method, the PCIe control component further includes:

[0057] The RP TLP sending processing module is used to send the corresponding first TLP message information and second TLP message information to the RP controller according to the instruction information;

[0058] The RP controller is configured to send the second TLP message information to the opposite-end EP device and obtain processing status information of the opposite-end EP device.

[0059] Specifically, the RP TLP transmission processing module in the embodiment of the present application is specifically a PCIe RP TLP transmission processing module. It initiates a corresponding TLP request based on the instruction processed by the instruction conversion module, composes a TLP request packet of CFGWR0, CFGRD0, IOWR, IORD, MEMWR, or MEMRD according to the TLP message format, and sends it to the data transmission interface of the PCIe RP controller. The TLP request packet is then sent to the peer EP device through a physical connection. That is, the RP controller sends the corresponding first TLP message information and second TLP message information to the peer EP device based on the instruction information. The RP controller sends the message to the peer EP device, that is, to the PCIe EP controller.

[0060] The PCIe RP controller and PCIe EP controller are FPGA-integrated PCI Express controller cores, providing high-bandwidth, configurable, and highly reliable PCI Express interconnection.

[0061] As one implementation manner, the RP TLP receiving and processing module is configured to obtain processing status information and obtain first completion flag information based on verification of the processing status information.

[0062] Specifically, in the embodiment of the present application, the first TLP message information acts on the RP TLP receiving and processing module of the RP board, and a first test operation is performed when the first TLP message information is obtained. The first completion flag information is returned to the test terminal component through the instruction conversion module and the serial port parsing module for analysis and judgment.

[0063] The PCIe RP TLP receive processing module is connected to the PCIe RP controller's data receive interface. It parses TLP messages received from the peer EP device and returns a TLP request completion flag and the 32-bit data received from the receive processing module's internal ERAM. When PRBS mode is enabled, it only returns a check to see if errors occurred in the current data. This return information is output to the computer via the command conversion module and serial port parsing module. The computer then analyzes the TLP request transmission and verifies that the data meets expectations.

[0064] In one implementation, the PCIe device-side components include:

[0065] The EP TLP sending and receiving processing module is used to obtain the second TLP message information of the EP controller, perform a parsing operation on the second TLP message information, and obtain second completion flag information during the parsing process, where the second completion flag information includes CPL message information and CPLD message information;

[0066] The EP controller is used to obtain the second TLP message information of the PCIe control component, transmit the second TLP message information to the EP TLP sending and receiving processing module, and send the received CPL message information and CPLD message information to the opposite RP device.

[0067] Specifically, the PCIe EP TLP sending and receiving processing module in the embodiment of the present application is responsible for parsing the TLP messages received by the data receiving interface of the PCIe EP controller to extract corresponding information. When parsing an IO write request TLP or a memory write request TLP, it stores the different TLP write request data separately and returns a CPL message when parsing an IO write request. When parsing an IO read request TLP or a memory read request TLP, it extracts data from the previously stored data to form a CPLD message of corresponding length and sends it to the peer RP device via the data sending interface of the PCIe EP controller. Among them, CPL is a completion packet without data, and CPLD is a completion packet with data.

[0068] One embodiment of the present application is to test the terminal component, that is, the computer calls the serial port through a Python script, and judges whether the current test result meets the expectation based on the serial port command sent and the returned result, thereby performing automated testing and stability testing. The test steps are as follows:

[0069] Step 1: After connecting the hardware circuit, power on and load the FPGA bitstream files of RP and EP respectively.

[0070] Step 2: Read the PCIe Link status on the RP side. If it meets expectations, proceed to step 3. Otherwise, stop the process.

[0071] Step 3: Enable Bus Master and Mem Space in the PCIe Command register on the RP side. Bus Master refers to the bus master, and Mem Space refers to the memory space.

[0072] Step 4: Generate an instruction to enable the RP to read the EP Device ID and Vendor ID through the configuration read request TLP. If they meet the expectations, execute step 5; otherwise, stop running. The Device ID is the device ID and the Vendor ID is the manufacturer ID. Complete the first test operation and feedback whether the expected result is met as the first completion flag information.

[0073] Step 5: Generate instructions to enable the RP to configure EP IO and MEM Space through the configuration write request TLP, where MEMSpace is the memory space.

[0074] Step 6: Generate an instruction to enable the RP to configure the corresponding BAR space base address through the configuration write request TLP.

[0075] Step 7: Generate instructions for the RP to configure the EP MPS and MRRS by configuring the write request TLP. EP MPS is the MaxPayloadSize, i.e., the maximum payload size of the EP, and MRRS is the MaxReadRequestSize, i.e., the maximum read request size.

[0076] Step 8: Generate instructions to configure RP MPS and MRRS.

[0077] Step 9: Generate an instruction for the RP to configure the EP RCB by configuring the write request TLP. RCB stands for Read Completion Boundary, which defines the boundary for aligning the data addresses of the completion messages when a memory read request requires multiple memory read completion messages to respond.

[0078] Step 10: Generate an instruction to enable RP to write data to EP through a memory write request TLP.

[0079] Step 11: Generate an instruction to enable the RP to read the EP data through the memory read request TLP and verify whether the result is as expected. If so, execute step 12; otherwise, stop running.

[0080] Step 12: Generate an instruction to enable the RP to write data to the EP through the IO write request TLP.

[0081] Step 13: Generate an instruction to enable the RP to read the EP data through an IO read request TLP and verify whether the result meets the expectation. If so, execute step 14; otherwise, stop the operation. Steps 11 and 13 complete the second test operation, thereby obtaining the second completion flag information.

[0082] Step 14: Check whether the number of tests meets the test requirements. If yes, stop the test; otherwise, go to step 2.

[0083] Compared to traditional FPGA-based PCIe system testing, this embodiment simplifies the PCIe RP and EP testing process. By traversing PCIe functions in an automated manner and simultaneously testing both the RP and EP, this reduces labor and equipment costs while also improving the real-time and consistency of testing. This approach allows for faster discovery and remediation of potential issues, shortening time to market and improving overall product quality.

[0084] Reference Figure 4 , provides a PCIe testing method for an embodiment of the present application, including:

[0085] Obtain connection status information, and if the connection status information indicates a successful connection, send test data to the PCIe control component;

[0086] Acquire first completion mark information, perform a first expectation analysis on the first completion mark information, and acquire second completion mark information if the first analysis result obtained by the analysis is consistent with the expectation;

[0087] A second expected analysis is performed on the second completion mark information to obtain a second analysis result reflecting the RP and EP test conditions.

[0088] An embodiment of the present application provides a test terminal device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the PCIe test method as described above.

[0089] An embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the aforementioned PCIe test method when run.

[0090] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and products can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0091] In several embodiments provided in this application, it should be understood that the disclosed methods, systems, devices, and program products may be implemented in other ways.

[0092] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0093] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe test system, characterized in that: include: A PCIe control component, used to obtain test data of the test terminal component, parse the test data to obtain first TLP message information and second TLP message information, perform a first test operation according to the first TLP message information, and obtain first completion flag information; A PCIe device-side component, used to obtain second TLP message information of the PCIe control component, perform a second test operation according to the second TLP message information, and obtain second completion flag information; The test terminal component is used to obtain connection status information, and when the connection status information indicates that the connection is successful, send test data to the PCIe control component; Acquire first completion mark information, perform a first expectation analysis on the first completion mark information, and acquire second completion mark information when the first analysis result obtained by the analysis is in line with expectations; A second expected analysis is performed on the second completion mark information to obtain a second analysis result reflecting the RP and EP test conditions.

2. The PCIe test system according to claim 1, characterized in that: The PCIe control component includes: The serial port analysis module is used to analyze the test data according to the serial port protocol to obtain the valid serial port information; The instruction conversion module is used to control the reading and writing of TLP according to the internally defined user register to obtain instruction information.

3. The PCIe test system according to claim 2, characterized in that: The PCIe control component also includes: The RP TLP sending processing module is used to send the corresponding first TLP message information and second TLP message information to the RP controller according to the instruction information; The RP controller is used to send the second TLP message information to the opposite EP device and obtain the processing status information of the opposite EP device.

4. The PCIe test system according to claim 3, characterized in that: The PCIe control component also includes: The RP TLP receiving processing module is used to obtain processing status information and obtain first completion flag information according to the processing status information.

5. The PCIe test system according to claim 1, characterized in that: The PCIe device-side components include: The EP TLP sending and receiving processing module is used to obtain the second TLP message information of the EP controller, perform a parsing operation on the second TLP message information, and obtain the second completion flag information in the parsing process, wherein the second completion flag information includes the CPL message information and the CPLD message information; The EP controller is used to obtain the second TLP message information of the PCIe control component, transmit the second TLP message information to the EPTLP sending and receiving processing module, and send the received CPL message information and CPLD message information to the opposite RP device.

6. The PCIe test system according to claim 1, characterized in that: Also includes: The clock frequency division module is used to obtain the 25MHz system clock signal and construct the serial port processing clock and user clock for data processing according to the 25MHz system clock signal.

7. The PCIe test system according to claim 1, characterized in that: The PCIe control component also includes: Clock configuration module, used to initialize and configure the clock chip.

8. A PCIe testing method, characterized in that: include: Obtain connection status information, and if the connection status information indicates that the connection is successful, send test data to the PCIe control component; Acquire first completion mark information, perform a first expectation analysis on the first completion mark information, and acquire second completion mark information when the first analysis result obtained by the analysis is in line with expectations; A second expected analysis is performed on the second completion mark information to obtain a second analysis result reflecting the RP and EP test conditions.

9. A test terminal device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the PCIe test method as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the PCIe test method of claim 8 when executed.

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