Device sample preparation method for tellurium-cadmium-mercury Hall test and Hall device test method
By performing two photolithography and corrosion treatments on the surface of mercury cadmium tellurium chips, growing metal electrodes and preparing Hall rod structure devices, the problems of poor accuracy and low efficiency of Hall tests under traditional methods are solved, and high accuracy and high efficiency are achieved Hall test.
Patent Information
- Application Number
- CN202411540124.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-21
AI Technical Summary
Traditional device preparation methods for mercury cadmium tellurium Hall test lead to poor test accuracy and low test efficiency, large test errors caused by metal contact size and position, low test signals, many test steps and long time.
A device sample preparation method is adopted, including performing a photolithography on the surface of a mercury cadmium tellurium chip, etching the passivation layer and a mercury tellurium layer, and preparing the mesa structure of the Hall rod; then performing a second photolithography and etching the passivation layer. , grow metal electrodes and finally obtain Hall rod structure devices.
Hall devices prepared by this method can perform Hall resistance and longitudinal resistance tests simultaneously. There are few test steps, short time, high efficiency, small test errors caused by metal contact size and position, high test accuracy and sensitivity, and can accurately characterize cadmium tellurium tellurium. Carrier-electric transport characteristics of mercury materials.
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Figure CN119497567A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of infrared detectors, and in particular relates to a device sample preparation method for mercury cadmium telluride Hall test and a Hall device test method. Background Art
[0002] In order to prepare high-quality infrared detection device materials, Hall tests are required to utilize the Hall effect to accurately characterize the electrical transport characteristics of carriers, thereby optimizing the carrier concentration and mobility of various conductive types in mercury cadmium telluride materials, reducing dark current and improving the performance of infrared detection devices. Therefore, the preparation of Hall devices for Hall tests is particularly critical.
[0003] The traditional device preparation method for HgCdTe Hall test is mostly the chip four-corner lead welding method, that is, the passivation layer is removed from the four corners of the chip, and then the wires are welded as electrodes, and the Hall characteristics of the device are tested through four Hall electrodes. However, the Hall device prepared by this method has a simple shape, resulting in large test errors caused by the size and position of the metal contact, low test signals, poor test sensitivity and test accuracy; the longitudinal resistance and Hall resistance need to be tested separately, with many test steps and long test time. Summary of the invention
[0004] The embodiments of the present application provide a device sample preparation method for mercury cadmium telluride Hall testing and a Hall device testing method, which are used to at least solve the problems of poor testing accuracy and low testing efficiency of Hall devices prepared by traditional preparation methods.
[0005] In a first aspect, an embodiment of the present application provides a device sample preparation method for mercury cadmium telluride Hall test, comprising:
[0006] Coating a photoresist on the surface of the pre-treated mercury cadmium telluride chip, wherein the pre-treated mercury cadmium telluride chip comprises a passivation layer and a P-type mercury cadmium telluride layer;
[0007] After the photoresist is cured, the HgCdTe chip is subjected to the first photolithography to obtain a target photolithography pattern;
[0008] The passivation layer and the P-type HgCdTe layer which are not protected by the photoresist in the target photolithography pattern are etched away to obtain the mesa structure of the Hall bar;
[0009] Removing the photoresist from the surface of the mercury cadmium telluride chip;
[0010] Re-coating photoresist on the surface of the mercury cadmium telluride chip, and performing a second photolithography on the mercury cadmium telluride chip;
[0011] The passivation layer on the surface of the mercury-cadmium chip that is not protected by the photoresist is corroded away;
[0012] Growing metal electrodes on the surface of the mercury cadmium telluride chip;
[0013] The surface of the mercury cadmium telluride chip is sliced to obtain a plurality of Hall devices.
[0014] In a second aspect, an embodiment of the present application provides a method for testing a Hall device, wherein the method is applied to a Hall device prepared by the device sample preparation method for mercury cadmium telluride Hall testing as described in any embodiment of the first aspect;
[0015] The test method includes:
[0016] The Hall device is welded by packaging, and a metal wire is led out from a target area of the Hall device to be welded to a sample holder, wherein the target area is a metal area of the Hall device that needs to be electrically led out;
[0017] A Hall test is performed on the Hall device using a sample holder to obtain test data.
[0018] The device sample preparation method and Hall device testing method for HgCdTe Hall test in the embodiment of the present application mainly include one-time photolithography on the surface of HgCdTe chip, etching the passivation layer and HgCdTe layer, and preparing HgCdTe into the shape of Hall bar; two-time photolithography on the surface of HgCdTe chip, etching the passivation layer, exposing the surface of HgCdTe without passivation layer, growing metal electrode, and finally obtaining Hall bar structure device. The structure device prepared by this method can simultaneously perform Hall resistance and longitudinal resistance tests, with fewer test steps, short test time and high test efficiency; and the structure device prepared by this method has precise design dimensions, so the test error caused by metal contact size and position is small, the test accuracy and test sensitivity are high, and the carrier electrical transport characteristics of HgCdTe material such as carrier concentration, carrier mobility, and Hall coefficient can be obtained more accurately. Thereby optimizing the device process and improving the detector performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0020] Figure 1 It is a flow chart of a device sample preparation method for mercury cadmium telluride Hall test provided in an embodiment of the present application;
[0021] Figure 2 is a top view of a Hall device provided in an embodiment of the present application;
[0022] Figure 3 It is a flow chart of another device sample preparation method for mercury cadmium telluride Hall test provided in an embodiment of the present application;
[0023] Figure 4 It is a flow chart of a Hall device testing method provided in an embodiment of the present application;
[0024] Figure 5 It is a schematic diagram of an exemplary Hall bar package lead provided in an embodiment of the present application. DETAILED DESCRIPTION
[0025] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.
[0026] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0027] As a direct bandgap semiconductor material, the pseudo-binary compound HgCdTe has a high light absorption coefficient and carrier mobility. The bandgap width is adjustable in the range of 0-1.5eV, and the response range can cover the entire infrared band of short wave (1-3μm), medium wave (3-6μm), long wave (8-12μm) and very long wave (12-25μm). It is widely used in various high-sensitivity infrared detection devices and is one of the most ideal infrared detector materials. With the development of infrared detector technology, high-performance infrared detection devices such as ultra-large-scale staring, dual-color / multi-color, and intelligent types have put forward higher requirements for the preparation of materials. In order to prepare high-quality HgCdTe pn junction materials, Hall tests are required to accurately characterize the electrical transport characteristics of carriers using the Hall effect, thereby optimizing the carrier concentration and mobility of various conductive types in HgCdTe materials, reducing dark current, and improving the performance of infrared detection devices. Therefore, the preparation of Hall devices for Hall tests is particularly critical.
[0028] The van der Pauw method is a technique commonly used to measure the resistivity and Hall coefficient of a sample. The van der Pauw method uses a four-point probe placed around the perimeter of the sample, which provides the average resistivity of the sample, as opposed to a linear four-point probe, while the linear array provides the resistivity in the sensing direction.
[0029] The traditional device sample preparation method for HgCdTe Hall test is mostly the chip four-corner lead welding method, that is, when preparing the traditional HgCdTe Hall device, the passivation layer is removed from the four corners of the chip, and then the wires are welded at the HgCdTe layer at the four corners of the chip as electrodes, and then the Hall characteristics of the device are tested using the Van der Pauw method through four Hall electrodes. However, the Hall device prepared by this method has a simple shape, resulting in large test errors caused by the size and position of the metal contact; the longitudinal resistance and Hall resistance need to be tested separately, with many test steps and long test time; and the Hall device prepared by the traditional preparation method has a low test signal, poor test sensitivity and test accuracy. It is impossible to accurately characterize the carrier transport characteristics, carrier concentration and mobility of the HgCdTe pn junction material, and it is impossible to develop high-performance infrared detectors.
[0030] In order to solve the problems of the related art, the embodiments of the present application provide a device sample preparation method and a Hall device testing method for mercury cadmium telluride Hall testing. The prepared structural device can effectively improve the test efficiency and test accuracy of the mercury cadmium telluride Hall device testing.
[0031] The device sample preparation method for mercury cadmium telluride Hall test provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios.
[0032] refer to Figure 1 , is a schematic flow chart of a device sample preparation method for HgCdTe Hall test according to an embodiment of the present application. Figure 1 As shown, the device sample preparation method for mercury cadmium telluride Hall test may specifically include the following steps:
[0033] S101, coating a photoresist on the surface of the pretreated mercury cadmium telluride chip, wherein the pretreated mercury cadmium telluride chip comprises a passivation layer and a P-type mercury cadmium telluride layer;
[0034] S102, after the photoresist is cured, performing a first photolithography on the mercury cadmium telluride chip to obtain a target photolithography pattern;
[0035] S103, etching away the passivation layer and the P-type mercury cadmium telluride layer that are not protected by the photoresist in the target photolithography pattern to obtain a mesa structure of the Hall bar;
[0036] S104, removing the photoresist on the surface of the mercury cadmium telluride chip;
[0037] S105, re-coating photoresist on the surface of the mercury cadmium telluride chip, and performing a second photolithography on the mercury cadmium telluride chip;
[0038] S106, etching away the passivation layer on the surface of the mercury-cadmium chip that is not protected by the photoresist;
[0039] S107, growing a metal electrode on the surface of the mercury cadmium telluride chip;
[0040] S108, slicing the surface of the mercury cadmium telluride chip to obtain a plurality of Hall devices.
[0041] Therefore, the structure device prepared by the method is a Hall bar structure device, which can simultaneously perform Hall resistance and longitudinal resistance tests, with fewer test steps, shorter test time, and higher test efficiency; and the structure device prepared by the method has precise design dimensions, so the test error caused by the metal contact size and position is small, the test accuracy and test sensitivity are high, and the carrier electrical transport characteristics of the mercury cadmium telluride material, such as carrier concentration, carrier mobility, and Hall coefficient, can be obtained more accurately. This enables the optimization of device technology and improves detector performance.
[0042] The specific implementation methods of the above steps are introduced below.
[0043] In some embodiments, before S101, organic matter on the surface of the mercury cadmium telluride chip is removed; a passivation layer is grown on the mercury cadmium telluride chip to obtain a mercury cadmium telluride chip with a passivation layer; the mercury cadmium telluride chip with the passivation layer is heat-treated to form a P-type mercury cadmium telluride layer to obtain a pre-treated mercury cadmium telluride chip.
[0044] In specific implementation, the mercury cadmium telluride chip can be corroded by using a corrosive liquid to expose a new mercury cadmium telluride surface, remove organic matter on the surface of the mercury cadmium telluride chip, and complete the surface pretreatment of the mercury cadmium telluride chip.
[0045] In a specific implementation, the mercury cadmium telluride chip with the passivation layer can be placed in an annealing furnace and subjected to high-temperature annealing in a nitrogen atmosphere to achieve a heat treatment process.
[0046] Optionally, the grown passivation layer is a cadmium telluride film layer (CdTe film layer). Specific implementation methods for growing the passivation layer include, but are not limited to, magnetron sputtering, thermal evaporation, etc. This embodiment does not specifically limit this.
[0047] In some embodiments, in S102, 4 μm AZ6130 photoresist may be spin-coated on the chip surface. After the photoresist is cured, a contact exposure device is used to expose a preset area of the mercury cadmium telluride chip, and a development process is performed to obtain a target photolithography pattern.
[0048] In some embodiments, in S103, the exposed passivation layer and the HgCdTe layer in the target photolithography pattern are etched away using a HgCdTe etching solution, and it should be understood that the remaining portion will not react under the protection of the photoresist, thereby preparing a mesa structure of the Hall bar.
[0049] As an optional embodiment, in S107, the metal electrode includes Cr (chromium) metal and Au (gold) metal. The thickness of the Cr layer may be 50nm to 100nm, and the thickness of the Au layer may be 100nm to 700nm. In this way, the Cr layer, as a contact layer, can facilitate the connection of the Au layer, and the Au layer can play a conductive role.
[0050] In some embodiments, after S107 and before S108, the metal electrode of the mercury cadmium telluride chip is stripped to form an ohmic contact between the metal electrode and the mercury cadmium telluride film layer, and the photoresist on the surface of the mercury cadmium telluride chip is removed. Specifically, the chip can be immersed in acetone first, and then the chip can be placed on a cleaning table to perform metal stripping and remove the photoresist on the chip surface at the same time.
[0051] Figure 2 FIG. 4 shows a top view of the Hall device divided by S108. Figure 2 As shown, the Hall device obtained by the device sample preparation method for mercury cadmium telluride Hall test according to the embodiment of the present application is a Hall bar structure device, which realizes precise control of the shape and size of the sample.
[0052] In addition, the size and position of the Hall device prepared by this method are more accurate, the test accuracy is high, the test error is small, the test steps are few, the test time is short, and the test efficiency is high. This method is a sample preparation method for high-sensitivity HgCdTe Hall test, and the Hall bar structure device prepared by it can effectively improve the test efficiency and test accuracy of HgCdTe Hall test.
[0053] In another embodiment, the specific implementation method of preparing the Hall device can be referred to Figure 3 .
[0054] like Figure 3As shown, another device sample preparation method for mercury cadmium telluride Hall test provided by an embodiment of the present application may include the following steps: performing surface pretreatment on the mercury cadmium telluride chip to remove organic matter on the chip surface; growing a passivation layer on the mercury cadmium telluride chip; performing a heat treatment process on the mercury cadmium telluride chip with the passivation layer; coating photoresist on the surface of the mercury cadmium telluride chip and performing a first photolithography process; using a corrosive solution to corrode the passivation layer and the mercury cadmium telluride layer on the surface of the mercury cadmium telluride chip that are not protected by the photoresist; removing the photoresist on the surface of the mercury cadmium telluride chip; coating photoresist on the surface of the mercury cadmium telluride chip and performing a second photolithography process; using a corrosive solution to corrode the passivation layer on the surface of the mercury cadmium telluride chip that are not protected by the photoresist; growing electrodes on the surface of the mercury cadmium telluride chip; performing electrode stripping and chip surface photoresist removal processes on the surface of the mercury cadmium telluride chip; performing a slicing process on the surface of the mercury cadmium telluride chip to obtain multiple Hall devices.
[0055] That is to say, the device sample preparation method for HgCdTe Hall test mainly includes: pre-treating the surface of the HgCdTe chip; growing and annealing the passivation layer of the HgCdTe chip; performing a primary photolithography on the surface of the HgCdTe chip to etch away part of the passivation layer and HgCdTe, and preparing the HgCdTe into the shape of a Hall bar; performing a secondary photolithography on the surface of the HgCdTe chip to etch away part of the passivation layer to expose the HgCdTe surface without the passivation layer, and growing a metal electrode; and stripping the electrode on the surface of the HgCdTe chip to form an ohmic contact between the electrode and the HgCdTe film layer.
[0056] It can be understood that compared with the traditional preparation method of welding the four corner leads of the mercury cadmium telluride chip, that is, the preparation method of the Hall device with a Hall bar structure, this method can accurately control the shape and size of the sample and reduce the test error. Therefore, when performing the Hall test, the test steps can be shortened and the test efficiency can be improved. In addition, the Hall device test sensitivity and accuracy of this Hall bar structure are very high, and the electrical transport characteristics of the carrier can be accurately analyzed.
[0057] Furthermore, the present application also provides a method for testing a Hall device. It should be noted that the method for testing a Hall device can be applied to a Hall device prepared by the device sample preparation method for HgCdTe Hall testing in any of the above embodiments.
[0058] Figure 4 FIG. 2 is a flow chart showing a method for testing a Hall device according to an embodiment of the present application. Figure 4 As shown, the Hall device testing method may specifically include the following steps: S401 and S402.
[0059] S401, welding the Hall device by packaging, and drawing out metal wires in a target area of the Hall device to weld to a sample holder, wherein the target area is a metal area of the Hall device that needs to be electrically drawn out.
[0060] S402: Performing a Hall test on the Hall device using a sample holder to obtain test data.
[0061] refer to Figure 5 , is a schematic diagram of an exemplary Hall bar package lead. Figure 5 As shown in the lead positions, when current flows between metal lead positions 5-6, the Hall voltage between positions 2-3, the resistance voltage between positions 1-2, and the resistance voltage between positions 3-4 can be measured simultaneously.
[0062] Furthermore, the Hall resistance and longitudinal resistance can be obtained by calculation, and finally the carrier concentration and mobility spectrum can be obtained to complete the Hall test. That is, the test data at least includes: electrical parameters of the material such as Hall resistance, longitudinal resistance, carrier concentration and mobility spectrum.
[0063] In this way, by selecting a Hall bar structure device and using package welding, metal wires are welded to the sample holder in the metal area where electrical lead-out is required to perform Hall test on the mercury cadmium telluride chip. Compared with the traditional four-corner lead method, the test steps are fewer, so the test time can be shortened by at least half, effectively improving the test efficiency; and the test accuracy is high, and the electrical transport characteristics of carriers such as the carrier concentration, carrier mobility, and Hall coefficient of the mercury cadmium telluride material can be obtained more accurately. Ultimately, the device process can be optimized and the detector performance can be improved.
[0064] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0065] Reference to "embodiment" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments.
[0066] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "attached" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0067] In the embodiments of the present application, the same reference numerals represent the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width and other dimensions of various components in the embodiments of the present application shown in the drawings, as well as the overall thickness, length, width and other dimensions of the integrated device are only exemplary descriptions and should not constitute any limitation to the present application.
[0068] The term "plurality" used in the present application refers to two or more (including two).
[0069] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
[0070] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.
[0071] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.
Claims
1. A device sample preparation method for mercury cadmium telluride Hall test, characterized in that: include: Coating a photoresist on the surface of the pre-treated mercury cadmium telluride chip, wherein the pre-treated mercury cadmium telluride chip comprises a passivation layer and a P-type mercury cadmium telluride layer; After the photoresist is cured, the HgCdTe chip is subjected to the first photolithography to obtain a target photolithography pattern; The passivation layer and the P-type HgCdTe layer which are not protected by the photoresist in the target photolithography pattern are etched away to obtain the mesa structure of the Hall bar; Removing the photoresist from the surface of the mercury cadmium telluride chip; Re-coating photoresist on the surface of the mercury cadmium telluride chip, and performing a second photolithography on the mercury cadmium telluride chip; The passivation layer on the surface of the mercury-cadmium chip that is not protected by the photoresist is corroded away; Growing metal electrodes on the surface of the mercury cadmium telluride chip; The surface of the mercury cadmium telluride chip is sliced to obtain a plurality of Hall devices.
2. The method according to claim 1, characterized in that Before coating the photoresist on the pretreated surface of the mercury cadmium telluride chip, the method further comprises: Remove organic matter from the surface of HgCdTe chips; Growing a passivation layer on the mercury cadmium telluride chip to obtain a mercury cadmium telluride chip with a passivation layer; The HgCdTe chip with the passivation layer is heat-treated to form a P-type HgCdTe layer, thereby obtaining a pre-treated HgCdTe chip.
3. The method according to claim 2, characterized in that The step of thermally treating the mercury cadmium telluride chip with the passivation layer to form a P-type mercury cadmium telluride layer comprises: The HgCdTe chip with the passivation layer is placed in an annealing furnace and subjected to high temperature annealing in a nitrogen atmosphere.
4. The method according to claim 1, characterized in that: The first photolithography of the mercury cadmium telluride chip to obtain a target photolithography pattern includes: The contact exposure equipment is used to expose the preset area of the mercury cadmium telluride chip, and then the development process is performed to obtain the target photolithography pattern.
5. The method according to claim 1, characterized in that After growing the metal electrode on the surface of the mercury cadmium telluride chip and before slicing the surface of the mercury cadmium telluride chip, the method further comprises: Stripping the metal electrode of the mercury cadmium telluride chip so that the metal electrode forms an ohmic contact with the mercury cadmium telluride film layer; Remove the photoresist from the surface of the HgCdTe chip.
6. The method according to claim 1, characterized in that The passivation layer is a cadmium telluride film layer.
7. The method according to claim 1, characterized in that The metal electrodes include chromium metal and gold metal.
8. A Hall device testing method, characterized in that: The test method is applied to a Hall device prepared by a device sample preparation method for mercury cadmium telluride Hall test according to any one of claims 1 to 7; The test method includes: The Hall device is welded by packaging, and a metal wire is led out from a target area of the Hall device to be welded to a sample holder, wherein the target area is a metal area of the Hall device that needs to be electrically led out; A Hall test is performed on the Hall device using a sample holder to obtain test data.
9. The method according to claim 8, characterized in that The test data at least includes: Hall resistance, longitudinal resistance, carrier concentration and mobility spectrum.