Computing device and computing method

Abstract

The invention discloses computing equipment and a computing method. The computing device comprises a digital computing unit, an analog computing unit and a compensation unit, the analog computing unit comprises one or more first arrays, the digital computing unit comprises one or more second arrays, and one first array corresponds to one second array; wherein the analog calculation unit is used for determining a first error and a second error corresponding to one or more first arrays, the first error comprises a write-in error of each first array in one or more first arrays, and the second error comprises a calculation error of each first array in one or more first arrays; the compensation unit is used for fitting the first error and the second error to obtain an error compensation parameter and writing the error compensation parameter into one or more second arrays; and the digital calculation unit is used for performing error compensation on calculation results output by the one or more first arrays through the one or more second arrays.

Description

Technical Field

[0001] The present application relates to the technical field of Internet of Things, and in particular to a computing device and a computing method. Background Art

[0002] At present, the computing unit and storage unit of computing devices in related architectures are separated, and data is repeatedly transmitted between the central processing unit (CPU) and the storage unit (also called memory). This will generate a lot of power consumption and transmission delay, thereby limiting the performance of access-intensive applications such as artificial intelligence and big data.

[0003] As a new type of computing technology, storage-computing integration relies on the development of materials, devices, computing paradigms and architectures, and can use storage units to realize computing functions. In this way, zero distance between storage and computing can be achieved, thereby greatly improving computing power and computing energy efficiency. For storage-computing integration devices (which can be understood as devices where computing units and storage units are deployed together), it is mainly used for matrix multiplication and addition operations, and can be applied to application scenarios such as data retrieval, video differential super-resolution, and large model reasoning.

[0004] However, when using related storage and computing devices for calculations, the calculation results have the problem of low accuracy. Summary of the invention

[0005] To solve the related technical problems, the embodiments of the present application provide a computing device and a computing method.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] The embodiment of the present application provides a computing device, including: an analog computing unit, a digital computing unit and a compensation unit, wherein the analog computing unit includes one or more first arrays, the digital computing unit includes one or more second arrays, and one first array corresponds to one second array; wherein,

[0008] The simulation calculation unit is used to determine a first error and a second error corresponding to the one or more first arrays, wherein the first error includes a writing error of each first array in the one or more first arrays, and the second error includes a calculation error of each first array in the one or more first arrays;

[0009] The compensation unit is configured to fit the first error and the second error to obtain an error compensation parameter, and write the error compensation parameter into the one or more second arrays;

[0010] The digital calculation unit is used to perform error compensation on the calculation results output by the one or more first arrays through the one or more second arrays.

[0011] In the above computing device, the analog computing unit further includes: a read-write circuit; wherein,

[0012] The read / write circuit is used to write a first parameter into the one or more first arrays and read a second parameter from the one or more first arrays; and determine the first error using the first parameter and the second parameter.

[0013] In the above computing device, the analog computing unit further comprises: a verification circuit; wherein,

[0014] The verification circuit is used to compare the first error with a first threshold to obtain a comparison result;

[0015] The read-write circuit is used to retain the first parameter written this time when the comparison result indicates that the first error is less than or equal to the first threshold.

[0016] In the above computing device, the read-write circuit is further used to rewrite the first parameter into the one or more first arrays when the comparison result indicates that the first error is greater than the first threshold.

[0017] In the above computing device, the analog computing unit further includes: a read-write circuit; wherein,

[0018] The read / write circuit is used to input a third parameter into the one or more first arrays and obtain a first calculation result output by the one or more first arrays; and determine the second error using the first calculation result and the second calculation result, wherein the second calculation result includes a target calculation result of the one or more first arrays.

[0019] In the above-mentioned computing device, each of the one or more first arrays includes multiple analog units, and the read-write circuit is used to write the third parameter to the Mth column analog unit in the first array for each first array, to obtain a third calculation result output by the Mth column analog unit, where M is an integer greater than or equal to 1; and determine a third error using the third calculation result and the fourth calculation result, wherein the fourth calculation result includes the target calculation result of the Mth column analog unit, and the third error includes the calculation error of the Mth column analog unit.

[0020] In the above-mentioned computing device, each of the one or more second arrays includes multiple computing units, each simulation unit corresponds to multiple computing units, and the compensation unit is used to fit the first error and the third error to obtain a first error compensation parameter, and write the first error compensation parameter to the Nth column of computing units in the second array corresponding to the Mth column of simulation units, where N is an integer greater than or equal to 1.

[0021] In the above computing device, the read-write circuit is further used to re-write the third parameter into the Mth column of analog cells in the first array when the first error compensation parameter is greater than the second threshold.

[0022] In the above-mentioned computing device, the simulation computing unit is further used to determine a fifth computing result corresponding to the target parameter to be calculated through the one or more first arrays;

[0023] The digital calculation unit is further used to determine a sixth calculation result corresponding to the target parameter to be calculated through the one or more second arrays;

[0024] The compensation unit is further used to use the sixth calculation result to perform error compensation on the fifth calculation result to obtain a seventh calculation result.

[0025] The present application also provides a calculation method, which is applied to a computing device and includes:

[0026] The analog calculation unit of the computing device determines a first error and a second error corresponding to a plurality of first arrays, the analog calculation unit including the one or more first arrays, the first error including a written error of each first array in the plurality of first arrays, and the second error including a calculated error of each first array in the plurality of first arrays;

[0027] The compensation unit of the computing device fits the first error and the second error to obtain error compensation parameters, and writes the error compensation parameters into one or more second arrays, the digital computing unit of the computing device includes the one or more second arrays, and one first array corresponds to one second array;

[0028] The digital calculation unit performs error compensation on calculation results output by the one or more first arrays through the one or more second arrays.

[0029] The computing device and computing method provided in the embodiment of the present application, the analog computing unit determines the first error and the second error corresponding to one or more first arrays, the analog computing unit includes the one or more first arrays, the first error includes the write error of each first array in the one or more first arrays, and the second error includes the calculation error of each first array in the one or more first arrays; the compensation unit fits the first error and the second error to obtain the error compensation parameter, and writes the error compensation parameter to one or more second arrays, the digital computing unit includes the one or more second arrays, one first array corresponds to one second array; the digital computing unit performs error compensation on the calculation results output by the one or more first arrays through the one or more second arrays. The technical solution provided in the embodiment of the present application, the compensation unit fits the on-chip error (i.e., the write error and the calculation error) to obtain the device-level error, and the digital computing circuit compensates the on-chip error of the analog computing circuit, so that the accuracy of the calculation result output by the analog computing circuit can be improved, and at the same time, the writing accuracy requirement of the analog computing circuit can be reduced, thereby reducing the number of writes and extending the service life of the device, that is, realizing high-precision calculation based on the analog computing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of an analog computing circuit in the related art;

[0031] Figure 2 A schematic diagram of the working principle of a memristor;

[0032] Figure 3 A schematic diagram showing the change of the conductance value of a memristor over time;

[0033] Figure 4 This is a schematic diagram of the working principle of another memristor;

[0034] Figure 5 It is a structural schematic diagram of a calculation circuit in the related art;

[0035] Figure 6 This is a schematic diagram of the structure of the first computing device according to an embodiment of the present application;

[0036] Figure 7 This is a schematic diagram of the structure of a second computing device according to an embodiment of the present application;

[0037] Figure 8 This is a schematic diagram of the structure of a third computing device according to an embodiment of the present application;

[0038] Fig. 9 A schematic diagram of a digital-analog hybrid storage and computing integrated circuit is provided as an example for the application of this application;

[0039] Fig.10 A flow chart of a method for model deployment of a digital-analog hybrid storage and computing integrated circuit for the application example of this application;

[0040] Fig.11 A flow chart of a method for model training using a digital-analog hybrid storage and computing circuit in this application example;

[0041] Fig.12 A flowchart of a method for calculation by a computing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The present application is further described in detail below through the accompanying drawings and specific embodiments.

[0043] In the related art, according to the computing principle, the storage-computing integrated circuit corresponding to the storage-computing integrated device can be divided into analog computing circuits (also called analog storage-computing integrated circuits) and digital computing circuits (also called computing-storage-computing integrated circuits).

[0044] For analog computing circuits, such as Figure 1 As shown, non-volatile memory (NVM) (such as flash memory, resistive random access memory (RRAM), ferromagnetic random access memory (FRAM), phase change memory (PCM) or non-volatile random access memory (NRAM)) is usually used as a storage and calculation unit, which can realize multi-bit (English can be expressed as bit) storage and calculation. The analog computing circuit can realize multiplication and addition in the array with the help of Ohm's law and Kirchhoff's law, and realize signal conversion through peripheral analog-to-digital converter (ADC) or digital-to-analog conversion (DAC) devices to connect with other digital modules. Analog computing circuits have high storage density and low computing power consumption, but their computing accuracy is poor. In particular, new storage units such as memristors (such as RRAM, PCM, FRAM or NRAM) have write errors (which can be understood as the error between the written data and the stored data), which will affect the computing accuracy.

[0045] This is because: Memristor is a non-volatile resistive memory device, such as Figure 2As shown in Figure 1, by adjusting the pulse length and amplitude of the current and voltage applied to the memristor, the resistance of the memristor can be changed. Memristors are passive electronic components that allow a certain amount of current to pass safely and can also store the previous resistance value of the device after power is turned off. When using memristors to train neural networks, such as Figure 3 As shown, the conductance value of the memristor is usually used to represent the network parameters. Since the conductance value of the device is an analog quantity, the conductance value may drift over time, thus causing data writing errors (also called storage errors).

[0046] The working principle of memristor is as follows: memristor is usually integrated in high density by means of crossbar array (also called resistive switching array). Figure 4 As shown, when a column voltage vector is input at one end of the memristor cross array, the output current vector at the other end is the product of the column voltage vector and the memristor conductance matrix. In other words, based on Ohm's law and Kirchhoff's voltage law, the memristor array can complete the multiplication and accumulation of vectors (also called vectors) and matrices within one cycle, and store the multiplication factors directly in the memristor array. In this way, no separate storage unit is required, thereby bypassing the performance bottleneck (such as the von Neumann bottleneck); in addition, this core unit based on the memristor array multiplication and accumulation operation has higher computing energy efficiency, which is of great significance for intelligent processing tasks with a large number of multiplication and accumulation operations.

[0047] In addition, analog computing circuits may also have analog computing errors, which may include unit difference errors, line resistance errors, etc. Among them, line resistance error refers to the existence of line resistance on the bit line of the storage and computing integrated array, resulting in voltage drop (which can be expressed as IR drop in English), thereby causing the current and to decrease; unit difference error refers to the internal parameter difference between storage and computing integrated devices due to the manufacturing process, which may result in different outputs under the same input and the same storage. Analog computing errors cannot be measured, so it is difficult to perform accurate compensation at the device level through algorithms.

[0048] For digital computing circuits, such as Figure 5 As shown, single-bit memories such as static random-access memory (SRAM) and magnetic random-access memory (MRAM) are usually used as storage and calculation units. With the help of peripheral digital multipliers and adder trees, multiplication and addition can be realized, and other digital units can be directly connected. The calculation accuracy loss of digital calculation circuits is relatively low, but there are problems such as high device cost, low storage and calculation density, large peripheral circuit area, and high calculation power consumption.

[0049] From the above description, it can be seen that due to limitations of peripheral circuits, device errors or storage density, analog computing circuits and digital computing circuits cannot achieve a balance between power consumption, accuracy, area and cost (PPAC).

[0050] In order to solve the above problems, a related implementation scheme is to use a mixed method of digital computing circuits and analog computing circuits to achieve complementary advantages and disadvantages of the two circuits; specifically, the operands stored in the storage and calculation unit are split into high-order and low-order; wherein the high-order calculation is performed by the digital computing circuit, and the low-order calculation is performed by the analog computing circuit, so as to reduce the impact of the analog computing circuit error on the result. However, the above scheme still has analog computing errors, which will affect the calculation accuracy, thereby limiting the application scenarios.

[0051] Another related implementation scheme is to separate the calibration and calculation, and divide the readout circuit in the integrated storage and computing chip into a calibration readout circuit and a calculation readout circuit; wherein the calibration readout circuit is used to calibrate the write weight, and the calculation readout circuit is used to read the matrix-vector multiplication result of the integrated storage and computing chip. However, the calibration readout circuit is only used for error control in the parameter writing process, and does not take into account the precision loss generated in the actual calculation process, that is, the calculation error.

[0052] To summarize, the relevant implementation scheme can reduce the writing error caused by the non-ideal characteristics of the storage and computing circuit by splitting the high and low bits or adding calibration units (it can also be understood as calibrating the parameter writing process). However, it does not take into account the simulation calculation error existing in the calculation and training process, which will affect the accuracy of the calculation results.

[0053] Based on this, in various embodiments of the present application, on-chip error compensation is performed on the analog computing circuit through the digital computing circuit, so that the writing error of the parameter can be compensated. At the same time, the analog computing error can also be compensated, thereby further improving the accuracy of the analog computing circuit and giving full play to the advantages of low power consumption and high density of the storage and computing integrated device.

[0054] The present application embodiment provides a computing device, such as Figure 6 As shown, it includes: an analog calculation unit 601, a digital calculation unit 603 and a compensation unit 602, the analog calculation unit 601 includes one or more first arrays 6011, the digital calculation unit 603 includes one or more second arrays, and one first array 6011 corresponds to one second array; wherein,

[0055] The simulation calculation unit 601 is used to determine a first error and a second error corresponding to the one or more first arrays 6011, wherein the first error includes a writing error of each first array in the one or more first arrays 6011, and the second error includes a calculation error of each first array in the one or more first arrays 6011;

[0056] The compensation unit 602 is used to fit the first error and the second error to obtain an error compensation parameter, and write the error compensation parameter into the one or more second arrays;

[0057] The digital calculation unit 603 is used to perform error compensation on the calculation results output by the one or more first arrays 6011 through the one or more second arrays.

[0058] In actual application, the computing device can be called a storage-computing integrated circuit, a digital-analog hybrid storage-computing integrated circuit, a storage-computing integrated computing chip or a storage-computing integrated computing array, etc., and at least includes an analog computing unit 601, a digital computing unit 603 and a compensation unit 602; wherein the analog computing unit 601 can be called an analog storage-computing module (ACIM), an analog computing module, an analog storage-computing unit, etc., and the present application does not limit the name of the analog computing unit 601, as long as its function is realized; the digital computing unit 602 can be called a digital storage-computing module (DCIM), a digital computing module, a digital storage-computing unit, etc., and the present application does not limit the name of the digital computing unit 602, as long as its function is realized.

[0059] In addition, the first array 6011 can be called a storage array, a memristor array or an analog computing memristor array, etc., and at least has a computing function, can perform multiplication and addition operations on input parameters, and output corresponding calculation results; the second array can be called a storage array, a digital storage array, etc., and at least has a storage function, and can store the error compensation parameters; wherein, there is a one-to-one correspondence between the first array 6011 and the second array, that is, different first arrays 6011 correspond to different second arrays.

[0060] In actual application, in order to determine the first error, a target parameter may be written (also referred to as burned) into the one or more first arrays 6011, and the actually written first parameter may be read from the one or more first arrays 6011, thereby obtaining the first error.

[0061] Specifically, in one embodiment, if Figure 7 As shown, the analog computing unit 601 may further include: a read-write circuit 6012; wherein,

[0062] The read / write circuit 6012 is used to write the first parameter into the one or more first arrays 6011 and read the second parameter from the one or more first arrays 6011; and determine the first error using the first parameter and the second parameter.

[0063] Among them, the first parameter can be understood as the target parameter to be written into the first array 6011 (also referred to as the target write parameter, parameter matrix, etc.), and the first parameter can be pre-configured as needed, which is not limited in this embodiment of the present application; the second parameter can be understood as the first parameter read from the first array 6011.

[0064] In actual application, after the read / write circuit 6012 obtains the pre-configured first parameter, it writes the first parameter into the one or more first arrays 6011. The first parameter can be represented in the form of a matrix. The form of the first parameter in the embodiment of the present application is not limited. After writing, the read / write circuit 6012 can read the written first parameter from the one or more first arrays 6011 to obtain the second parameter, and obtain the first error by performing a difference process on the first parameter and the second parameter. The first error can be expressed as: E W =W 0 -W 1 ; Among them, W 0 Represented as the first parameter, W 1 Expressed as the second parameter, E W It is indicated as the first error.

[0065] It should be noted that the second parameter may refer to the first parameter converted by ADC and stored in one or more first arrays 6011; that is, the analog calculation unit 601 may also include an ADC, and the ADC is used to perform analog-to-digital conversion on the first parameter to obtain the first parameter after analog-to-digital conversion, so that the first parameter can be stored in a numerical form.

[0066] Here, in order to extend the service life of the analog calculation unit 601, a corresponding compensation range can be pre-set for the first error, and the first error and the compensation range can be compared to reduce the number of parameter writing times by allowing the first error within the compensation range, thereby ensuring the life of the device.

[0067] Specifically, in one embodiment, if Figure 8 As shown, the analog calculation unit 601 may further include: a verification circuit 6013; wherein,

[0068] The verification circuit 6013 is used to compare the first error with a first threshold to obtain a comparison result;

[0069] The read-write circuit 6012 is configured to retain the first parameter written this time when the comparison result indicates that the first error is less than or equal to the first threshold.

[0070] Among them, the first threshold can be understood as a compensation range associated with the first error, that is, a range in which error compensation can be performed by the one or more second arrays. The value of the first threshold can be pre-configured as needed, and the embodiment of the present application does not limit this.

[0071] In actual application, after the verification circuit 6013 obtains the pre-configured first threshold, it can compare the first threshold and the first error; when the first error is less than or equal to the first threshold, the verification circuit 6013 can determine that the first error written this time is within the allowable range. In this case, the read-write circuit 6012 can retain the first parameter written this time.

[0072] In addition, when the first error is greater than the first threshold, the verification circuit 6013 can determine that the first error written this time exceeds the allowable range; in this case, the read-write circuit 6012 needs to rewrite the parameters.

[0073] Based on this, in one embodiment, the read / write circuit 6012 is further configured to rewrite the first parameter into the one or more first arrays 6011 when the comparison result indicates that the first error is greater than the first threshold.

[0074] In actual application, after completing the rewriting of the first parameter, the read-write circuit 6012 can reread the second parameter from the one or more first arrays 6011, and use the rewritten first parameter and second parameter to re-determine the first error; then, the verification circuit 6013 compares the re-determined first error with the first threshold until the re-determined first error is less than or equal to the first threshold.

[0075] It should be noted that, since the parameters (also referred to as weights) of the one or more first arrays 6011 may change over time, causing the first parameters retained in the first array to change (which can also be understood as a weight shift), the verification circuit 6013 may periodically detect the one or more first arrays 6011 while retaining the written first parameters, and calculate the first error; when the calculated first error is greater than the first threshold, the read-write circuit 6012 may rewrite the first parameter to the one or more first arrays 6011, so that the first error is within an allowable range.

[0076] Here, for the second error, a target data set may be output to the one or more first arrays 6011 for calculation, and the output calculation result may be compared with the target calculation result corresponding to the target data set, thereby obtaining the second error.

[0077] Based on this, in one embodiment, the read-write circuit 6012 is also used to input a third parameter into the one or more first arrays 6011, and obtain a first calculation result output by the one or more first arrays 6011; and determine the second error using the first calculation result and the second calculation result, wherein the second calculation result includes a target calculation result of the one or more first arrays 6011.

[0078] The third parameter may include a target parameter and a corresponding target calculation result, and the target calculation result may be understood as an expected calculation result obtained by calculating the target parameter by the one or more first arrays 6011 .

[0079] In actual application, in the process of obtaining the first calculation result, the read-write circuit 6012 can use a column-by-column calculation method to determine the calculation result corresponding to each column in each first array 6011, thereby obtaining the first calculation result; wherein, each first array 6011 can include multiple analog units, that is, the first array 6011 is composed of multiple analog units, and the analog unit can include FLASH, RRAM, FRAM, PCM, NRAM and other devices, and the analog unit can be called an analog storage and calculation unit, a storage and calculation unit or a basic unit, etc., and the embodiment of the present application does not limit this.

[0080] Specifically, in one embodiment, the read-write circuit 6012 is used to write the third parameter to the Mth column analog unit in the first array 6011 for each first array 6011, to obtain a third calculation result output by the Mth column analog unit, where M is an integer greater than or equal to 1; and to determine a third error using the third calculation result and the fourth calculation result, wherein the fourth calculation result includes a target calculation result of the Mth column analog unit, and the third error includes a calculation error of the Mth column analog unit.

[0081] In actual application, the read-write circuit 6012 can input the target parameter included in the third parameter into the Mth column analog unit for multiplication and addition calculation to obtain the third calculation result (also called the multiplication and addition calculation result); after obtaining the fourth calculation result from the target calculation result included in the third parameter, the read-write circuit 6012 can compare the third calculation result with the fourth calculation result to obtain the third error.

[0082] It should be noted that the principle of multiplication and addition calculation is: in the process of performing simulation calculation in the Mth column simulation unit, the input target parameter is usually converted into a voltage value, and the parameter data of each simulation unit is a conductance value (which can be expressed as P M ); Apply Ohm's law and Kirchhoff's law, and obtain the current value corresponding to the analog unit through the voltage and conductance values ​​(current = voltage * conductance); by aggregating the output current of each analog unit in the Mth column of analog units, the final current can be obtained.

[0083] For example, assuming that the Mth column of analog cells includes n analog cells, the read / write circuit 6012 sets the target parameter (which can be expressed as I={I 1 ,I 2 ,I 3 ,...,I n}) is input to the Mth column simulation unit for multiplication and addition calculation to obtain the third calculation result (which can be expressed as Am ); By the third calculation result and the fourth calculation result (which can be expressed as O m' ) is processed by subtraction to obtain the third error (which can be expressed as E c =|O m' -O Am |).

[0084] In actual application, for the Mth column analog unit, the read / write circuit 6012 can repeatedly write the target parameter to the Mth column analog unit S times, and obtain S third errors (which can also be understood as a third error list with a length of S, which can be expressed as ψ c ={E c1 ,E c2 ,....,E cS}), S is an integer greater than 1, and the value of S can be set as needed, which is not limited in the embodiment of the present application. This is because: during the analog calculation of the M-th column analog unit, there may be noise, which leads to calculation errors. Therefore, the read-write circuit 6012 can obtain multiple third errors by repeated input, so as to accurately compensate based on the obtained third errors.

[0085] Here, in the case where the third error is obtained by calculating column by column, the compensation unit 602 may compensate the analog units included in the first array 6011 column by column.

[0086] Specifically, in one embodiment, each of the one or more second arrays includes multiple computing units, each simulation unit corresponds to multiple computing units, and the compensation unit 602 is used to fit the first error and the third error to obtain a first error compensation parameter, and write the first error compensation parameter to the Nth column of computing units in the second array corresponding to the Mth column of simulation units, where N is an integer greater than or equal to 1.

[0087] In actual application, each second array may include multiple computing units, that is, the second array is composed of multiple computing units, and the computing units may be called storage units, digital storage units, etc., which are not limited in the present embodiment. In addition, each analog unit corresponds to multiple computing units, that is, for each analog unit, the second array can allocate multiple computing units to compensate the analog unit, for example, X computing units are allocated to each analog unit, and the value of X can be determined according to the first threshold value (which can be expressed as k) (which can be expressed as k=2 X -1)

[0088] In actual application, in the process of performing column-by-column compensation, the compensation unit 602 may fit the target parameter, the first error and the third error through a linear function to obtain the first error compensation parameter, and the first error compensation parameter may include the error compensation parameter corresponding to each simulation unit in the Mth column of simulation units; wherein, in the case where the Mth column of simulation units includes n simulation units, the first error compensation parameter may be expressed as {k 0 ,k m1 ,k m2 ,...k mn}.

[0089] Exemplarily, by inputting the target parameter, the first error and the third error list into the compensation unit 602, the compensation unit 602 can fit the calculated error and the write error distribution of the Mth column of analog cells, and based on the fitting result (which can be expressed as F CE (I) = k 0 +k m1 I 1 +k m2 I 2 +...+k mn I n ) obtains the first error compensation parameter.

[0090] Here, after obtaining the first error compensation parameter, the compensation unit 602 may compare the first error compensation parameter with a second threshold value to determine whether the calculation error and the writing error exceed the range that the second array can compensate for; wherein the value of the second threshold value may be set as required, and the first threshold value and the second threshold value may be the same or different, which is not limited in this embodiment of the present application.

[0091] Specifically, in one embodiment, the read / write circuit 6012 is further configured to re-write the third parameter into the Mth column of analog cells in the first array 6011 when the first error compensation parameter is greater than a second threshold.

[0092] In actual application, when there are one or more error compensation parameters in the first error compensation parameters that are greater than or equal to the second threshold value, the read-write circuit 6012 can rewrite the first parameters to the one or more first arrays 6011 to adjust the first error; in addition, the read-write circuit 6012 can also re-input the target parameters into the Mth column analog unit to adjust the third error.

[0093] In actual application, when the error compensation parameters included in the first error compensation parameters are all smaller than the first threshold, the compensation unit 602 may write the first error compensation parameters into the Nth column calculation unit.

[0094] In actual application, after completing the calculation of the error compensation parameters corresponding to each first array in the one or more first arrays 6011 (which can also be understood as completing the deployment of the computing device), the target parameters to be calculated can be input into the analog computing unit 601, and the corresponding calculation results can be obtained through the digital computing unit 603 and the digital computing unit 603.

[0095] Based on this, in one embodiment, the simulation calculation unit 601 is further used to determine a fifth calculation result corresponding to the target parameter to be calculated through the one or more first arrays 6011;

[0096] The digital calculation unit 603 is further used to determine a sixth calculation result corresponding to the target parameter to be calculated through the one or more second arrays;

[0097] The compensation unit 602 is further configured to use the sixth calculation result to perform error compensation on the fifth calculation result to obtain a seventh calculation result.

[0098] In actual application, after receiving the target parameter to be calculated, the simulation calculation unit 601 can input the target parameter to be calculated into the one or more first arrays 6011 for calculation to obtain the fifth calculation result, and the fifth calculation result can include the calculation results of multiple columns of simulation units corresponding to each first array 6011; that is, the fifth calculation result is obtained by multiplying and adding the first parameters written in the one or more first arrays 6011 and the target parameter to be calculated.

[0099] Exemplarily, the analog calculation unit 601 may adopt a column-by-column calculation method to write the target parameter to be calculated into each column of the analog calculation units in the first array 6011 in sequence to obtain the calculation result corresponding to each column of the analog calculation units, thereby obtaining the fifth calculation result.

[0100] In addition, the digital calculation unit 603 can input the target parameter to be calculated into the one or more second arrays for column-by-column calculation to obtain the sixth calculation result, and the sixth calculation result can include the calculation results of multiple columns of calculation units corresponding to each second array; specifically, the digital calculation unit 603 can also include a selection circuit, an accumulator, and a shared multiplier and an addition tree; wherein the selection circuit is used to select a column of calculation units from the one or more second arrays in turn, and input the selected column of calculation units into the shared multiplier and the addition tree; the shared multiplier and the addition tree are used to obtain the calculation result corresponding to the selected column of calculation units by performing multiplication and addition calculations on the target parameter to be calculated and the first error compensation parameter stored in the selected column of calculation units; the accumulator is used to perform accumulation processing on the calculation results corresponding to the selected column of calculation units to obtain the calculation result after accumulation processing.

[0101] It should be noted that, since the calculation frequency of the digital calculation unit 603 (e.g., 10 times per minute) is usually higher than that of the analog calculation unit 601 (e.g., 1 time per minute), the one or more second arrays can adopt a method of sharing multipliers and adder trees in multiple columns (which can be understood as multiple columns of calculation units sharing a set of calculation logic devices) to reduce the area and power consumption corresponding to the digital calculation unit 603. This is because: if the method of sharing multipliers and adder trees in multiple columns is not adopted, after the calculation result corresponding to a column of calculation units is obtained by sharing multipliers and adder trees, it is necessary to wait until the corresponding column of analog units obtains the corresponding calculation result, which will cause a waste of resources. Therefore, in the calculation process of a column of analog units, the selection circuit can select multiple columns of calculation units (e.g., 10 columns of calculation units) at the same time, and input them into the shared multipliers and adder trees in sequence, so as to obtain the calculation results corresponding to the multiple columns of calculation units through the shared multipliers and adder trees.

[0102] In actual application, after the compensation unit 602 obtains the fifth calculation result and the sixth calculation result, it can sum the fifth calculation result and the sixth calculation result to obtain the seventh calculation result, and the seventh calculation result can be understood as the final calculation result after error compensation; wherein, the fifth calculation result can be the calculation result after ADC conversion processing, so that the compensation unit 602 can directly sum the fifth calculation result and the sixth calculation result.

[0103] Exemplarily, assuming that the fifth calculation result is represented by Y A , the sixth calculation result is expressed as Y I , then, the seventh calculation result can be expressed as Y'=Y A +Y I ;

[0104] The computing device provided in the embodiment of the present application, the analog computing unit determines the first error and the second error corresponding to one or more first arrays, the analog computing unit includes the one or more first arrays, the first error includes the write error of each first array in the one or more first arrays, and the second error includes the calculation error of each first array in the one or more first arrays; the compensation unit fits the first error and the second error to obtain the error compensation parameter, and writes the error compensation parameter to one or more second arrays, the digital computing unit includes the one or more second arrays, one first array corresponds to one second array; the digital computing unit performs error compensation on the calculation results output by the one or more first arrays through the one or more second arrays. The technical solution provided in the embodiment of the present application, the compensation unit fits the on-chip error (i.e., the write error and the calculation error) to obtain the device-level error, and the digital computing circuit compensates the on-chip error of the analog computing circuit, so that the accuracy of the calculation result output by the analog computing circuit can be improved, and at the same time, the writing accuracy requirement of the analog computing circuit can be reduced, thereby reducing the number of writes and extending the service life of the device, that is, realizing high-precision calculation based on the analog computing circuit.

[0105] The present application is described in further detail below in conjunction with application examples.

[0106] Based on the advantages and disadvantages of digital storage and calculation circuits and analog storage and calculation circuits, the application example of this application proposes a digital-analog hybrid storage and calculation integrated circuit (i.e., the above-mentioned computing device); wherein, Fig. 9As shown, the core module of the digital-analog hybrid storage and computing integrated circuit includes an analog storage and computing module (i.e. the above-mentioned analog computing unit), a digital storage and computing module (i.e. the above-mentioned digital computing unit), and an error compensation module (i.e. the above-mentioned compensation unit); wherein the analog storage and computing unit at least includes multiple storage and computing arrays (i.e. the above-mentioned first array), a read-write circuit, a verification circuit, an ADC and a DAC, and each storage and computing array includes multiple storage and computing units (i.e. the above-mentioned analog unit); the digital storage and computing module at least includes multiple storage arrays (i.e. the above-mentioned second array), a shared multiplier and an adder tree, a selection circuit and an accumulator, one storage and computing array corresponds to one storage array, each storage and computing array includes multiple storage units (i.e. the above-mentioned computing unit), and the storage and computing array allocates multiple storage units to each storage and computing unit for error compensation; the error compensation module includes a data fitting unit and an output unit, the data fitting unit is used to calculate the error compensation parameters, and the output unit is used to integrate and output the results of the analog storage and computing array and the digital storage and computing array.

[0107] Specifically, in the process of model deployment using a hybrid analog-digital storage and computing circuit, Fig.10 As shown, the following steps are included:

[0108] Step 1001: Obtaining a write weight (ie, the first parameter mentioned above) and a compensation range (ie, the first threshold mentioned above);

[0109] Step 1002: writing the write weight into the simulation storage array;

[0110] Step 1003: After writing is completed, the writing error (i.e., the first error mentioned above) is obtained, and the device whose error exceeds the compensation range is re-programmed until the writing error is within the compensation range;

[0111] Here, the actual write weight is read from the simulated storage array, and the read write weight is compared with the written write weight to obtain the write error.

[0112] Step 1004: Obtain data (i.e., the third parameter mentioned above) and input it into the simulation storage and calculation module to perform multiplication and addition calculation to obtain a calculation result (i.e., the first calculation result mentioned above);

[0113] Among them, for the Mth column of storage and computing units, the target data set is input into the simulation storage and computing array for calculation to obtain the multiplication and addition calculation results; based on the multiplication and addition calculation results of each column of storage and computing units, the calculation results are obtained.

[0114] Step 1005: Compare the calculation result with the target value (i.e., the second calculation result mentioned above) to obtain a calculation error (i.e., the second error mentioned above);

[0115] Step 1006: inputting the input data and the calculated error into the error compensation module for fitting to obtain error compensation parameters;

[0116] The error compensation module fits the calculation error distribution through a linear function to obtain the error compensation parameters corresponding to the Mth column storage and calculation unit.

[0117] Step 1007: writing the error compensation parameters into the digital storage array;

[0118] The error compensation parameters corresponding to the storage and calculation units in the Mth column are written into the storage units in the Nth column of the digital storage and calculation array.

[0119] Step 1008: Periodically check whether the weight of the simulation storage array drifts.

[0120] Specifically, based on a preset cycle, the actual write weight is read from the simulated storage array, and the read write weight is compared with the written write weight to obtain a write error; when the write error is greater than the compensation range, it is determined that the weight is offset, and step 1001 is re-executed.

[0121] Here, in the process of model reasoning using the digital-analog hybrid storage and computing circuit, Fig.11 As shown, the following steps are included:

[0122] Step 1101: inputting target data (i.e. the target parameters to be calculated) into a simulation storage module to obtain a simulation calculation result (i.e. the fifth calculation result);

[0123] The analog calculation result is the digital calculation result obtained after ADC conversion.

[0124] Step 1102: input the target data into the digital storage and calculation module to obtain a digital compensation result (i.e., the sixth calculation result mentioned above);

[0125] Therein, digital compensation results can be obtained column by column.

[0126] Step 1103: The compensation module obtains the analog calculation results and the digital calculation results, adds them together, and obtains the final reasoning result (ie, the seventh calculation result mentioned above).

[0127] In the application example of this application, on the one hand, by setting the compensation range, a certain range of write errors is allowed to reduce the number of writes; on the other hand, after matching several digital storage and calculation units for each analog storage and calculation unit, error compensation is performed through the digital calculation array to calibrate the write error, line resistance error, device unit difference, etc. In this way, the write life of the analog device can be extended, the device resistance drift can be prevented, and at the same time, the calculation accuracy of the storage and calculation can be improved, giving play to the advantages of high performance and low power consumption.

[0128] Based on the computing device of the embodiment of the present application, the embodiment of the present application also provides a computing method, such as Fig.12As shown, the method includes:

[0129] Step 1201: the analog calculation unit of the computing device determines a first error and a second error corresponding to one or more first arrays, the analog calculation unit including the one or more first arrays, the first error includes a write error of each first array in the one or more first arrays, and the second error includes a calculation error of each first array in the one or more first arrays;

[0130] Step 1202: the compensation unit of the computing device fits the first error and the second error to obtain an error compensation parameter, and writes the error compensation parameter into one or more second arrays, the digital computing unit of the computing device includes the one or more second arrays, and one first array corresponds to one second array;

[0131] Step 1203: The digital calculation unit performs error compensation on the calculation results output by the one or more first arrays through the one or more second arrays.

[0132] In one embodiment, the analog computing unit further includes: a read / write circuit; the analog computing unit of the computing device determines the first error and the second error corresponding to the first arrays, including:

[0133] The read / write circuit writes a first parameter to the one or more first arrays and reads a second parameter from the one or more first arrays;

[0134] The read / write circuit determines the first error using the first parameter and the second parameter.

[0135] In one embodiment, the analog calculation unit further includes: a verification circuit; the method may further include:

[0136] The verification circuit compares the first error with a first threshold to obtain a comparison result;

[0137] The read-write circuit retains the first parameter written this time when the comparison result indicates that the first error is less than or equal to the first threshold.

[0138] In one embodiment, the method may further include:

[0139] The read / write circuit rewrites the first parameter into the one or more first arrays when the comparison result indicates that the first error is greater than the first threshold.

[0140] In one embodiment, the analog computing unit further includes: a read / write circuit; the analog computing unit of the computing device determines the first error and the second error corresponding to the first arrays, including:

[0141] The read / write circuit inputs a third parameter into the one or more first arrays, and obtains a first calculation result output by the one or more first arrays;

[0142] The read / write circuit determines the second error using the first calculation result and a second calculation result, wherein the second calculation result includes a target calculation result of the one or more first arrays.

[0143] In one embodiment, each of the one or more first arrays includes a plurality of analog units; the read / write circuit determines the second error using the first calculation result and the second calculation result, including:

[0144] For each first array, the read / write circuit writes the third parameter into the Mth column analog unit in the first array to obtain a third calculation result output by the Mth column analog unit, where M is an integer greater than or equal to 1;

[0145] The read / write circuit determines a third error using a third calculation result and a fourth calculation result, wherein the fourth calculation result includes a target calculation result of the analog cell in the Mth column, and the third error includes a calculation error of the analog cell in the Mth column.

[0146] In one embodiment, each of the one or more second arrays includes a plurality of computing units, and each simulation unit corresponds to a plurality of computing units; the compensation unit of the computing device fits the first error and the second error to obtain an error compensation parameter, including:

[0147] The compensation unit fits the first error and the third error to obtain a first error compensation parameter, and writes the first error compensation parameter into the Nth column calculation unit in the second array corresponding to the Mth column simulation unit, where N is an integer greater than or equal to 1.

[0148] In one embodiment, the method may further include:

[0149] The read / write circuit re-writes the third parameter into the Mth column of analog cells in the first array when the first error compensation parameter is greater than a second threshold.

[0150] In one embodiment, the method may further include:

[0151] The simulation calculation unit determines a fifth calculation result corresponding to the target parameter to be calculated through the one or more first arrays;

[0152] The digital calculation unit determines a sixth calculation result corresponding to the target parameter to be calculated through the one or more second arrays;

[0153] The compensation unit uses the sixth calculation result to perform error compensation on the fifth calculation result to obtain a seventh calculation result.

[0154] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0155] In addition, the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0156] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A computing device, characterized in that include: An analog computing unit, a digital computing unit and a compensation unit, wherein the analog computing unit includes one or more first arrays, the digital computing unit includes one or more second arrays, and one first array corresponds to one second array; wherein, The simulation calculation unit is used to determine a first error and a second error corresponding to the one or more first arrays, the first error includes a writing error of each first array in the one or more first arrays, and the second error includes a calculation error of each first array in the one or more first arrays; The compensation unit is configured to fit the first error and the second error to obtain an error compensation parameter, and write the error compensation parameter into the one or more second arrays; The digital calculation unit is used to perform error compensation on the calculation results output by the one or more first arrays through the one or more second arrays.

2. The computing device according to claim 1, wherein: The analog computing unit also includes: a read-write circuit; wherein, The read / write circuit is used to write a first parameter into the one or more first arrays and read a second parameter from the one or more first arrays; and determine the first error using the first parameter and the second parameter.

3. The computing device according to claim 2, characterized in that The analog calculation unit further includes: a verification circuit; wherein, The verification circuit is used to compare the first error with a first threshold to obtain a comparison result; The read-write circuit is used to retain the first parameter written this time when the comparison result indicates that the first error is less than or equal to the first threshold.

4. The computing device according to claim 3, characterized in that The read-write circuit is further configured to rewrite the first parameter into the one or more first arrays when the comparison result indicates that the first error is greater than the first threshold.

5. The computing device according to claim 1, wherein: The analog computing unit also includes: a read-write circuit; wherein, The read / write circuit is used to input a third parameter into the one or more first arrays and obtain a first calculation result output by the one or more first arrays; and determine the second error using the first calculation result and the second calculation result, wherein the second calculation result includes a target calculation result of the one or more first arrays.

6. The computing device according to claim 5, characterized in that Each of the one or more first arrays includes a plurality of analog units, and the read / write circuit is used to write the third parameter into the analog units in the Mth column of the first array for each first array, to obtain a third calculation result output by the analog units in the Mth column, where M is an integer greater than or equal to 1; A third error is determined using the third calculation result and the fourth calculation result, wherein the fourth calculation result includes the target calculation result of the M-th column of simulation cells and the third error includes the calculation error of the M-th column of simulation cells.

7. The computing device according to claim 6, characterized in that Each of the one or more second arrays includes multiple computing units, each simulation unit corresponds to multiple computing units, and the compensation unit is used to fit the first error and the third error to obtain a first error compensation parameter, and write the first error compensation parameter to the Nth column of computing units in the second array corresponding to the Mth column of simulation units, where N is an integer greater than or equal to 1.

8. The computing device according to claim 7, characterized in that The read-write circuit is further used for rewriting the third parameter into the Mth column of analog cells in the first array when the first error compensation parameter is greater than a second threshold value.

9. The computing device according to any one of claims 1 to 8, characterized in that: The simulation calculation unit is further used to determine a fifth calculation result corresponding to the target parameter to be calculated through the one or more first arrays; The digital calculation unit is further used to determine a sixth calculation result corresponding to the target parameter to be calculated through the one or more second arrays; The compensation unit is further used to use the sixth calculation result to perform error compensation on the fifth calculation result to obtain a seventh calculation result.

10. A calculation method, characterized in that: Applied to computing devices, including: The analog calculation unit of the computing device determines a first error and a second error corresponding to a plurality of first arrays, the analog calculation unit including the one or more first arrays, the first error including a written error of each first array in the plurality of first arrays, and the second error including a calculated error of each first array in the plurality of first arrays; The compensation unit of the computing device fits the first error and the second error to obtain error compensation parameters, and writes the error compensation parameters into one or more second arrays, the digital computing unit of the computing device includes the one or more second arrays, and one first array corresponds to one second array; The digital calculation unit performs error compensation on calculation results output by the one or more first arrays through the one or more second arrays.

Images