A time series report analysis method

Abstract

A timing report analysis method includes: generating a complete timing path based on the timing path information in the timing report, and storing it at each level; calculating the signal capture level according to the clock frequency and the delay information of the timing path, and setting the corresponding capture signal; adjusting the timing path to generate an ideal timing path; performing signal capture on the ideal timing path, analyzing and calculating the error of the timing delay in the timing report. The present application generates a timing circuit based on the timing path information of the timing report, and calculates the signal capture level according to the clock frequency and the delay information of the timing report, performs signal capture on the adjusted timing circuit, and judges whether there is an error in the timing delay in the timing report through the captured data, providing a reference for designers, thereby reducing the time cost and labor cost in the circuit optimization process and improving work efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of data processing, and in particular relates to a time series report analysis method. Background Art

[0002] Timing performance is one of the important indicators to measure whether a circuit can work properly. If there is a timing violation, the circuit cannot work properly. The timing report can show whether the timing is violated and can also find detailed information on the timing path.

[0003] The timing path is affected by two important parameters: user design and timing delay. When the user design is fixed, timing delay is the only indicator that affects timing performance.

[0004] Therefore, it is necessary to verify whether the timing delay in the timing report is accurate to ensure that the designer makes reasonable judgments based on the timing report and thus optimizes the circuit. Summary of the invention

[0005] The present application provides a timing report analysis method, which generates a timing circuit based on the timing path information of the timing report, calculates the signal capture level according to the clock frequency and the delay information of the timing report, and captures the signal of the adjusted timing circuit. It is judged whether there is an error in the timing delay in the timing report through the captured data, which provides a reference for designers, thereby reducing the time cost and labor cost in the circuit optimization process and improving work efficiency.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] To achieve one, part, or all of the above purposes or other purposes, the present invention provides a time series report analysis method.

[0008] A time series report analysis method, comprising:

[0009] Generate a sequential circuit based on the timing path information of the timing report, and register at each level of the sequential circuit;

[0010] Calculating the capture level of the signal according to the clock frequency and the delay information of the timing report, and setting the corresponding capture signal;

[0011] Adjusting the timing path of the sequential circuit to obtain an ideal timing path, wherein the ideal timing path is connected in the same manner as the timing model of the timing report;

[0012] The adjusted timing circuit is signal captured, and the timing delay error in the timing report is analyzed and calculated.

[0013] The specific process of generating a sequential circuit includes:

[0014] A complete timing path is generated based on the timing path information of the timing report, and the timing path is encoded and designed as a 50-level four-bit accumulator timing circuit. Each level of the timing circuit is equal to the previous level + 1, and 9 is subtracted every 10 levels to ensure that the data of each level does not exceed 16 bits, and the data of each level is stored in the register.

[0015] The specific process of calculating the capture level of the signal includes:

[0016] The calculation level is calculated according to the clock frequency and the delay information of the timing report, and the calculation level and the three levels before and after the calculation level are used as signal capture levels.

[0017] The calculation process of the calculation level is:

[0018] Calculation level = (clock cycle - (register A + register N)) / (internal logic delay + wiring delay);

[0019] Among them, register A is the internal delay of register A, register N is the internal delay of register N, and the logic internal delay and wiring delay are the delays within the same level of the sequential circuit.

[0020] If the calculation level is a non-integer, it needs to be rounded down.

[0021] The calculation level performs multiple samplings with different clock frequencies as samples, and different clock frequencies correspond to different capture levels.

[0022] The signal capture tool of the EDA software is used to capture data from registers at the signal capture level, and the captured data is stored in a buffer.

[0023] The timing path of the sequential circuit is adjusted to an ideal timing path through manual boxing and manual layout of EDA software, and the delay of each segment of the path of the ideal timing path and the timing model is the same.

[0024] The specific process of manual packing includes:

[0025] Obtain the components of each level of the 50-level four-bit accumulator sequential circuit, manually put the components of the same level into the same element cluster, and save them to the configuration file in a specified format;

[0026] The EDA software reads the configuration file and determines whether the packing rules are met. If so, specific packing is performed to generate an element cluster file, and the element cluster file is saved in the configuration file; otherwise, a packing failure log is printed.

[0027] The specific process of manual layout includes:

[0028] The EDA software reads the configuration file and determines whether the layout rules are met. If so, a specific layout is performed to generate a layout file. Otherwise, a layout failure log is printed.

[0029] The calculation process of the timing delay error in the timing report is:

[0030] Error rate = (measured level - calculated level) / calculated level;

[0031] The measured level is the level with the correct value among all levels captured in the same clock cycle.

[0032] If the error rate is a positive number, the timing delay in the timing report is relatively pessimistic; if the error rate is a negative number, the timing delay in the timing report is relatively optimistic.

[0033] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0034] This application generates a timing circuit based on the timing path information in the timing report, calculates the signal capture level according to the clock frequency and the delay information in the timing report, captures the signal of the adjusted timing circuit, and verifies whether the timing delay in the timing report is accurate through the captured data, providing a reference for designers.

[0035] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A flowchart of a timing report analysis method provided in an embodiment of the present application.

[0038] Figure 2 A complete timing path diagram provided for an embodiment of the present application.

[0039] Figure 3 A schematic diagram of signal capture provided in an embodiment of the present application.

[0040] Figure 4 A schematic diagram of the manual packing process provided in an embodiment of the present application.

[0041] Figure 5A schematic diagram of a configuration file provided in an embodiment of the present application.

[0042] Figure 6 A schematic diagram of the manual layout process provided in an embodiment of the present application.

[0043] Figure 7 A schematic diagram of a signal analysis page provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0045] This application generates a timing circuit based on the timing path information in the timing report, calculates the signal capture level according to the clock frequency and the delay information in the timing report, captures the signal of the adjusted timing circuit, and verifies whether the timing delay in the timing report is accurate through the captured data, providing a reference for designers.

[0046] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0047] Figure 1 The figure is a flow chart of a timing report analysis method provided in an embodiment of the present application.

[0048] like Figure 1 As shown, a timing report analysis method verifies whether the timing delay in the timing report is accurate through the generated timing circuit and the captured data, including:

[0049] Step S1: Generate a sequential circuit based on the timing path information in the timing report, and register it at each level of the sequential circuit;

[0050] Step S2: Calculate the capture level of the signal according to the clock frequency and the delay information of the timing report, and set the corresponding capture signal;

[0051] Step S3: adjusting the timing path of the sequential circuit to obtain an ideal timing path, where the ideal timing path is connected in the same way as the timing model in the timing report;

[0052] Step S4: Capture the signal of the adjusted timing circuit, analyze and calculate the error of the timing delay in the timing report.

[0053] Specifically, the specific process of generating the sequential circuit in step S1 includes:

[0054] First, generate a complete timing path based on the timing path information in the timing report, such as Figure 2 As shown in the figure, a complete timing path consists of two registers (register A and register N), a clock, and a logic combination. Excluding the changes caused by clock offset, the delay of the timing path is completely determined by the length of the path of the logic combination.

[0055] Write circuit code and design the generated timing path into a sequential circuit with 50 levels of 4-bit accumulators. Each level of the sequential circuit is equal to the previous level + 1, and 9 is subtracted every 10 levels to ensure that the data of each level does not exceed 16 bits (the maximum value of a 4-bit accumulator is 15), and the data of each level is stored in the register;

[0056] "50-level 4-bit accumulator" refers to a digital circuit composed of 50 4-bit accumulators in cascade, each 4-bit accumulator is responsible for processing the addition of 4-bit binary numbers, and 50 such accumulators cascaded together can process the addition of 200-bit binary numbers; a 4-bit accumulator is a digital circuit that can add two 4-bit binary numbers and output a 4-bit result and a carry flag. For example, a 4-bit accumulator can process the addition of binary numbers from 0000 to 1111 (that is, 0 to 15). "50 levels" means that there are 50 such 4-bit accumulators connected in series, each 4-bit accumulator processes a part of the input data and passes the result to the next 4-bit accumulator, and finally it can process the addition of 200-bit binary numbers.

[0057] Working principle of "50-level 4-bit accumulator":

[0058] Input: Suppose you have a 200-digit binary number A and a 200-digit binary number B.

[0059] Processing: The first 4-bit accumulator processes the lowest 4 bits of A and the lowest 4 bits of B, producing a 4-bit result and a carry.

[0060] Cascading: The second 4-bit accumulator processes the next 4 bits of A and the next 4 bits of B while taking into account the carry from the first accumulator, and so on.

[0061] Output: The 50th 4-bit accumulator processes the highest 4 bits of A and the highest 4 bits of B, ultimately producing a 200-bit result and a final carry flag.

[0062] Step S2 estimates the capture range of the signal. It is necessary to first obtain the calculation level. Since "clock cycle = register A + calculation level * (logic internal delay + wiring delay) + register N", the calculation level = (clock cycle - (register A + register N)) / (logic internal delay + wiring delay);

[0063] Among them, register A is the internal delay of register A, register N is the internal delay of register N, the delays inside register A and register N are fixed, and the internal logic delay and wiring delay are the delays within one level of the sequential circuit.

[0064] In addition, if the calculation level is a non-integer, the calculation level needs to be rounded down.

[0065] Signal capture Figure 3 As shown, the calculation level n, the first three levels n-1 / n-2 / n-3 of the calculation level, and the last three levels n+1 / n+2 / n+3 of the calculation level are all used as signal capture levels.

[0066] like Figure 3 As shown, data of the target register n, registers n-1 / n-2 / n-3 and registers n+1 / n+2 / n+3 are captured by the capture signal, and the captured data is stored in the buffer.

[0067] In step S2, the calculation level performs multiple samplings with different clock frequencies as samples, and different clock frequencies correspond to different capture levels.

[0068] The clock cycle represents the time from a rising edge to a falling edge of the clock signal, which is inversely proportional to the clock frequency; the maximum operating frequency is inversely proportional to the maximum timing path delay.

[0069] The corresponding relationship between different clock frequencies and clock cycles is shown in Table 1:

[0070]

[0071] Table 1

[0072] Step S3 adjusts the timing path of the sequential circuit to an ideal timing path through manual binning and manual layout of the EDA software. The ideal timing path has the same delay as each path of the timing model.

[0073] Specifically, the manual packing process is as follows: Figure 4 As shown, including:

[0074] Get the components of each level of the 50-level 4-bit accumulator sequential circuit. Each level of the 4-bit accumulator will synthesize 4 components;

[0075] Manually place components of the same level into the same element cluster. Each coordinate (element cluster) can hold up to 10 components. To achieve average delay at each level, components of the same level should be placed in the same element cluster.

[0076] Save the configuration file in the specified format, and read the configuration file through the EDA software to determine whether the packing rules are met;

[0077] If it is satisfied, then specific packing is performed to generate element cluster files, and the element cluster files are saved in the configuration file;

[0078] Otherwise, a packing failure log is printed.

[0079] After manual boxing, the components of each level are saved in the same element cluster, and the element cluster is saved in the configuration file by name; Figure 5 As shown, each column of components in the FPGA is of the same type, the element clusters corresponding to the logic combination are placed in the same column, the element clusters corresponding to the registers are placed in adjacent columns, and the element clusters corresponding to the buffers are placed in the storage column; the X-axis coordinates of the logic combination element clusters are the same, and the Y-axis coordinates are arranged in order from small to large according to the level; the element clusters corresponding to the registers are arranged in order of the X-axis coordinates of the element clusters corresponding to the adjacent logic combinations.

[0080] Manual layout process such as Figure 6 As shown, including:

[0081] The logical coordinates in EDA are set for each element cluster. The EDA software reads the manual layout configuration file and determines whether the layout rules are met. If so, a specific layout is performed to generate a layout file. Otherwise, a layout failure log is printed.

[0082] After the manual layout is completed, the connections between all layers are optimal. After the subsequent process is completed using the automated algorithm, the code stream needs to be downloaded to the board with the debugging module and the signal is analyzed through the signal capture tool in the EDA software, such as Figure 7 shown.

[0083] As a preferred embodiment of the present invention, the difference between the values ​​of adjacent levels captured in the same clock cycle in this embodiment should be 1, and the difference between the values ​​of consecutive clock cycles of the same register at the same level should also be 1, and the error rate = (measured level - calculated level) / calculated level;

[0084] The measured level is the level with the correct value among all levels captured in the same clock cycle.

[0085] If the error rate is a positive number, the timing delay in the timing report is more pessimistic; if the error rate is a negative number, the timing delay in the timing report is more optimistic.

[0086] like Figure 7 As shown, the calculated value of level 44 is wrong, while the value of level 43 is correct. The correct level is smaller than the calculated level, and the timing delay in the timing report is optimistic.

[0087] This application generates a timing circuit based on the timing path information in the timing report, calculates the signal capture level according to the clock frequency and the delay information in the timing report, captures the signal of the adjusted timing circuit, and verifies whether the timing delay in the timing report is accurate through the captured data, providing a reference for designers.

[0088] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0089] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A time series report analysis method, characterized in that: include: Generate a sequential circuit based on the timing path information of the timing report, and register at each level of the sequential circuit; Calculating the capture level of the signal according to the clock frequency and the delay information of the timing report, and setting the corresponding capture signal; Adjusting the timing path of the sequential circuit to obtain an ideal timing path, wherein the ideal timing path is connected in the same manner as the timing model of the timing report; Capture signals of the adjusted timing circuit, analyze and calculate the error of the timing delay in the timing report; The specific process of generating a sequential circuit based on the timing path information of the timing report includes: A complete timing path is generated based on the timing path information of the timing report, and the timing path is encoded and designed as a 50-level four-bit accumulator timing circuit. Each level of the timing circuit is equal to the previous level + 1, and 9 is subtracted every 10 levels to ensure that the data of each level does not exceed 16 bits, and the data of each level is stored in the register.

2. A time series report analysis method according to claim 1, characterized in that: The specific process of calculating the capture level of the signal includes: The calculation level is calculated according to the clock frequency and the delay information of the timing report, and the calculation level and the three levels before and after the calculation level are used as signal capture levels.

3. A time series report analysis method according to claim 2, characterized in that: The calculation process of the calculation level is: Calculation level = (clock cycle - (register A + register N)) / (internal logic delay + wiring delay); Among them, register A is the internal delay of register A, register N is the internal delay of register N, and the logic internal delay and wiring delay are the delays within the same level of the sequential circuit.

4. A time series report analysis method according to claim 3, characterized in that: If the calculation level is a non-integer, it needs to be rounded down.

5. A time series report analysis method according to claim 2, characterized in that: The calculation level performs multiple samplings with different clock frequencies as samples, and different clock frequencies correspond to different capture levels.

6. A time series report analysis method according to claim 1, characterized in that: The signal capture tool of the EDA software is used to capture data from registers at the signal capture level, and the captured data is stored in a buffer.

7. A time series report analysis method according to claim 1, characterized in that: The timing path of the sequential circuit is adjusted to an ideal timing path through manual boxing and manual layout of EDA software, and the delay of each segment of the path of the ideal timing path and the timing model is the same.

8. A time series report analysis method according to claim 7, characterized in that: The specific process of manual packing includes: Obtain the components of each level of the 50-level four-bit accumulator sequential circuit, manually put the components of the same level into the same element cluster, and save them to the configuration file in a specified format; The EDA software reads the configuration file and determines whether the packing rules are met. If so, specific packing is performed to generate an element cluster file, and the element cluster file is saved in the configuration file; otherwise, a packing failure log is printed.

9. A time series report analysis method according to claim 8, characterized in that: The specific process of manual layout includes: The EDA software reads the configuration file and determines whether the layout rules are met. If so, a specific layout is performed to generate a layout file. Otherwise, a layout failure log is printed.

10. A time series report analysis method according to claim 1, characterized in that: The calculation process of the timing delay error in the timing report is: Error rate = (measured level - calculated level) / calculated level; The measured level is the level with the correct value among all levels captured in the same clock cycle.

11. A time series report analysis method according to claim 10, characterized in that: If the error rate is a positive number, the timing delay in the timing report is pessimistic; if the error rate is a negative number, the timing delay in the timing report is optimistic.

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