Estimation method of integrated circuit chip for integrated circuit design and integrated circuit chip

Abstract

The invention relates to an estimation method of an integrated circuit chip, which comprises the following steps of: calculating a first slope value of a distance-space relationship of a first design condition according to a spatial distance value between circuit elements of the integrated circuit chip and a spatial process change of the first design condition; calculating a second slope value of a distance-space relationship of a second design condition according to the spatial distance value and a spatial process change of the second design condition; calculating a regression proportionality coefficient and a regression power coefficient according to the first slope value, the second slope value, the overall process change of the first design condition and the overall process change of the second design condition; calculating a third slope value of a third design condition according to the regression proportionality coefficient, the regression power coefficient and the overall process change of the third design condition; and estimating the space process change of the third design condition according to the third slope value and the space distance value.

Description

Technical Field

[0001] The present invention relates to integrated circuit design, and in particular to an integrated circuit chip and an estimation method of the integrated circuit chip used in integrated circuit design. Background Art

[0002] Generally speaking, traditional integrated circuit design requires the use of a variety of different design conditions, such as various combinations of design conditions including different standard cell heights, different voltages, different channel lengths, different operating temperatures, etc., to generate or form a spatial variation model of the integrated circuit design.

[0003] There are two existing methods for generating data of spatial variation models. The first existing method is to obtain the data of the spatial variation model directly from the manufactured chip. The advantage of this method is that the chip data directly obtained is quite accurate. However, its disadvantage is that it necessarily requires a considerable process time and a considerable manufacturing cost to implement this method. For example, it is actually necessary to design and manufacture a test circuit chip, ask the wafer factory to manufacture chips under different design conditions, and then measure and obtain the chip data. This is very resource-consuming for circuit designers.

[0004] Another existing method is to directly refer to adjacent similar design conditions. For example, assuming that there is already a spatial variation model for some design conditions, but due to design requirements, different voltages, different standard component heights, different channel lengths and / or different operating temperatures need to be used, this method directly refers to similar design conditions to generate data for the spatial variation model. The advantage is that it does not require chip data measurement, but the disadvantage is that the data accuracy of the generated spatial variation model will be quite poor. Summary of the invention

[0005] Therefore, one of the objectives of the present invention is to provide an integrated circuit design and a corresponding method to solve the above-mentioned problem.

[0006] The present invention uses a mathematical method of regression analysis to perform interpolation or extrapolation operations on the existing amount of spatial variation model data, in order to achieve both high parameter data accuracy and rapid generation of spatial variation models, thereby solving the problems encountered by the prior art. Compared with the prior art, the cost of the technical solution provided by the present invention is relatively small.

[0007] According to an embodiment of the present invention, a method for estimating an integrated circuit chip for an integrated circuit design is disclosed. The estimation method includes: obtaining an overall process variation of a first design condition and a spatial process variation of the first design condition; obtaining an overall process variation of a second design condition and a spatial process variation of the second design condition; calculating a first slope value of the distance-space relationship of the first design condition based on a spatial distance value between a first circuit element of the integrated circuit chip and a second circuit element of the integrated circuit chip and the spatial process variation of the first design condition, wherein the first circuit element and the second circuit element both have a specific circuit design structure; calculating the second design condition based on the spatial distance value and the spatial process variation of the second design condition. a second slope value of the distance-space relationship of the first design condition; calculating a regression proportionality coefficient and a regression power coefficient according to the first slope value, the second slope value, the overall process change of the first design condition and the overall process change of the second design condition; obtaining an overall process change of a third design condition by simulation calculation; calculating a third slope value of the distance-space relationship of the third design condition according to the regression proportionality coefficient, the regression power coefficient and the overall process change of the third design condition; and estimating a spatial process change of the third design condition at the spatial distance value between the first circuit element and the second circuit element according to the third slope value and the spatial distance value.

[0008] According to an embodiment of the present invention, an integrated circuit chip is also disclosed. The integrated circuit chip includes at least a first circuit element and a second circuit element, and both the first circuit element and the second circuit element have a specific circuit design structure. A spatial distance value between the first circuit element and the second circuit element and a spatial process variation of the integrated circuit chip under a first design condition are used to calculate a first slope value of the distance-space relationship of the first design condition, then the spatial distance value and a spatial process variation of the integrated circuit chip under a second design condition are used to calculate a second slope value of the distance-space relationship of the second design condition, then the first slope value, the second slope value, an overall process variation of the integrated circuit chip under the first design condition, and an overall process variation of the integrated circuit chip under the second design condition are used to calculate a regression proportionality coefficient and a regression power coefficient, then the regression proportionality coefficient, the regression power coefficient, and an overall process variation of the integrated circuit chip under a third design condition are used to calculate a third slope value of the distance-space relationship of the third design condition, and then the third slope value and the spatial distance value are used to calculate a spatial process variation of the integrated circuit chip under the third design condition at the spatial distance value between the first circuit element and the second circuit element. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a flow chart of a method for estimating a spatial process variation of an integrated circuit chip according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of an example of overall process variation, local process variation and spatial process variation according to an embodiment of the present invention;

[0011] Figure 3 The embodiment of the present invention Figure 1 Schematic diagram of an example of regression calculation using the process method.

[0012] Description of reference numerals:

[0013] S105-S150: Step 200: Integrated circuit chips T1-T16: transistors DETAILED DESCRIPTION

[0014] The present invention aims to provide a method that can quickly and sufficiently accurately generate or estimate a spatial process variation of a circuit element of an integrated circuit chip under a specific design condition. The method refers to the spatial process variation of the circuit element of the integrated circuit chip under other close or similar design conditions and uses regression analysis calculations to accurately estimate the spatial process variation of the circuit element of the integrated circuit chip under the specific design condition, without the need to actually measure the spatial process variation of the integrated circuit chip under the specific design condition. Therefore, the time for manufacturing and measuring through the wafer fab can be greatly reduced, thereby reducing considerable costs.

[0015] Please refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for estimating a spatial process variation of an integrated circuit chip for an integrated circuit design according to an embodiment of the present invention. Figure 1 The steps in the process shown are performed in the order shown, and Figure 1 The steps shown do not have to be performed continuously, that is, other steps may be inserted therein; the process steps of the method of the present invention are described in detail as follows:

[0016] Step S105: start;

[0017] Step S110: obtaining a global process variation (or inter-die process variation) of an integrated circuit chip (or die) under a first design condition and a spatial process variation (or spatial process variation) under the first design condition;

[0018] Step S115: obtaining an overall process variation of the integrated circuit chip under a second design condition and a spatial process variation of the integrated circuit chip under the second design condition;

[0019] Step S120: Calculating a first slope value of a distance-to-spatial relation under the first design condition according to a spatial distance value between a first circuit element of the integrated circuit chip and a second circuit element of the integrated circuit chip and the spatial process variation under the first design condition, wherein both the first circuit element and the second circuit element have a specific circuit design structure, such as a specific transistor structure, such as an inverter (but not limited to);

[0020] Step S125: Calculating a second slope value of the distance-space relationship of the second design condition according to the spatial distance value and the spatial process change under the second design condition;

[0021] Step S130: Calculate a linear regression coefficient and a polynomial regression coefficient according to the first slope value, the second slope value, the overall process variation under the first design condition, and the overall process variation under the second design condition;

[0022] Step S135: simulating and calculating to obtain an overall process change of a third design condition;

[0023] Step S140: Calculating a third slope value of the distance-space relationship under the third design condition according to the regression proportionality coefficient, the regression power coefficient, and the overall process variation under the third design condition;

[0024] Step S145: estimating a spatial process variation under the third design condition at the spatial distance value between the first circuit element and the second circuit element according to the third slope value and the spatial distance value; and

[0025] Step S150: End.

[0026] The following first describes and defines the differences between the overall process variation, local process variation (or intra-die process variation), and spatial process variation of the present invention. Figure 2 , Figure 2It is an example schematic diagram of overall process variation, local process variation and spatial process variation of one embodiment of the present invention. The yield of chip manufacturing of circuit design is affected by three factors such as overall process variation, local process variation and spatial process variation. Therefore, the circuit chip design needs to take these three variations into consideration. The first variation refers to overall process variation, which refers to the variation / variation of the same circuit design element between chips (inter-die, die-to-die, chip-to-chip, lot-to-lot, wafer-to-wafer), such as the manufacturing non-uniformity between chips in the semiconductor manufacturing process, such as etching, exposure, chemical deposition, etc. caused by the conductor manufacturing process. When analyzing the overall process variation, the semiconductor manufacturing process, the actual operating voltage of the chip, the operating temperature, and the selected critical voltage value, etc., are taken into consideration. For example, Figure 2 One of the wafers in the plurality of wafers shown in part (a) includes a plurality of chips / die, and the statistical characteristics of the overall process variation between the chips present a Gaussian distribution, for example (but not limited to). In addition, the second type of variation refers to local process variation, which refers to the variation / variation amount of the same circuit design element within the same chip (intra-die variation), which is a kind of random variation inside a small-sized chip assuming that the semiconductor manufacturing process is uniform, for example Figure 2 The statistical characteristics of local process variations within a chip / die as shown in part (b) of the figure, for example, present a statistical characteristic similar to random generation (but not limited to). In addition, the third type of variation refers to spatial process variation, which refers to the variation / variation amount caused by the different spatial distances of the same circuit design elements in the same chip. For example, two identical circuit design elements in the same chip, the variation caused by the different distances is called spatial process variation, and this spatial process variation amount will also vary depending on different design conditions (such as different standard cell heights, different voltages, different channel lengths, and different operating temperatures). The variation amount of spatial process variation will be proportional to the distance, for example Figure 2 A wafer as shown in part (c) of the embodiment includes a plurality of chips / bare dies, and a chip / bare die includes a plurality of circuit elements (such as transistors T1 to T16, but not limited thereto). A first circuit element (such as transistor T1) and a second circuit element (such as transistor T16 or other transistors) among the transistors T1 to T16 have the same circuit design structure (such as inverters, but not limited thereto) and / or operate under the same design conditions, and Figure 2Part (d) shows the result value of local process variation that additionally considers the influence of spatial process variation. The horizontal axis shows the different spatial distances (in μm) at which circuit elements are placed within a chip, and the vertical axis shows, for example, the corresponding actual measured local process variation value. When the spatial distance is zero, it corresponds to a pure local process variation without the influence of spatial process variation. However, when the spatial distance is not zero, the measured local process variation needs to additionally consider the influence of spatial process variation. The multiple transistors T1 to T16 will actually have different measured local process variation values ​​due to the different spatial placement distances. In addition, as shown in the figure, the statistical characteristics of the spatial process variation of circuit elements within the same chip present a trend similar to linear growth. Please continue to refer to Figure 2 As shown in part (e), it is the result value of local process variation without considering the influence of spatial process variation. The horizontal axis shows the different spatial distances (in μm) at which the circuit elements in a chip are placed, and the vertical axis shows the value of local process variation. It is assumed that there is no influence of spatial process variation. The numerical results can be shown in the following table:

[0027]

[0028] As described in the previous paragraph, traditional integrated circuit design requires the use of a variety of different design conditions, such as design conditions including different standard component heights, different voltages, different channel lengths, different operating temperatures, etc., to generate or form a spatial variation model of the integrated circuit design. A spatial variation model, for example, includes routing design of clock tree synthesis, such as a comparison table, which includes various different distance values ​​actually measured in traditional integrated circuit design under different design components and various different percentage adjustment values ​​of corresponding routing timing. For example, according to different distance values, the timing delay of the designed circuit unit / component needs to be multiplied by the corresponding different percentage adjustment values ​​to reflect the compensation or reduction of the impact of spatial process variation.

[0029] The advantage of the present invention is that, assuming that the spatial process variation corresponding to at least two sets of design conditions has been measured, a spatial process variation corresponding to another set of design conditions with a certain degree of accuracy can be generated through rapid calculation of regression analysis to generate or form a spatial variation model, so there is no need to measure each different set of design conditions as in the traditional method. For example (but not limited to), suppose that one currently wants to obtain the spatial process variation corresponding to a design condition of a low voltage (e.g., 0.7 volts), but the data of the spatial variation model actually measured currently only include the spatial process variation corresponding to two design conditions including 0.8 volts and 0.9 volts. At this time, the rapid calculation of the regression analysis of the present invention can be used to obtain a spatial process variation corresponding to the design condition of 0.7 volts to update the data of the spatial variation model.

[0030] The following describes the definitions of symbols used in one embodiment of the present invention:

[0031] Symbol d ij is the distance between the i-th circuit element / component and the j-th circuit element / component in the same chip, which can also be abbreviated as d;

[0032] The symbol x represents a certain type or a certain design condition, for example, x1, x2, and x3 represent three different design conditions corresponding to different operating voltages;

[0033] σ s (x) 2 is the spatial process variation under the design condition x, which can also be expressed as σ s 2 (x);

[0034] σ g (x) 2 is the overall process variation under the design condition x, which can also be expressed as σ g 2 (x);

[0035] ρ(d) is a function of the relationship between the spatial process variation and the distance, which refers to the spatial process variation caused by the distance d when the variable of the distance d is known; and

[0036] Cov(i,j) is the covariance between the i-th circuit element and the j-th circuit element.

[0037] Assume that for a very small chip, the local process variation ρ1 is equal to 0, while the spatial process variation ρ2 is greater than 0 and equal to ρ(d ij), and the value of the overall process variation ρ3 is a maximum value and can be assumed to be a fixed value (compared to the local process variation ρ1 and the spatial process variation ρ2). Cov(i,j) can be expressed by the following equation:

[0038] Cov(i,j)=σ g 2 (x)+ρ(d)×σ s 2 (x)

[0039] where σ g 2 (x) is the overall process variation under the design condition x, and can be considered as a fixed value when the distance d is maximum under the design condition x.

[0040] where σ s 2 (x) = ss(x) × d

[0041] ss(x) refers to the spatial process variation σ of distance d under design condition x. s 2 (x), that is, the slope value of the distance d to the spatial process variation σ of the embodiment of the present invention s 2 (x) is calculated by linear regression. In the embodiment of the present invention, the slope value ss(x) can be approximated by a linear regression using a regression proportional coefficient a1 and an exponential regression using a regression power coefficient b1 to approximate the slope value ss(x) as closely as possible:

[0042]

[0043] That is, the embodiment of the present invention has a significant impact on the spatial process variation σ s 2 The slope value ss(x) of (x) and the overall process variation σ g 2 (x) is calculated by using a polynomial quadratic regression method. Therefore, the present invention aims to use the two spatial process variations actually measured under at least two different design conditions (e.g., two different design conditions x1, x2) to calculate the two slope values ​​ss(x1) and ss(x2) corresponding to the design conditions x1 and x2 in the actual measurement, and then use the above-mentioned linear regression and exponential regression approximation method to calculate the values ​​of a1 and b1, and then use the values ​​of a1 and b1 and the above-mentioned approximate equation to calculate the distance d to the spatial process variation σ under the design condition x3. s 2(x3), and then calculate and estimate a spatial process variation σ of the distance d under the design condition x3 based on the slope value ss(x3) and the distance d s 2 (x3), so that the comparison table in the spatial variation model can be newly added or updated, so that the comparison table of the spatial variation model can record the estimated spatial process variation of the distance d under the design condition x3 without actually measuring the design condition x3, and correspondingly record a percentage adjustment value of the estimated spatial process variation in proportion thereto, so that subsequent circuit designers can directly select or adopt the estimated spatial process variation to compensate for the actual spatial process variation of the distance d under the design condition x3.

[0044] It should be noted that the above-mentioned method flow and the calculation of linear regression and exponential regression can be executed on a computer device operated by a circuit chip designer. For example, a processor of the computer device can receive data of a basic spatial variation model mentioned from a wafer factory, and the data of the basic spatial variation model, for example, includes measurement data of spatial process variations related to two different sets of design conditions x1 and x2, but does not include measurement data of spatial process variations of design condition x3. At this time, the circuit chip designer can operate the computer device to let the processor perform the above-mentioned method flow and the calculation of linear regression and exponential regression to estimate the spatial process variation of design condition x3, and supplement or update the spatial process variation data of design condition x3 in the basic spatial variation model to generate an updated spatial variation model without the need for measurement by the wafer factory.

[0045] Please refer again Figure 1 And with reference Figure 3 , Figure 3 An embodiment of the present invention Figure 1 An example diagram of the regression calculation of the process method. Figure 3 As shown, first, the circuit designer can, for example, receive a first design condition x1 (for example, a first operating voltage) provided by a wafer factory and obtain the actual measured spatial process variation σ corresponding to the first design condition x1 (for example, a first operating voltage) through a computer device. s 2 (x1) and also use the computer device to analyze and calculate the overall process variation σ of the first design condition x1 from the model data provided by the wafer factory g 2 (x1) (step S110), then similarly, the circuit designer can receive, for example, through the computer device, the actual measured spatial process variation σ corresponding to a second design condition x2 (for example, a second operating voltage different from the first operating voltage) provided by the wafer factory. s2 (x2) and also use the computer device to analyze and calculate the overall process variation σ of the second design condition x2 from the model data provided by the wafer factory g 2 (x2) (step S1105). Then, the spatial process variation actually measured under a design condition is equal to a corresponding spatial distance value multiplied by a corresponding slope value under the design condition. Therefore, as described in steps S120 and S125, the circuit designer can, for example, use the computer device to calculate the spatial process variation σ under the first design condition x1 according to a spatial distance value d between a first circuit element of the integrated circuit chip and a second circuit element of the integrated circuit chip. s 2 (x1), calculate a first slope value ss(x1) of the distance-to-spatial relation under the first design condition x1, and calculate the spatial process variation σ under the second design condition x2 according to the spatial distance value d between the first circuit element of the integrated circuit chip and the second circuit element of the integrated circuit chip. s 2 (x2), a second slope value ss(x2) of the distance-space relationship under the second design condition x2 is calculated. The relationship between the two slope values ​​and the spatial distance value d and the corresponding spatial process variation can be expressed by the following equation:

[0046] σ s 2 (x1) = ss(x1) × d; and

[0047] σ s 2 (x2)=ss(x2)×d.

[0048] Next, after calculating the first slope value ss(x1) and the second slope value ss(x2), the circuit designer may, for example, use the computer device to perform the above-mentioned regression analysis (such as step S130) to obtain the overall process variation σ under the first design condition x1 according to the first slope value ss(x1), the second slope value ss(x2), and the overall process variation σ under the first design condition x1. g 2 (x1) and the overall process variation σ under the second design condition x2 g 2 (x2) to calculate a regression proportional coefficient a1 and a regression power coefficient b1. The regression calculation can be expressed by the following equation:

[0049] ss(x1)=a1×(σ g 2 (x1))b1 ;as well as

[0050] ss(x2)=a1×(σ g 2 (x2)) b1 .

[0051] In addition, as shown in step S135, the circuit designer can, for example, use the computer device to simulate and calculate an overall process variation σ of a third design condition x3. g 2 (x3), the third design condition x3 is different from the previous two design conditions, for example, a different operating voltage. Then, after estimating the regression proportional coefficient a1 and the regression power coefficient b1, the circuit designer can, for example, use the computer device to calculate the overall process variation σ based on the regression proportional coefficient a1, the regression power coefficient b1 and the overall process variation σ under the third design condition x3. g 2 (x3), calculate a third slope value ss(x3) of the distance-space relationship under the third design condition x3 (step S140), and the calculated third slope value ss(x3) can be expressed by the following equation:

[0052] ss(x3)=a1×(σ g 2 (x3)) b1 .

[0053] Next, after calculating the third slope value ss(x3), the circuit designer can estimate, by means of the computer, a spatial process variation σ under the third design condition x3 based on the calculated third slope value ss(x3) and the spatial distance value d. s 2 (x3), spatial process variation σ s 2 (x3) can be expressed by the following equation:

[0054] σ s 2 (x3)=ss(x3)×d.

[0055] In this way, the circuit designer can, for example, use the computer device to calculate the estimated spatial process variation σ s 2 (x3), from the actual measured spatial process variation σ s 2 (x1), spatial process variation σ s 2(x1) corresponds to a percentage adjustment value, the actual measured spatial process variation σ s 2 (x2), spatial process variation σ s 2 (x2) corresponds to another percentage adjustment value, and the estimated spatial process variation σ is linearly estimated. s 2 (x3), and the estimated percentage adjustment value can be used subsequently to compensate and mitigate the line delay of the circuit unit actually caused by a spatial process variation in the spatial distance value d and the third design condition x3.

[0056] For example (but not limited to), the actual measurement data of the existing spatial variation model includes two different percentage adjustment values ​​corresponding to different spatial process variation amounts of two different operating voltages of 0.765 volts and 0.675 volts, such as 1.034 and 1.048. For a new design condition, such as a different operating voltage of 0.585 volts, the existing method of measuring chip data, such as the actual measured spatial process variation amount corresponding to a percentage adjustment value of 1.0732, and the existing method of directly referring to the adjacent similar design conditions, such as directly referring to the adjacent operating voltage of 0.675 volts. The percentage adjustment value corresponding to 5 volts, for example, 1.048, is used as the percentage adjustment value of the operating voltage of 0.585 volts. However, it differs from the actual measured value by a large proportion, for example, the difference between the two is more than 2.5%, which will greatly affect the efficiency of chip use. Compared with the two existing methods, the regression analysis calculation method of the present invention does not require actual measurement of chip data, and the percentage adjustment value obtained is, for example, 1.0734, which differs from the actual measured value by only less than 0.5%. It has extremely high accuracy and the advantages of quickly generating spatial variation model data and low cost.

[0057] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made within the protection scope of the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for estimating an integrated circuit chip for an integrated circuit design, characterized in that: include: Obtaining an overall process variation of a first design condition and a spatial process variation of the first design condition; Obtaining an overall process variation of a second design condition and a spatial process variation of the second design condition; Calculating a first slope value of the distance-space relationship of the first design condition according to a spatial distance value between a first circuit element of the integrated circuit chip and a second circuit element of the integrated circuit chip and the spatial process variation of the first design condition, wherein the first circuit element and the second circuit element both have a specific circuit design structure; Calculating a second slope value of the distance-space relationship of the second design condition according to the spatial distance value and the spatial process variation of the second design condition; Calculating a regression proportionality coefficient and a regression power coefficient according to the first slope value, the second slope value, the overall process variation of the first design condition, and the overall process variation of the second design condition; Simulating and calculating an overall process change of a third design condition; Calculating a third slope value of the distance-space relationship of the third design condition according to the regression proportionality coefficient, the regression power coefficient and the overall process change of the third design condition; as well as A spatial process variation of the third design condition under the spatial distance value between the first circuit element and the second circuit element is estimated according to the third slope value and the spatial distance value.

2. The estimation method according to claim 1, characterized in that: The first slope value is a result of dividing the spatial process variation of the first design condition by the spatial distance value.

3. The estimation method according to claim 1, characterized in that: The second slope value is a result of dividing the spatial process variation of the second design condition by the spatial distance value.

4. The estimation method according to claim 1, characterized in that: The first design condition is x1, the first slope value is ss(x1), and the overall process change of the first design condition is σ g 2 (x1), the second design condition is x2, the second slope value is ss(x2), and the overall process change of the second design condition is σ g 2 (x2), and the regression proportional coefficient a1 and a regression power coefficient b1 are calculated by the following two equations: ss(x1)=a1×(σ g 2 (x1)) b1 ; ss(x2)=a1×(σ g 2 (x2)) b1 。 5. The estimation method according to claim 4, characterized in that: The overall process variation of the third design condition is σ g 2 (x3), the third slope value is ss(x3) and is represented by the following equation: ss(x3)=a1×(σ g 2 (x3)) b1 ; The spatial process variation of the third design condition is equal to a result obtained by multiplying the third slope value by the spatial distance value between the first circuit element and the second circuit element.

6. An integrated circuit chip, characterized in that: At least: a first circuit element; as well as a second circuit element, wherein the first circuit element and the second circuit element both have a specific circuit design structure; A spatial distance value between the first circuit element and the second circuit element of the integrated circuit chip and a spatial process variation of the integrated circuit chip under a first design condition are used to calculate a first slope value of the distance-space relationship of the first design condition, then the spatial distance value and a spatial process variation of the integrated circuit chip under a second design condition are used to calculate a second slope value of the distance-space relationship of the second design condition, then the first slope value, the second slope value, an overall process variation of the integrated circuit chip under the first design condition, and an overall process variation of the integrated circuit chip under the second design condition are used to calculate a regression proportionality coefficient and a regression power coefficient, then the regression proportionality coefficient, the regression power coefficient, and an overall process variation of the integrated circuit chip under a third design condition are used to calculate a third slope value of the distance-space relationship of the third design condition, and then the third slope value and the spatial distance value are used to calculate a spatial process variation of the integrated circuit chip under the third design condition at the spatial distance value between the first circuit element and the second circuit element.

7. The integrated circuit chip according to claim 6, characterized in that: The first slope value is a result of dividing the spatial process variation of the first design condition by the spatial distance value.

8. The integrated circuit chip according to claim 6, characterized in that: The second slope value is a result of dividing the spatial process variation of the second design condition by the spatial distance value.

9. The integrated circuit chip according to claim 6, characterized in that: The first design condition is x1, the first slope value is ss(x1), and the overall process change of the first design condition is σ g 2 (x1), the second design condition is x2, the second slope value is ss(x2), and the overall process change of the second design condition is σ g 2 (x2), and the regression proportional coefficient a1 and a regression power coefficient b1 are calculated by the following two equations: ss(x1)=a1×(σ g 2 (x1)) b1 ; ss(x2)=a1×(σ g 2 (x2)) b1 。 10. The integrated circuit chip according to claim 9, characterized in that: The overall process variation of the third design condition is σ g 2 (x3), the third slope value is ss(x3) and is represented by the following equation: ss(x3)=a1×(σ g 2 (x3)) b1 ; The spatial process variation of the third design condition is equal to a result obtained by multiplying the third slope value by the spatial distance value between the first circuit element and the second circuit element.

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