Gate driving circuit, gate driving chip and electronic equipment

Abstract

A gate drive circuit, a gate drive chip and an electronic device, the gate drive circuit comprising: a discharge circuit comprising: a first constant current reference generation circuit, used for outputting an adjustable first current, and a second constant current reference generation circuit, which are connected in sequence; a first current mirror circuit for outputting a second current based on the first current; the first output stage circuit is used for working based on the second current, so that a third current output to the first output stage circuit by the power device is adjustable; the charging circuit comprises a second constant-current reference generation circuit used for outputting an adjustable fourth current and a second constant-current reference generation circuit which are connected in sequence; the second current mirror circuit is used for outputting a fifth current based on the fourth current; and the second output stage circuit is used for working based on the fifth current, so that a sixth current output to the power device by the second output stage circuit is adjustable, and the power device is connected to the output end of the first output stage circuit and the output end of the second output stage circuit. The gate drive circuit can solve the problem that a power device is not matched with the gate drive circuit.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and more specifically to a gate drive circuit, a gate drive chip and an electronic device. Background Art

[0002] With the rapid development of electronic technology, especially in the field of power electronics, higher and higher requirements are placed on the accuracy and stability of current control.

[0003] The current gate drive circuit controls the on and off of power devices (such as insulated gate bipolar transistors IGBTs or metal oxide semiconductor field effect transistors MOSFETs) through an enable signal. When the enable signal is a low voltage, the gate drive circuit charges the power device, and the magnitude of the charging current depends on the on resistance of the P-channel MOS transistor and the magnitude of the gate drive resistor; when the enable signal is a high voltage, the power device discharges to the ground through the transistor of the gate drive circuit, and the magnitude of the discharge current depends on the on resistance of the N-channel MOS transistor and the magnitude of the off resistance.

[0004] Therefore, the current gate drive circuit, no matter what kind of power device is connected to it, has a fixed charging current for the power device and a fixed discharge current for the power device. However, in practice, there may be various factors that cause the gate drive circuit to be mismatched with the power device. In this case, using the current gate drive circuit will result in problems such as inappropriate charging and discharging currents, and charging and discharging that are too fast or too slow. Summary of the invention

[0005] The present application is proposed to solve the above problems. According to one aspect of the present application, a gate drive circuit is provided, the gate drive circuit comprising:

[0006] A discharge circuit, the discharge circuit comprising:

[0007] A first constant current reference generating circuit, used for outputting an adjustable first current;

[0008] A first current mirror circuit, configured to output a second current based on the first current;

[0009] a first output stage circuit, configured to operate based on the second current so that a third current outputted by the power device to the first output stage circuit is adjustable;

[0010] A charging circuit, the charging circuit comprising:

[0011] A second constant current reference generating circuit, used for outputting an adjustable fourth current;

[0012] a second current mirror circuit, configured to output a fifth current based on the fourth current;

[0013] The second output stage circuit is configured to operate based on the fifth current so that a sixth current output by the second output stage circuit to the power device is adjustable, wherein the power device is connected to the output end of the first output stage circuit and the output end of the second output stage circuit.

[0014] The above technical solution has the following technical effects: the constant current reference generating circuit outputs an adjustable current, and the current is still an adjustable current after being copied by the current mirror circuit. The adjustable current is used in the output stage circuit, so that the current of the output stage circuit is adjustable, that is, the charging current and the discharging current are adjustable. Therefore, in the case of a mismatch between the power device and the gate drive circuit, the power device can be matched by adjusting the charging current and / or the discharging current.

[0015] In one embodiment of the present application,

[0016] The discharge circuit further comprises:

[0017] a first clamping circuit, connected between the first current mirror circuit and the first output stage circuit, configured to operate based on the second current, and whose output acts on the first output stage circuit; and / or

[0018] The charging circuit further comprises:

[0019] The second clamping circuit is connected between the second current mirror circuit and the second output stage circuit, and is used for operating based on the fifth current, and the output of the second clamping circuit acts on the second output stage circuit.

[0020] The above technical solution has the following technical effects: by adding a first clamping circuit between the first current mirror circuit and the first output stage circuit of the discharge circuit, it is possible to ensure that the voltage of the node between the first current mirror circuit and the first output stage circuit remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the first current mirror. Similarly, by adding a second clamping circuit between the second current mirror circuit and the second output stage circuit of the charging circuit, it is possible to ensure that the voltage of the node between the second current mirror circuit and the second output stage circuit remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the second current mirror.

[0021] In one embodiment of the present application,

[0022] The discharge circuit further comprises:

[0023] a first buffer circuit, connected between the first clamp circuit and the first output stage circuit, and configured to operate based on an output of the first clamp circuit, wherein the output of the first buffer circuit acts on the first output stage circuit; and / or

[0024] The charging circuit further comprises:

[0025] The second buffer circuit is connected between the second clamp circuit and the second output stage circuit and is used for operating based on the output of the second clamp circuit, and the output of the second buffer circuit acts on the second output stage circuit.

[0026] The above technical solution has the following technical effects: by adding a first buffer circuit between the first clamp circuit and the first output stage circuit of the discharge circuit, a greater driving capability can be provided for the output of the first clamp circuit, and at the same time, the gate and source voltages of the transistors of the first clamp circuit and the first buffer circuit are made consistent, thereby forming a current source. Similarly, by adding a second buffer circuit between the second clamp circuit and the second output stage circuit of the charging circuit, a greater driving capability can be provided for the output of the second clamp circuit, and at the same time, the gate and source voltages of the transistors of the second clamp circuit and the transistors of the second buffer circuit are made consistent, thereby forming a current source.

[0027] In one embodiment of the present application,

[0028] The charging circuit further comprises:

[0029] The third current mirror circuit is connected between the second current mirror circuit and the second clamp circuit, and is used to operate based on the fifth current, and the output of the third current mirror circuit serves as the input of the second clamp circuit.

[0030] The above technical solution has the following technical effects: by adding a third current mirror circuit between the second current mirror circuit and the second clamping circuit of the charging circuit, it can play a role in amplifying the current, so that the output stage circuit can provide a larger charging current to the power device.

[0031] In one embodiment of the present application,

[0032] The first constant current reference generating circuit and the second constant current reference generating circuit both include:

[0033] an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of an adjustable resistance element, and an output terminal thereof is connected to a gate of a transistor;

[0034] The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the adjustable resistance element;

[0035] The second end of the adjustable resistance element is grounded.

[0036] The above technical solution has the following technical effects: through the negative feedback of the operational amplifier, the voltage at the source of the transistor is equal to the reference voltage, so that the voltage across the adjustable resistance element is determined, and then the adjustable current value can be obtained by adjusting the resistance value of the adjustable resistance element. This technical solution realizes current regulation through internal components and is simple to operate.

[0037] In one embodiment of the present application,

[0038] The adjustable resistance element comprises:

[0039] A plurality of resistors are connected in series, wherein two ends of each resistor in at least some of the resistors are connected in parallel with a switch element, and each of the switch elements is controlled by a respective control signal.

[0040] The above technical solution has the following technical effects: by connecting a switch element in parallel to both ends of each of the partial resistors in the plurality of series-connected resistors, when the switch element is turned on, the resistor is equivalent to being short-circuited, that is, the resistance value of the adjustable resistor element is reduced; when the switch element is turned off, the resistor is not short-circuited, that is, the resistance value of the adjustable resistor element is increased. By connecting the switch element in parallel to both ends of at least part of the resistors, the technical solution can control the resistors separately, thereby conveniently achieving the effect of adjusting the current by the number of connected resistors.

[0041] In one embodiment of the present application,

[0042] The first constant current reference generating circuit and the second constant current reference generating circuit both include:

[0043] an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of a resistor element, and an output terminal thereof is connected to a gate of a transistor;

[0044] The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the resistor element;

[0045] The resistance element has a second end connected to the interface;

[0046] The interface is used to connect an external resistor.

[0047] The above technical solution has the following technical effects: through the negative feedback of the operational amplifier, the voltage at the source of the transistor is equal to the reference voltage, so that the voltage across the resistor element is determined, and then the external resistor is connected through the adjustment interface, and the change of the access resistance value is achieved by adjusting the external resistor, so that the adjustable current value can be obtained. This technical solution realizes current regulation by connecting the external resistor through the interface, which can reduce the internal components of the circuit, save costs, and improve the flexibility of current regulation.

[0048] In one embodiment of the present application, the first current mirror circuit and the second current mirror circuit both include:

[0049] an operational amplifier, wherein a positive input terminal is connected to the gate of the first transistor and the gate of the second transistor, a negative input terminal is connected to the drain of the second transistor and the source of the third transistor, and an output terminal is connected to the gate of the third transistor;

[0050] The first transistor has a source connected to a power supply signal and a drain connected to the corresponding constant current reference generating circuit;

[0051] The second transistor has a source connected to a power signal;

[0052] The drain of the third transistor serves as the output end of the current mirror circuit.

[0053] The above technical solution has the following technical effects: by adding an operational amplifier to the current mirror circuit, the problem of drain-source voltage difference can be solved, thereby ensuring the accuracy of the current mirror when copying the current.

[0054] In one embodiment of the present application, the first current mirror circuit and the second current mirror circuit both include:

[0055] The filter circuit is connected between the gate of the first transistor and the gate of the second transistor.

[0056] The above technical solution has the following technical effects: by adding a filter circuit in the current mirror circuit, the problem of drain-source voltage difference can be solved, thereby ensuring the accuracy of the current mirror when copying the current.

[0057] In one embodiment of the present application,

[0058] The first output stage circuit comprises:

[0059] a first operational amplifier, wherein a positive input terminal of the first operational amplifier is connected to the output terminal of the first current mirror circuit, a negative input terminal of the first operational amplifier is connected to the source of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor, and an output terminal of the first operational amplifier is connected to the gate of the fourth transistor;

[0060] The fourth transistor has a drain connected to the first end of the first resistor element;

[0061] The fifth transistor has a source connected to the ground and a gate connected to the output end of the first buffer circuit;

[0062] The sixth transistor has a source connected to the ground and a gate connected to the first control signal;

[0063] The first resistance element, a second end of the first resistance element is connected to the power device;

[0064] The second output stage circuit comprises:

[0065] a second operational amplifier, wherein a positive input terminal of the second operational amplifier is connected to the output terminal of the second current mirror circuit, a negative input terminal of the second operational amplifier is connected to the source of the seventh transistor, the drain of the eighth transistor and the drain of the ninth transistor, and an output terminal of the second operational amplifier is connected to the gate of the seventh transistor;

[0066] The seventh transistor has a drain connected to the first end of the second resistor element;

[0067] The eighth transistor has a source connected to a power supply and a gate connected to an output end of the second buffer circuit;

[0068] The ninth transistor has a source connected to the power supply and a gate connected to the second control signal;

[0069] The second resistance element, a second end of the second resistance element is connected to the power device.

[0070] The above technical solution has the following technical effects: by adding an operational amplifier to the output stage circuit, the problem of the source-drain voltage difference between the transistors of the clamp circuit and the transistors of the buffer circuit can be eliminated, thereby improving the accuracy of the current mirror. In addition, the on and off of the transistors in the output stage circuit can be controlled, that is, the operation or shutdown of the discharge circuit and the charging circuit can be controlled, thereby eliminating the need to provide additional control signals.

[0071] According to another aspect of the present application, a gate driving circuit is further provided, the gate driving circuit comprising:

[0072] A first constant current reference generating circuit, used for outputting an adjustable first current;

[0073] A first current mirror circuit, configured to output a second current based on the first current;

[0074] a first output stage circuit, configured to operate based on the second current so that a third current outputted by the power device to the first output stage circuit is adjustable;

[0075] The second output stage circuit is used to operate based on the second current so that a fourth current output by the second output stage circuit to the power device is adjustable, wherein the power device is connected to the output end of the first output stage circuit and the output end of the second output stage circuit.

[0076] The above technical solution has the following technical effects: the constant current reference generating circuit outputs an adjustable current, and the current is still an adjustable current after being copied by the current mirror circuit. The adjustable current is used in the output stage circuit, so that the current of the output stage circuit can be adjusted, that is, the charging current and the discharging current can be adjusted synchronously. Therefore, in the case of mismatch between the power device and the gate drive circuit, the power device can be matched by adjusting the charging current and / or the discharging current.

[0077] In one embodiment of the present application, the gate drive circuit further includes:

[0078] a first clamping circuit, connected between the first current mirror circuit and the first output stage circuit, configured to operate based on the second current, and whose output acts on the first output stage circuit; and / or

[0079] The second clamping circuit is connected between the first current mirror circuit and the second output stage circuit, and is used for operating based on the second current, and the output of the second clamping circuit acts on the second output stage circuit.

[0080] The above technical solution has the following technical effects: by adding a first clamping circuit between the first current mirror circuit and the first output stage circuit, it is possible to ensure that the voltage of the node between the first current mirror circuit and the first output stage circuit remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the first current mirror. Similarly, by adding a second clamping circuit between the first current mirror circuit and the second output stage circuit, it is possible to ensure that the voltage of the node between the first current mirror circuit and the second output stage circuit remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the first current mirror.

[0081] In one embodiment of the present application, the gate drive circuit further includes:

[0082] a first buffer circuit, connected between the first clamp circuit and the first output stage circuit, and configured to operate based on an output of the first clamp circuit, wherein the output of the first buffer circuit acts on the first output stage circuit; and / or

[0083] The second buffer circuit is connected between the second clamp circuit and the second output stage circuit and is used for operating based on the output of the second clamp circuit, and the output of the second buffer circuit acts on the second output stage circuit.

[0084] The above technical solution has the following technical effects: by adding a first buffer circuit between the first clamp circuit and the first output stage circuit, a greater driving capability can be provided for the output of the first clamp circuit, and at the same time, the gate and source voltages of the transistors of the first clamp circuit and the first buffer circuit are made consistent, thereby forming a current source. Similarly, by adding a second buffer circuit between the second clamp circuit and the second output stage circuit, a greater driving capability can be provided for the output of the second clamp circuit, and at the same time, the gate and source voltages of the transistors of the second clamp circuit and the transistors of the second buffer circuit are made consistent, thereby forming a current source.

[0085] In one embodiment of the present application, the gate drive circuit further includes:

[0086] The second current mirror circuit is connected between the first current mirror circuit and the second clamp circuit and is used to operate based on the second current, and the output of the second current mirror circuit serves as the input of the second clamp circuit.

[0087] The above technical solution has the following technical effects: by adding a second current mirror circuit between the first current mirror circuit and the second clamping circuit, the current can be amplified, so that the output stage circuit can provide a larger charging current to the power device.

[0088] In one embodiment of the present application, the first constant current reference generating circuit comprises:

[0089] an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of an adjustable resistance element, and an output terminal thereof is connected to a gate of a transistor;

[0090] The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the adjustable resistance element;

[0091] The second end of the adjustable resistance element is grounded.

[0092] The above technical solution has the following technical effects: through the negative feedback of the operational amplifier, the voltage at the source of the transistor is equal to the reference voltage, so that the voltage across the adjustable resistance element is determined, and then the adjustable current value can be obtained by adjusting the resistance value of the adjustable resistance element. This technical solution realizes current regulation through internal components and is simple to operate.

[0093] In one embodiment of the present application, the adjustable resistance element includes:

[0094] A plurality of resistors are connected in series, wherein two ends of each resistor in at least some of the resistors are connected in parallel with a switch element, and each of the switch elements is controlled by a respective control signal.

[0095] The above technical solution has the following technical effects: by connecting a switch element in parallel to both ends of each of the partial resistors in the plurality of series-connected resistors, when the switch element is turned on, the resistor is equivalent to being short-circuited, that is, the resistance value of the adjustable resistor element is reduced; when the switch element is turned off, the resistor is not short-circuited, that is, the resistance value of the adjustable resistor element is increased. By connecting the switch element in parallel to both ends of at least part of the resistors, the technical solution can control the resistors separately, thereby conveniently achieving the effect of adjusting the current by the number of connected resistors.

[0096] In one embodiment of the present application, the first constant current reference generating circuit comprises:

[0097] an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of a resistor element, and an output terminal thereof is connected to a gate of a transistor;

[0098] The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the resistor element;

[0099] The resistance element has a second end connected to the interface;

[0100] The interface is used to connect an external resistor.

[0101] The above technical solution has the following technical effects: through the negative feedback of the operational amplifier, the voltage at the source of the transistor is equal to the reference voltage, so that the voltage across the resistor element is determined, and then the external resistor is connected through the adjustment interface, and the change of the access resistance value is achieved by adjusting the external resistor, so that the adjustable current value can be obtained. This technical solution realizes current regulation by connecting the external resistor through the interface, which can reduce the internal components of the circuit, save costs, and improve the flexibility of current regulation.

[0102] In one embodiment of the present application, the first current mirror circuit includes:

[0103] an operational amplifier, wherein a positive input terminal is connected to the gate of the first transistor and the gate of the second transistor, a negative input terminal is connected to the drain of the second transistor and the source of the third transistor, and an output terminal is connected to the gate of the third transistor;

[0104] The first transistor has a source connected to a power supply signal and a drain connected to the corresponding constant current reference generating circuit;

[0105] The second transistor has a source connected to a power signal;

[0106] The drain of the third transistor serves as the output end of the current mirror circuit.

[0107] The above technical solution has the following technical effects: by adding an operational amplifier to the current mirror circuit, the problem of drain-source voltage difference can be solved, thereby ensuring the accuracy of the current mirror when copying the current.

[0108] In one embodiment of the present application, the first current mirror circuit further includes:

[0109] The filter circuit is connected between the gate of the first transistor and the gate of the second transistor.

[0110] The above technical solution has the following technical effects: by adding a filter circuit in the current mirror circuit, the problem of drain-source voltage difference can be solved, thereby ensuring the accuracy of the current mirror when copying the current.

[0111] In one embodiment of the present application,

[0112] The first output stage circuit comprises:

[0113] a first operational amplifier, wherein a positive input terminal of the first operational amplifier is connected to the output terminal of the first current mirror circuit, a negative input terminal of the first operational amplifier is connected to the source of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor, and an output terminal of the first operational amplifier is connected to the gate of the fourth transistor;

[0114] The fourth transistor has a drain connected to the first end of the first resistor element;

[0115] The fifth transistor has a source connected to the ground and a gate connected to the output end of the first buffer circuit;

[0116] The sixth transistor has a source connected to the ground and a gate connected to the first control signal;

[0117] The first resistance element, a second end of the first resistance element is connected to the power device;

[0118] The second output stage circuit comprises:

[0119] a second operational amplifier, wherein a positive input terminal of the second operational amplifier is connected to the output terminal of the second current mirror circuit, a negative input terminal of the second operational amplifier is connected to the source of the seventh transistor, the drain of the eighth transistor and the drain of the ninth transistor, and an output terminal of the second operational amplifier is connected to the gate of the seventh transistor;

[0120] The seventh transistor has a drain connected to the first end of the second resistor element;

[0121] The eighth transistor has a source connected to a power supply and a gate connected to an output end of the second buffer circuit;

[0122] The ninth transistor has a source connected to the power supply and a gate connected to the second control signal;

[0123] The second resistance element, a second end of the second resistance element is connected to the power device.

[0124] The above technical solution has the following technical effects: by adding an operational amplifier to the output stage circuit, the problem of the source-drain voltage difference between the transistors of the clamp circuit and the transistors of the buffer circuit can be eliminated, thereby improving the accuracy of the current mirror. In addition, the on and off of the transistors in the output stage circuit can be controlled, that is, the operation or shutdown of the discharge circuit and the charging circuit can be controlled, thereby eliminating the need to provide additional control signals.

[0125] According to another aspect of the present application, a gate driving chip is provided, and the gate driving chip includes the above-mentioned gate driving circuit.

[0126] According to another aspect of the present application, an electronic device is provided, comprising the above-mentioned gate driving chip.

[0127] According to the gate drive circuit, gate drive chip and electronic device of the embodiments of the present application, it is possible to provide adjustable charge and discharge currents, so that when there is a mismatch between the power device and the gate drive circuit, the power device can be matched by adjusting the charge current and / or discharge current. BRIEF DESCRIPTION OF THE DRAWINGS

[0128] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0129] Figure 1 A circuit diagram showing an output stage circuit portion of a conventional gate drive circuit.

[0130] Figure 2 A schematic structural block diagram of a gate driving circuit according to an embodiment of the present application is shown.

[0131] Figure 3 A schematic structural block diagram of a gate driving circuit according to another embodiment of the present application is shown.

[0132] Figure 4 A schematic structural block diagram of a gate driving circuit according to another embodiment of the present application is shown.

[0133] Figure 5 A schematic structural block diagram of a gate driving circuit according to yet another embodiment of the present application is shown.

[0134] Figure 6A schematic circuit diagram of a first constant current reference generating circuit according to an embodiment of the present application is shown.

[0135] Figure 7 A schematic circuit diagram of a first constant current reference generating circuit according to another embodiment of the present application is shown.

[0136] Figure 8 A schematic circuit diagram of a first current mirror circuit according to an embodiment of the present application is shown.

[0137] Fig. 9 A schematic circuit diagram of a first clamping circuit according to an embodiment of the present application is shown.

[0138] Fig.10 A schematic circuit diagram of a first buffer circuit according to an embodiment of the present application is shown.

[0139] Fig.11 A schematic circuit diagram of a first output stage circuit according to an embodiment of the present application is shown.

[0140] Fig.12 An exemplary circuit diagram of a gate driving circuit according to an embodiment of the present application is shown.

[0141] Fig.13 An exemplary circuit diagram of a gate driving circuit according to another embodiment of the present application is shown.

[0142] Fig.14 An exemplary circuit diagram of a gate driving circuit according to yet another embodiment of the present application is shown.

[0143] Fig.15 A schematic structural block diagram of a gate driving circuit according to another embodiment of the present application is shown.

[0144] Fig.16 An exemplary circuit diagram of a gate driving circuit according to yet another embodiment of the present application is shown. DETAILED DESCRIPTION

[0145] In order to make the purpose, technical solutions and advantages of the present application more obvious, the example embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0146] Figure 1 FIG. 2 shows a circuit diagram of an output stage circuit portion of a conventional gate drive circuit. Figure 1As shown in Figure 1, the enable signal EN controls the on and off of the power device Q1. When EN is a low voltage, the PM tube is turned on and the NM tube is turned off. The gate drive circuit charges the power device Q1, and the charging current I c The size of depends on the on-resistance of PM and the size of the gate drive resistance. When EN is a high voltage, the PM tube is cut off and the NM tube is turned on. The power device Q1 discharges to the ground through the NM tube of the gate drive circuit. The discharge current I disc The size of Rgoff depends on the on-resistance and off-resistance Rgoff of the NM tube.

[0147] exist Figure 1 In the gate drive circuit shown in FIG. 1 , no matter what power device is connected to it, the charging current of the power device and the discharge current of the power device to it are fixed. However, in practice, there may be various factors that cause the gate drive circuit and the power device to be mismatched. In this case, Figure 1 The gate drive circuit shown cannot provide appropriate charge and discharge current, resulting in too fast or too slow charge and discharge.

[0148] Based on this, the present application provides a new gate drive circuit solution. Figures 2 to 12 to describe.

[0149] Figure 2 FIG. 1 shows a schematic structural block diagram of a gate drive circuit 1 according to an embodiment of the present application. Figure 2 As shown, the gate drive circuit 1 may include a discharge circuit 11 and a charging circuit 12. The discharge circuit 11 includes a first constant current reference generating circuit 111, a first current mirror circuit 112 and a first output stage circuit 113 connected in sequence. The output end of the first output stage circuit 113 and the output end of the second output stage circuit 123 are connected to a power device (not shown). The first constant current reference generating circuit 111 is used to output an adjustable first current. The first current mirror circuit 112 is used to output a second current based on the first current. The first output stage circuit 113 is used to operate based on the second current so that the third current (i.e., the discharge current) output by the power device to the first output stage circuit 113 is adjustable. The charging circuit 12 includes a second constant current reference generating circuit 121, a second current mirror circuit 122 and a second output stage circuit 123 connected in sequence. The second constant current reference generating circuit 121 is used to output an adjustable fourth current. The second current mirror circuit 122 is used to output a fifth current based on the fourth current. The second output stage circuit 123 is configured to operate based on the fifth current, so that the sixth current (ie, the charging current) output by the second output stage circuit 123 to the power device is adjustable.

[0150] In an embodiment of the present application, the discharge circuit 11 and the charging circuit 12 of the gate drive circuit 1 both include a constant current reference generating circuit capable of outputting an adjustable current, and also include a current mirror circuit capable of replicating the adjustable current output by the constant current reference generating circuit. Since the constant current reference generating circuit can output an adjustable current, the current is still an adjustable current after being replicated by the current mirror circuit, and the adjustable current is used in the output stage circuit, so that the current of the output stage circuit is adjustable, that is, the charging current and the discharging current can be independently adjusted, so that in the case of a mismatch between the power device and the gate drive circuit, the power device can be matched by adjusting the charging current and / or the discharging current, thereby solving the problem of too fast or too slow charging and discharging when the gate drive circuit does not match the power device.

[0151] In a further embodiment of the present application, the discharge circuit 11 may further include a first clamping circuit 114 (not shown in Figure 2 It is shown in Figure 3 As shown in FIG. 1 , the first clamping circuit 114 is connected between the first current mirror circuit 112 and the first output stage circuit 113 and is configured to operate based on the second current, and its output acts on the first output stage circuit 113.

[0152] In this embodiment, by adding a first clamping circuit 114 between the first current mirror circuit 112 and the first output stage circuit 113 of the discharge circuit 11, it is possible to ensure that the voltage of the node between the first current mirror circuit 112 and the first output stage circuit 113 remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the first current mirror.

[0153] Similarly, the charging circuit 12 may further include a second clamping circuit 124 (not shown). Figure 2 It is shown in Figure 3 As shown in FIG. 1 , the second clamping circuit 124 is connected between the second current mirror circuit 122 and the second output stage circuit 123 and is configured to operate based on the fifth current, and its output acts on the second output stage circuit 123.

[0154] In this embodiment, by adding a second clamping circuit 124 between the second current mirror circuit 122 and the second output stage circuit 123 of the charging circuit 12, it is possible to ensure that the voltage of the node between the second current mirror circuit 122 and the second output stage circuit 123 remains unchanged, and its equivalent capacitance to ground does not need to be charged or discharged, thereby improving the turn-on speed of the second current mirror.

[0155] Since the charging circuit 12 and the discharging circuit 11 are independent of each other, either the first clamping circuit 114 or the second clamping circuit 124 may be present in the gate driving circuit, or both of them may be present in the gate driving circuit. Figure 3That is, an embodiment in which both exist is shown. Figure 2 The illustrated embodiment distinguishes between Figure 3 The gate drive circuit in the embodiment shown is named gate drive circuit 2. Figure 2 Compared with the gate drive circuit 1 shown in the figure, clamping circuits are added in the charging circuit 12 and the discharging circuit 11. As mentioned above, the gate drive circuit 2 can not only solve the problem of too fast or too slow charging and discharging when the gate drive circuit does not match the power device, but also further improve the opening speed of the current mirror in its charging circuit 12 and the discharging circuit 11, thereby improving the operating speed of the entire circuit.

[0156] In a further embodiment of the present application, the discharge circuit 11 may further include a first buffer circuit 115 (not shown in Figure 3 It is shown in Figure 4 As shown in FIG. 1 , the first buffer circuit 115 is connected between the first clamp circuit 114 and the first output stage circuit 113 and is used to operate based on the output of the first clamp circuit 114, and its output acts on the first output stage circuit 113.

[0157] In this embodiment, by adding a first buffer circuit 115 between the first clamp circuit 114 and the first output stage circuit 113 of the discharge circuit 11, a greater driving capability can be provided for the output of the first clamp circuit 114, and at the same time, the gate and source voltages of the transistors of the first clamp circuit 114 and the first buffer circuit 115 are made consistent to form a current source, thereby better replicating the current.

[0158] Similarly, the charging circuit 12 may further include a second buffer circuit 125 (not shown). Figure 3 It is shown in Figure 4 As shown in FIG. 1 , the second buffer circuit 125 is connected between the second clamping circuit 124 and the second output stage circuit 123 and is used to operate based on the output of the second clamping circuit 124, and its output acts on the second output stage circuit 123.

[0159] In this embodiment, by adding a second buffer circuit 125 between the second clamp circuit 124 and the second output stage circuit 123 of the charging circuit 12, a greater driving capability can be provided for the output of the second clamp circuit 124, while making the gate and source voltages of the transistors of the second clamp circuit 124 and the transistors of the second buffer circuit 125 consistent to form a current source, thereby better replicating the current.

[0160] Since the charging circuit 12 and the discharging circuit 11 are independent of each other, either the first buffer circuit 115 or the second buffer circuit 125 can be present in the gate driving circuit, or both can be present in the gate driving circuit. Figure 4That is, an embodiment in which both exist is shown. Figure 3 The illustrated embodiment distinguishes between Figure 4 The gate drive circuit in the embodiment shown is named gate drive circuit 3. Figure 3 Compared with the gate drive circuit 2 shown in the figure, a buffer circuit is added to the charging circuit 12 and the discharging circuit 11. As mentioned above, the gate drive circuit 3 can not only solve the problem of too fast or too slow charging and discharging when the gate drive circuit does not match the power device, but also improve the opening speed of the current mirror in the charging circuit 12 and the discharging circuit 11, thereby improving the operating speed of the entire circuit, but also can further provide a greater driving capability for the gate drive circuit, and improve the accuracy of current replication, so as to more accurately control the current.

[0161] In a further embodiment of the present application, the charging circuit 12 may further include a third current mirror circuit 126 (not shown in FIG. Figure 4 It is shown in Figure 5 As shown in FIG. 1 , the third current mirror circuit 126 is connected between the second current mirror circuit 122 and the second clamp circuit 124 for operating based on the fifth current, and its output serves as the input of the second clamp circuit 124.

[0162] In this embodiment, by adding a third current mirror circuit 126 between the second current mirror circuit 122 and the second clamp circuit 124 of the charging circuit 12, the current can be amplified, so that the output stage circuit can provide a larger charging current to the power device. Figure 5 That is, the example in which the charging circuit 12 of the gate driving circuit includes a third current circuit is shown. Figure 4 The illustrated embodiment distinguishes between Figure 5 The gate drive circuit in the embodiment shown is named gate drive circuit 4. Figure 4 Compared with the gate drive circuit 3 shown in the figure, a third current mirror circuit 126 is added to the charging circuit 12. As mentioned above, the gate drive circuit 4 can not only solve the problem of too fast or too slow charging and discharging when the gate drive circuit does not match the power device, but also improve the opening speed of the current mirror in the charging circuit 12 and the discharging circuit 11, thereby improving the operation speed of the entire circuit, and at the same time provide a greater driving capability for the gate drive circuit, and improve the accuracy of current replication, so as to more accurately control the current, and can further provide a larger charging current to more flexibly meet the needs of power devices.

[0163] In an embodiment of the present application, the first constant current reference generating circuit 111 and the second constant current reference generating circuit 121 described above may both include an operational amplifier, a transistor and an adjustable resistance element. Among them, the positive input terminal of the operational amplifier is connected to the reference signal, the negative input terminal is connected to the first end of the adjustable resistance element, and the output terminal is connected to the gate of the transistor. The drain of the transistor is connected to the corresponding current mirror circuit (here, "the drain of the transistor is connected to the corresponding current mirror circuit" can be understood as: the drain of the transistor in the first constant current reference generating circuit 111 is connected to the first current mirror circuit 112, and the drain of the transistor in the second constant current reference generating circuit 121 is connected to the second current mirror circuit 122), and the source is connected to the first end of the adjustable resistance element; the second end of the adjustable resistance element is grounded GND. The following is combined with Figure 6 To describe, Figure 6 An example of the first constant current reference generating circuit 111 is shown in FIG. 1 . It should be understood that the second constant current reference generating circuit 121 also has a similar structure. For the sake of brevity, it is not shown and described again.

[0164] like Figure 6 As shown, the first constant current reference generating circuit 111 includes an operational amplifier AMP1, a transistor NM1 and an adjustable resistance element. Among them, the adjustable resistance element includes a plurality of resistors connected in series, shown as R1, R2, R3...Rn-1, Rn. Among them, a switch tube is connected in parallel at both ends of each resistor from R2 to Rn-1, and its gate is controlled by a respective control signal S1, S2...Sx. The positive input terminal of AMP1 is connected to the reference signal VREF (wherein VREF can be provided by a bandgap reference circuit), and the negative input terminal is connected to one end of R1, R1 to Rn are connected in series, one end of Rn is connected to Rn-1, and the other end is grounded. The output end of AMP1 is connected to the gate of NM1, and the drain of NM1 is connected to the first current mirror circuit 112 (not shown). Figure 6 ).

[0165] according to Figure 6In the structure shown, the control signals S1, S2...Sx are control signals of the resistance from point A to ground, and the number of resistors connected to the circuit can be selected. When the VREF input is valid, the first constant current reference generating circuit 111 uses the negative feedback of the operational amplifier AMP1 to make the voltage at point A equal to VREF, and the current flowing through NM1 is I1. Then, by selecting S1~Sx, the number of load resistors connected to the circuit can be determined, thereby adjusting the resistance value from point A to ground. Let the resistance value from point A to ground be Rs, then when the S1~Sx signals are all high level, the load resistance at point A is Rs=R1+Rn. When the S1~Sx signals are all low level, Rs=R1+R2+R3+...+Rn-1+Rn. Assuming that the resistance of R1~Rn is R, that is, the minimum value of Rs is Rs=2R, and the maximum value of Rs=nR. It can be concluded from I1=VREF / Rs that I1 is inversely proportional to Rs. Therefore, the first constant current reference generating circuit 111 adjusts the resistance of the connected load resistor Rs to achieve the effect of adjusting the current.

[0166] In this embodiment, through the negative feedback of the operational amplifier AMP1, the voltage at the source of the transistor (i.e., the voltage at point A) is equal to the reference voltage VREF, so that the voltage across the adjustable resistance elements R1 to Rn is determined, and then the adjustable current value can be obtained by adjusting the resistance value of the adjustable resistance element. This technical solution realizes current regulation through internal components and is simple to operate.

[0167] In another embodiment of the present application, the first constant current reference generating circuit 111 and the second constant current reference generating circuit 121 described above may both include an operational amplifier, a transistor, a resistor element, and an interface. Among them, the positive input terminal of the operational amplifier is connected to the reference signal, the negative input terminal is connected to the first end of the resistor element, and the output terminal is connected to the gate of the transistor. The drain of the transistor is connected to the corresponding current mirror circuit (here, "the drain of the transistor is connected to the corresponding current mirror circuit" can be understood as: the drain of the transistor in the first constant current reference generating circuit 111 is connected to the first current mirror circuit 112, and the drain of the transistor in the second constant current reference generating circuit 121 is connected to the second current mirror circuit 122), and the source is connected to the first end of the resistor element. The second end of the resistor element is connected to the interface. The interface is used to connect an external resistor. The following is combined with Figure 7 To describe, Figure 7 Another example of the first constant current reference generating circuit 111 is shown in FIG. 1 . It should be understood that the second constant current reference generating circuit 121 also has a similar structure. For the sake of brevity, it is not shown and described again.

[0168] like Figure 7As shown, the first constant current reference generating circuit 111 includes an operational amplifier AMP1, a transistor NM1 and a resistor element R1. The positive input terminal of AMP1 is connected to the reference signal VREF, the negative input terminal is connected to one end of R1, and the other end of R1 is connected to an interface, which can be used to connect an external resistor. The output terminal of AMP1 is connected to the gate of NM1, and the drain of NM1 is connected to the first current mirror circuit 112 (not shown). Figure 7 ).

[0169] according to Figure 7 In the structure shown, when the VREF input is valid, the first constant current reference generating circuit 111 uses the negative feedback effect of the operational amplifier AMP1 to make the voltage at point A equal to VREF, and the current flowing through NM1 is I1, and then the load connected to the circuit is determined by selecting the number and / or size of the external resistors, thereby adjusting the resistance value from point A to ground. Let the resistance value from point A to ground be Rs, then the load resistance at point A, i.e., Rs min value, is Rs=R1, and Rs max=R1+value of the external resistor. It is obtained from I1=VREF / Rs that I1 is inversely proportional to Rs. Therefore, the first constant current reference generating circuit 111 achieves the effect of adjusting the current by adjusting the resistance value of the connected load resistor Rs.

[0170] In this embodiment, the voltage at the source of the transistor (i.e., the voltage at point A) is equal to the reference voltage VREF through the negative feedback of the operational amplifier AMP1, so that the voltage across the resistor element R1 is determined, and then the external resistor is connected through the interface, and the change of the access resistance value is achieved by adjusting the external resistor, so that the adjustable current value can be obtained. This technical solution realizes current regulation by connecting the external resistor through the interface, which can reduce the internal components of the circuit, save costs, and improve the flexibility of current regulation, because any number and size of external resistors can be connected as needed.

[0171] In an embodiment of the present application, the first current mirror circuit 112 and the second current mirror circuit 122 described above may both include an operational amplifier, a first transistor, a second transistor, and a third transistor. Wherein, the positive input terminal of the operational amplifier is connected to the gate of the first transistor and the gate of the second transistor, the negative input terminal is connected to the drain of the second transistor and the source of the third transistor, and the output terminal is connected to the gate of the third transistor. The source of the first transistor is connected to the power supply signal, and the drain is connected to the corresponding constant current reference generating circuit (here, "the drain of the first transistor is connected to the corresponding constant current reference generating circuit" can be understood as: the drain of the transistor in the first current mirror circuit 112 is connected to the first constant current reference generating circuit 111, and the drain of the transistor in the second current mirror circuit 122 is connected to the second constant current reference generating circuit 121). The source of the second transistor is connected to the power supply signal. The drain of the third transistor serves as the output end of the corresponding current mirror circuit (here, "the drain of the third transistor serves as the output end of the corresponding current mirror circuit" can be understood as: the drain of the transistor in the first current mirror circuit 112 serves as the output end of the first current mirror circuit 112, and the drain of the transistor in the second current mirror circuit 122 serves as the output end of the second current mirror circuit 122). Figure 8 To describe, Figure 8 An example of the first current mirror circuit 112 is shown in FIG. 1 . It should be understood that the second current mirror circuit 122 also has a similar structure. For the sake of brevity, it is not shown and described again.

[0172] like Figure 8 As shown, the first current mirror circuit 112 includes an operational amplifier AMP2, transistors PM1, PM2 and PM3. The positive input terminal of the operational amplifier AMP2 is connected to the gate of PM1 and the gate of PM2, the negative input terminal is connected to the drain of PM2 and the source of PM3, and the output terminal is connected to the gate of PM3. The source of PM1 is connected to the power signal, and the drain is connected to the first constant current reference generating circuit 111. The source of PM2 is connected to the power signal. The drain of PM3 serves as the output terminal of the first current mirror circuit 112.

[0173] according to Figure 8 The structure shown in FIG. 1 is a current mirror circuit that can convert the reference current (such as Figure 6 The current I1 shown in FIG. 1 is perfectly copied and output as I2. Generally, a general current mirror will cause a significant error in the mirrored current due to the difference in drain-source voltage between the pair of tubes PM1 and PM2. In this embodiment, this problem can be solved by the operational amplifier circuit AMP2. Specifically, AMP2 stabilizes the voltage at point C at the voltage at point B through negative feedback, so that the voltages at the drain, source, and gate of PM1 and PM2 are the same, thus solving the problem of the difference in drain-source voltage, thereby ensuring the accuracy of the current mirror when copying the current.

[0174] Further, optionally, the first current mirror circuit 112 may also include a filter circuit, for example Figure 8 The two-stage low-pass RC filter circuit composed of RA, RB, CA, and CB is connected between the gate of PM1 and the gate of PM2. The filter circuit can filter out high-frequency noise in the reference voltage and reduce the error of the output circuit.

[0175] In other embodiments, Figure 8 In the current mirror circuit shown, AMP2 and two sets of filtering RC are removed. Although this will affect the current accuracy, it can save chip area.

[0176] In an embodiment of the present application, the first clamp circuit 114 and the second clamp circuit 124 described above may both include an operational amplifier and a transistor. Among them, the positive input terminal of the operational amplifier is connected to the drain of the transistor, the negative input terminal is connected to the reference signal, and the output terminal is connected to the gate of the transistor. The source of the transistor is grounded, and the drain is connected to the output terminal of the corresponding current mirror circuit (here, "the drain of the transistor is connected to the output terminal of the corresponding current mirror circuit" can be understood as: the drain of the transistor in the first clamp circuit 114 is connected to the output terminal of the first current mirror circuit 112, and the drain of the transistor in the second clamp circuit 124 is connected to the output terminal of the second current mirror circuit 122). The following is combined with Fig. 9 to describe. Fig. 9 An example of the first clamping circuit 114 is shown in FIG. 1 . It should be understood that the second clamping circuit 124 also has a similar structure, which is not shown or described again for the sake of brevity.

[0177] like Fig. 9 As shown, the first clamping circuit 114 includes an operational amplifier AMP3 and a transistor NM2. Among them, the positive input terminal of AMP3 is connected to the drain of NM2, the negative input terminal is connected to the reference signal VREF1, and the output terminal is connected to the gate of NM2. The source of NM2 is grounded, and the drain is connected to the output terminal of the first current mirror circuit 112. The clamping circuit composed of AMP3 and NM2 can make the source-drain voltage of NM2 equal to VREF1 through the negative feedback of the operational amplifier (wherein VREF1 can be provided by a bandgap reference circuit, and VREF1 can be a voltage division of VREF described above, and VREF2 to be described below can also be a voltage division of VREF). VREF1 is a relatively low voltage, and the clamping circuit can make NM2 work stably in the saturation region and the power consumption of normal conduction operation is relatively low.

[0178] In an embodiment of the present application, the first buffer circuit 115 and the second buffer circuit 125 described above may both include an operational amplifier, whose positive input terminal may be connected to the output terminal of the corresponding clamp circuit (here, "the positive input terminal may be connected to the output terminal of the corresponding clamp circuit" may be understood as: the positive input terminal of the operational amplifier in the first buffer circuit 115 is connected to the output terminal of the first clamp circuit 114, and the positive input terminal of the operational amplifier in the second buffer circuit 125 is connected to the output terminal of the second clamp circuit 124), and the negative input terminal is connected to the corresponding output stage circuit (here, "the negative input terminal is connected to the corresponding output stage circuit" may be understood as: the negative input terminal of the operational amplifier in the first buffer circuit 115 is connected to the first output stage circuit 113, and the negative input terminal of the operational amplifier in the second buffer circuit 125 is connected to the second output stage circuit 123). In combination with Fig.10 to describe. Fig.10 An example of the first buffer circuit 115 is shown in FIG. 1 . It should be understood that the second buffer circuit 125 also has a similar structure. For the sake of brevity, it is not shown and described again.

[0179] like Fig.10 As shown, the first buffer circuit 115 includes an operational amplifier AMP4, wherein its positive input terminal is connected to the output terminal of the first clamp circuit 114, its negative input terminal is connected to the output terminal, and the output terminal is connected to the first output stage circuit 113. Exemplarily, the gain of the first buffer circuit 115 is 1, which can provide a greater driving capability for the output of the first clamp circuit 114 (such as the output of AMP3 described above).

[0180] In an embodiment of the present application, the first output stage circuit 113 described above includes: a first operational amplifier, a fourth transistor, a fifth transistor, a sixth transistor and a first resistor element. Among them, the positive input terminal of the first operational amplifier is connected to the output terminal of the first current mirror circuit, the negative input terminal is connected to the source of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor, and the output terminal is connected to the gate of the fourth transistor; the drain of the fourth transistor is connected to the first end of the first resistor element; the source of the fifth transistor is grounded, and the gate is connected to the output terminal of the first buffer circuit; the source of the sixth transistor is grounded, and the gate is connected to the first control signal; the second end of the first resistor element is connected to the power device. The second output stage circuit 123 includes a second operational amplifier, a seventh transistor, an eighth transistor, a ninth transistor and a second resistor element. The positive input terminal of the second operational amplifier is connected to the output terminal of the second current mirror circuit, the negative input terminal is connected to the source of the seventh transistor, the drain of the eighth transistor and the drain of the ninth transistor, and the output terminal is connected to the gate of the seventh transistor; the drain of the seventh transistor is connected to the first terminal of the second resistor element; the source of the eighth transistor is connected to the power supply, and the gate is connected to the output terminal of the second buffer circuit; the source of the ninth transistor is connected to the power supply, and the gate is connected to the second control signal; the second terminal of the second resistor element is connected to the power device. Fig.11 To describe, Fig.11 An example of the first output stage circuit 113 is shown in FIG. 1 . It should be understood that the second output stage circuit 123 also has a similar structure. For the sake of brevity, it is not shown and described again.

[0181] like Fig.11 As shown, the first output stage circuit 113 includes an operational amplifier AMP5, transistors NM3, NM4, NM5 and a resistor element Rgoff. Among them, the positive input terminal of the operational amplifier AMP5 is connected to the output terminal of the first current mirror circuit 112, the negative input terminal is connected to the source of NM4, the drain of NM3 and the drain of NM5, and the output terminal is connected to the gate of NM4. The drain of NM4 is connected to the first end of the resistor element Rgoff. The source of NM3 is grounded, and the gate is connected to the output terminal of the first buffer circuit 115. The source of NM5 is grounded, and the gate is connected to the pull-down signal PDN. The second end of the resistor element Rgoff is connected to the power device.

[0182] according to Fig.11In the structure shown, the first output stage circuit 113 and the first clamping circuit 114 shown above constitute a current mirror. Due to the action of the first clamping circuit 114, the voltage of the node D remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the opening speed of the current mirror. One of the functions of AMP5 is to make the voltage at point E equal to the voltage at point D through negative feedback, thereby eliminating the problem of the difference in drain-source voltage of the current mirror tubes NM2 and NM3, and improving the accuracy of the current mirror; another function is to control the opening and closing of the NM4 tube of the output stage circuit, that is, to control the operation or closing of the discharge circuit 11, so that there is no need to provide an additional control signal.

[0183] The above exemplary describes the detailed structure of each circuit in the gate drive circuit according to the embodiment of the present application. Figure 12 to Figure 14 A combination of some of the above examples is described to more completely describe the working process of the gate driving circuit according to the embodiment of the present application.

[0184] Fig.12 FIG. 2 shows an exemplary circuit diagram of a gate drive circuit according to an embodiment of the present application. Fig.12 As shown, the gate drive circuit includes a discharge circuit and a charging circuit. The discharge circuit includes a first constant current reference generation circuit, a first current mirror circuit, a first clamp circuit, a first buffer circuit and a first output stage circuit connected in sequence. The first constant current reference generation circuit, the first current mirror circuit, the first clamp circuit, the first buffer circuit and the first output stage circuit are respectively as described above. Figure 6 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 As shown. The discharge circuit includes a second constant current reference generating circuit, a second current mirror circuit, a second clamping circuit, a second buffer circuit and a second output stage circuit connected in sequence, which are similar to the structures of the first constant current reference generating circuit, the first current mirror circuit, the first clamping circuit, the first buffer circuit and the first output stage circuit. In addition, the charging circuit also includes a third current mirror circuit, which is similar to the first and second current mirror circuits.

[0185] like Fig.12As shown, the second constant current reference generating circuit includes an operational amplifier AMP10, a transistor NM9 and an adjustable resistance element. Among them, the adjustable resistance element includes a plurality of resistors connected in series, shown as R1, R2, R3...Rn-1, Rn. Among them, a switch tube is connected in parallel at both ends of each resistor from R2 to Rn-1, and its gate is controlled by respective control signals Z1, Z2...Zx. The positive input terminal of AMP10 is connected to the reference signal VREF (wherein VREF can be provided by a bandgap reference circuit), the negative input terminal is connected to one end of R1 (node ​​F), R1 to Rn are connected in series, one end of Rn is connected to Rn-1, and the other end is grounded. The output end of AMP10 is connected to the gate of NM9, and the drain of NM9 is connected to the second current mirror circuit to provide it with current I4.

[0186] The second current mirror circuit includes an operational amplifier AMP11, transistors PM4, PM5 and PM6. The positive input terminal of the operational amplifier AMP11 is connected to the gate of PM4 and the gate of PM5 (point G), the negative input terminal is connected to the drain of PM5 and the source of PM6 (point H), and the output terminal is connected to the gate of PM6. The source of PM4 is connected to the power signal, and the drain is connected to the second constant current reference generation circuit. The source of PM5 is connected to the power signal. The drain of PM6 serves as the output terminal of the second current mirror circuit and outputs the current I5. Further, optionally, the second current mirror circuit may also include a filtering circuit, such as Fig.12 The two-stage low-pass RC filter circuit composed of RD, RE, CD, and CE is connected between the gate of PM4 and the gate of PM5. The filter circuit can filter out high-frequency noise in the reference voltage and reduce the error of the output circuit.

[0187] The third current mirror circuit includes operational amplifiers AMP6, NM6, NM7 and NM8. Among them, the positive input terminal of AMP6 is connected to the gates of NM6 and NM7 (point J), the negative input terminal is connected to the drain of NM7 and the source of NM8 (point K), and the output terminal is connected to the gate of NM8. The drain of NM6 is connected to the output terminal of the second current mirror circuit, and the source is grounded. The source of NM7 is grounded. The drain of NM8 is connected to the second clamping circuit and the second output stage circuit (point M). The third current mirror circuit outputs current I6 based on current I5.

[0188] The second clamp circuit includes an operational amplifier AMP7 and a transistor PM8. The positive input terminal of AMP7 is connected to the drain of PM8, the negative input terminal is connected to the reference signal VREF2 (wherein VREF2 can be provided by a bandgap reference circuit), and the output terminal is connected to the gate of PM8. The source of PM8 is connected to the power supply signal VCC, and the drain is connected to the output terminal of the third current mirror circuit.

[0189] The second buffer circuit comprises an operational amplifier AMP8, wherein a positive input terminal thereof is connected to the output terminal of the second clamping circuit, and a negative input terminal thereof is connected to the second output stage circuit.

[0190] The second output stage circuit includes an operational amplifier AMP9, transistors PM7, PM8, PM10 and a resistor element Rgon. The positive input terminal of the operational amplifier AMP9 is connected to the output terminal of the third current mirror circuit, the negative input terminal is connected to the source of PM10, the drain of PM9 and the drain of PM7 (point N), and the output terminal is connected to the gate of PM10. The drain of PM10 is connected to the first end of the resistor element Rgon. The source of PM9 is connected to the power signal VCC, and the gate is connected to the output terminal of the second buffer circuit. The source of PM7 is connected to the power signal VCC, and the gate is connected to the pull-up signal PUP. The second end of the resistor element Rgon is connected to the power device.

[0191] like Fig.12 VREF, VREF1, and VREF2 shown are all provided by a bandgap reference circuit, where VREF1 and VREF2 are different voltage dividers of VREF. S1~Sx, Z1~Zx are control signals of the resistance between point A and point F to ground, respectively, and can select the number of resistors connected to the circuit. PDN is the pull-down signal of the circuit, and PUP is the pull-up signal of the circuit. LO is the output terminal of the gate drive circuit, connected to the gate of the power semiconductor device Q1, driving it to turn on and off. Since the circuit structures of the charging circuit and the discharging circuit are very similar, and the two circuits do not interfere with each other, the working principle of the discharge circuit is explained below, and the charging circuit is only briefly described.

[0192] The detailed working principle of the discharge circuit is:

[0193] When the VREF input is valid, the first constant current reference generation circuit uses the negative feedback of the op amp to make the voltage at point A equal to VREF, and the current flowing through NM1 is I1. Then, by selecting S1~Sx, the number of load resistors S connected to the circuit can be determined, thereby adjusting the resistance value Rs from point A to ground. Then, when the S1~Sx signals are all high, the load resistance at point A is Rs=R1+Rn. When the S1~Sx signals are all low, Rs=R1+R2+R3+…+Rn-1+Rn. If the resistance of R1~Rn is the same as R, that is, the RS min value is RS=2R, and RS max=nR. It can be concluded from I1=VREF / Rs that I1 is inversely proportional to Rs. The first constant current reference generation circuit achieves the effect of adjusting the current by adjusting the resistance value of the connected load resistor Rs.

[0194] The high-precision current mirror composed of PM1, PM2 and AMP2 perfectly copies the reference current I1 to I2. Usually, the general current mirror will cause a large error in the mirrored current due to the difference in drain-source voltage between PM1 and PM2. The role of AMP2 is to stabilize the voltage at point C at the voltage at point B through negative feedback, so that the drain, source and gate voltages of PM1 and PM2 are the same, thus solving the problem of the existence of drain-source voltage V SD The problem of difference is solved, thereby ensuring the accuracy of the current mirror when copying the current. In addition, the current mirror also includes a two-stage low-pass RC filter circuit composed of RA, RB, CA, and CB. The filter circuit can filter out the high-frequency noise in the reference voltage and reduce the error of the output circuit.

[0195] If the ratio between the width-to-length ratio of PM2 and the width-to-length ratio of PM1 is b, then:

[0196]

[0197] The clamp circuit composed of AMP3 and NM2 mainly makes the drain-source voltage of NM2 equal to VREF1 through the negative feedback of the operational amplifier. VREF1 is a relatively low voltage. The clamp circuit can make NM2 work stably in the saturation region and the power consumption is relatively low when it is turned on normally. The main function of the first buffer circuit with a gain of 1 is to provide greater driving capability for the output of AMP3, and at the same time make the gate and source voltages of NM2 and NM3 consistent to form a current mirror.

[0198] The output stage circuit and the clamp circuit form a current mirror. Due to the clamp circuit, the voltage of node D remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby increasing the turn-on speed of the current mirror. One of the functions of AMP5 is to make the voltage at point E equal to the voltage at point D through negative feedback, thereby eliminating the problem of the drain-source voltage difference between the current mirror tubes NM2 and NM3 and improving the accuracy of the current mirror; another function is to control the turn-on and turn-off of the NM4 tube of the output stage circuit, that is, to control the operation or shut-off of the discharge loop of the gate circuit.

[0199] In summary, when the VREF input is valid, the PUP signal is low (pull-up works), the PM7 tube is turned on so that the voltage at point N is pulled up to VCC and the output of AMP9 is also pulled up to VCC, then PM10 is turned off, that is, the charging circuit is closed. At this time, the PDN signal is low, the NM5 tube is turned off, the voltage at point E is not pulled down to the ground, and the PDN of AMP5 also does not have a pull-down effect. AMP5 operates normally. At this time, the power semiconductor device is turned off, and the gate drive circuit works in a discharge state.

[0200] like Fig.12 As shown, if the ratio between the width-to-length ratio of NM3 and the width-to-length ratio of NM2 is c, then:

[0201]

[0202] When the discharge current I3 from LO to ground matches the power device and is found to be too small or too large, the appropriate I3 current value can be quickly obtained by adjusting the resistance value of Rs.

[0203] Similarly, when charging, when PUP and PDN are both high, NM5 is turned on, point E is pulled down to the ground, and PDN of AMP5 is high, which causes the output of AMP5 to be pulled down to the ground, that is, the gate voltage of NM4 is 0, then NM4 will be cut off, that is, the discharge circuit is closed. The PUP signal is high, PM7 is cut off, the voltage at point N is not pulled up to the power supply, and the output of AMP9 is not pulled up to the power supply by PUP. AMP9 works normally, PM10 is turned on, and the power semiconductor device is turned on, and the gate drive circuit works in the charging state.

[0204] like Fig.12 As shown, if the ratio between the width-to-length ratio of PM5 and PM4 is d, the ratio between the width-to-length ratio of NM7 and NM6 is e, the ratio between the width-to-length ratio of PM9 and PM8 is f, and Rz is the resistance value from point F to ground, which is adjusted by the Z1~Zx selection signals. Then we can get:

[0205]

[0206] When the charging current I7 from VCC to LO matches the power device and is found to be too small or too large, the appropriate I7 ​​current value can be quickly obtained by adjusting the resistance value of Rz.

[0207] Fig.13 An exemplary circuit diagram of a gate driving circuit according to another embodiment of the present application is shown. Fig.13 The examples shown are similar to Fig.12 The two constant current reference generation circuits are generally similar, so their structure and working principle will not be described in detail. Only the differences between the two are described. The difference is that both constant current reference generation circuits use external resistors to achieve adjustable resistance, thereby achieving electrical adjustment. Fig.12 The example shown, Fig.13 The gate driving circuit of the illustrated example can greatly save circuit area, as described above.

[0208] Fig.14 An exemplary circuit diagram of a gate driving circuit according to yet another embodiment of the present application is shown. Fig.14 The examples shown are similar to Fig.12 Compared with the example shown in the figure, the structure is simplified, the clamping circuit and the buffer circuit in the charging circuit and the discharging circuit are removed, and the structure of the current mirror circuit is also simplified, which can be used to implement Figure 2The working principle of the structural framework shown has been described in the previous text and will not be repeated here.

[0209] Based on the above description, the gate drive circuit according to the embodiment of the present application can match the power device by adjusting the charging current and / or discharging current when the power device and the gate drive circuit do not match, thereby solving the problem of charging and discharging too fast or too slow when the gate drive circuit does not match the power device.

[0210] Fig.15 FIG. 4 shows an exemplary structural block diagram of a gate drive circuit 5 according to another embodiment of the present application. Fig.15 As shown, the gate drive circuit 5 may include a first constant current reference generating circuit 111, a first current mirror circuit 112, a first output stage circuit 113, and a second output stage circuit 123. The output end of the first output stage circuit 113 and the output end of the second output stage circuit 123 are connected to a power device (not shown). The first constant current reference generating circuit 111 is used to output an adjustable first current. The first current mirror circuit 112 is used to output a second current based on the first current. The first output stage circuit 113 is used to operate based on the second current, so that the third current (i.e., the discharge current) output by the power device to the first output stage circuit 113 is adjustable. The second output stage circuit 123 is used to operate based on the second current, so that the fourth current (i.e., the charging current) output by the second output stage circuit 123 to the power device is adjustable.

[0211] The gate drive circuit 5 according to the embodiment of the present application is similar to the gate drive circuit 1 described above, except that the gate drive circuit 5 only includes one constant current reference generating circuit and one current mirror circuit, instead of two constant current reference generating circuits and two current mirror circuits as in the gate drive circuit 1, because the discharge circuit and the charging circuit of the gate drive circuit 5 share the constant current reference generating circuit and the current mirror circuit. Specifically, the discharge circuit includes a first constant current reference generating circuit 111, a first current mirror circuit 112, and a first output stage circuit 113. The charging circuit includes a first constant current reference generating circuit 111, a first current mirror circuit 112, and a second output stage circuit 123. In this way, since the constant current reference generating circuit can output an adjustable current, the current is still an adjustable current after being copied by the current mirror circuit, and the adjustable current is used in the output stage circuit, so that the current of the output stage circuit is adjustable, that is, the charging current and the discharging current are adjustable. Here, unlike gate drive circuits 1 to 4, since the discharge circuit and charging circuit of gate drive circuit 5 share the constant current reference generation circuit and the current mirror circuit, its charging current and discharge current need to be adjusted synchronously and cannot be adjusted independently. However, despite this, in some cases, the problem of too fast or too slow charging and discharging when the gate drive circuit does not match the power device can be solved. The other contents of gate drive circuit 5 are generally similar to the gate drive circuits 1 to 4 described above. For the sake of brevity, the details will not be repeated here, and only some main contents will be described.

[0212] In one embodiment of the present application, the gate drive circuit 5 further includes: a first clamping circuit (not shown in Fig.15 It is shown in Fig.16 ), connected between the first current mirror circuit 112 and the first output stage circuit 113, for operating based on the second current, and its output acts on the first output stage circuit 113; and / or, a second clamping circuit (not shown in Fig.15 It is shown in Fig.16 ), connected between the first current mirror circuit 112 and the second output stage circuit 123, for operating based on the second current, and its output acts on the second output stage circuit 123.

[0213] In this embodiment, by adding a first clamping circuit between the first current mirror circuit 112 and the first output stage circuit 113, it is possible to ensure that the voltage of the node between the first current mirror circuit 112 and the first output stage circuit 113 remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the first current mirror. Similarly, by adding a second clamping circuit between the first current mirror circuit 112 and the second output stage circuit 123, it is possible to ensure that the voltage of the node between the first current mirror circuit 112 and the second output stage circuit 123 remains unchanged, and the equivalent capacitance to the ground does not need to be charged or discharged, thereby improving the turn-on speed of the first current mirror.

[0214] In one embodiment of the present application, the gate drive circuit 5 further includes: a first buffer circuit (not shown in Fig.15 It is shown in Fig.16 ), connected between the first clamping circuit and the first output stage circuit 113, for operating based on the output of the first clamping circuit, whose output acts on the first output stage circuit 113; and / or, a second buffer circuit (not shown in Fig.15 It is shown in Fig.16 ), connected between the second clamping circuit and the second output stage circuit 123, and configured to operate based on the output of the second clamping circuit, and its output acts on the second output stage circuit 123.

[0215] In this embodiment, by adding a first buffer circuit between the first clamp circuit and the first output stage circuit 113, a greater driving capability can be provided for the output of the first clamp circuit, and at the same time, the gate and source voltages of the transistors of the first clamp circuit and the first buffer circuit are made consistent, thereby forming a current source. Similarly, by adding a second buffer circuit between the second clamp circuit and the second output stage circuit 123, a greater driving capability can be provided for the output of the second clamp circuit, and at the same time, the gate and source voltages of the transistors of the second clamp circuit and the transistors of the second buffer circuit are made consistent, thereby forming a current source.

[0216] In one embodiment of the present application, the gate drive circuit 5 further includes: a second current mirror circuit (not shown in Fig.15 It is shown in Fig.16 ), connected between the first current mirror circuit 112 and the second clamping circuit, for operating based on the second current, with its output serving as an input of the second clamping circuit.

[0217] In this embodiment, by adding a second current mirror circuit between the first current mirror circuit 112 and the second clamp circuit, the current can be amplified, so that the output stage circuit can provide a larger charging current to the power device.

[0218] In one embodiment of the present application, the first constant current reference generating circuit 111 includes: an operational amplifier, whose positive input terminal is connected to a reference signal, whose negative input terminal is connected to a first end of an adjustable resistance element, and whose output terminal is connected to a gate of a transistor; a transistor, whose drain is connected to a corresponding current mirror circuit, and whose source is connected to the first end of an adjustable resistance element; and an adjustable resistance element, whose second end is grounded.

[0219] In this embodiment, the voltage at the source of the transistor is equal to the reference voltage through the negative feedback of the operational amplifier, so that the voltage across the adjustable resistance element is determined, and then the adjustable current value can be obtained by adjusting the resistance value of the adjustable resistance element. This technical solution realizes current regulation through internal components and is simple to operate.

[0220] In one embodiment of the present application, the adjustable resistance element includes: a plurality of resistors connected in series, wherein two ends of each resistor in at least some of the resistors are connected in parallel with a switch element, and each switch element is controlled by a respective control signal.

[0221] In this embodiment, a switch element is connected in parallel to both ends of each of the partial resistors in the plurality of series resistors. When the switch element is turned on, the resistor is equivalent to being short-circuited, that is, the resistance value of the adjustable resistor element is reduced; when the switch element is turned off, the resistor is not short-circuited, that is, the resistance value of the adjustable resistor element is increased. This technical solution can control the resistors separately by connecting the switch element in parallel to at least part of the resistors, thereby conveniently achieving the effect of adjusting the current by the number of connected resistors.

[0222] In one embodiment of the present application, the first constant current reference generating circuit 111 includes: an operational amplifier, whose positive input terminal is connected to a reference signal, whose negative input terminal is connected to the first end of the resistor element, and whose output terminal is connected to the gate of the transistor; a transistor, whose drain is connected to the corresponding current mirror circuit and whose source is connected to the first end of the resistor element; a resistor element, whose second end is connected to an interface; and an interface for connecting an external resistor.

[0223] In this embodiment, the voltage at the source of the transistor is equal to the reference voltage through the negative feedback of the operational amplifier, so that the voltage across the resistor element is determined, and then the external resistor is connected through the adjustment interface. By adjusting the external resistor, the change of the access resistance value is achieved, so that the adjustable current value can be obtained. This technical solution realizes current regulation by connecting the external resistor through the interface, which can reduce the internal components of the circuit, save costs, and improve the flexibility of current regulation.

[0224] In one embodiment of the present application, the first current mirror circuit 112 includes: an operational amplifier, whose positive input terminal is connected to the gate of the first transistor and the gate of the second transistor, whose negative input terminal is connected to the drain of the second transistor and the source of the third transistor, and whose output terminal is connected to the gate of the third transistor; a first transistor, whose source is connected to a power supply signal and whose drain is connected to a corresponding constant current reference generating circuit; a second transistor, whose source is connected to the power supply signal; and a third transistor, whose drain serves as the output terminal of the current mirror circuit.

[0225] In this embodiment, by adding an operational amplifier to the current mirror circuit, the problem of drain-source voltage difference can be solved, thereby ensuring the accuracy of the current mirror when copying the current. Alternatively, the first current mirror circuit 112 may not include an operational amplifier and can also achieve the function of copying the current ( Fig.16 The current mirror shown in FIG. 1 is a more simplified structure).

[0226] In one embodiment of the present application, the first current mirror circuit 112 further includes: a filter circuit connected between the gate of the first transistor and the gate of the second transistor.

[0227] In this embodiment, by adding a filter circuit in the current mirror circuit, the problem of drain-source voltage difference can be solved, thereby ensuring the accuracy of the current mirror when copying the current.

[0228] In one embodiment of the present application, the first output stage circuit 113 includes: a first operational amplifier, whose positive input terminal is connected to the output terminal of the first current mirror circuit, whose negative input terminal is connected to the source of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor, and whose output terminal is connected to the gate of the fourth transistor; the fourth transistor, whose drain is connected to the first end of the first resistor element; the fifth transistor, whose source is grounded, and whose gate is connected to the output terminal of the first buffer circuit; the sixth transistor, whose source is grounded, and whose gate is connected to the first control signal; the first resistor element, whose second end is connected to the power device. The second output stage circuit 123 includes: a second operational amplifier, whose positive input terminal is connected to the output terminal of the second current mirror circuit, whose negative input terminal is connected to the source of the seventh transistor, the drain of the eighth transistor and the drain of the ninth transistor, and whose output terminal is connected to the gate of the seventh transistor; the seventh transistor, whose drain is connected to the first end of the second resistor element; the eighth transistor, whose source is connected to the power supply, and whose gate is connected to the output terminal of the second buffer circuit; the ninth transistor, whose source is connected to the power supply, and whose gate is connected to the second control signal; the second resistor element, whose second end is connected to the power device.

[0229] In this embodiment, by adding an operational amplifier to the output stage circuit, the problem of the source-drain voltage difference between the transistors of the clamp circuit and the transistors of the buffer circuit can be eliminated, thereby improving the accuracy of the current mirror. In addition, the on and off of the transistors in the output stage circuit can be controlled, that is, the operation or shutdown of the discharge circuit and the charging circuit can be controlled, thereby eliminating the need to provide additional control signals.

[0230] Fig.16 Shows Fig.15 The specific example of the structure shown is similar to the above Fig.12 The examples shown are similar to the original ones, so we will not repeat them here, but only describe the differences. The differences are Fig.16 The discharge circuit and charging circuit of the gate drive circuit shown in the figure share the constant current reference generation circuit and the current mirror circuit, so that the charging current of the power device and the discharge current of the power device can be adjusted synchronously (that is, both are adjusted up or down together) instead of being adjusted independently. However, it can also solve the problem of too fast or too slow charging and discharging when the gate drive circuit and the power device do not match to a certain extent. In the figure, EN and ENB are mutually inverse enable control signals. When the enable is valid, the circuit works normally (EN=0, ENB=1), and when it is invalid, the circuit cannot work.

[0231] According to another aspect of the present application, a gate driving chip is further provided, and the gate driving chip includes the above-mentioned gate driving circuit according to the embodiment of the present application.

[0232] According to another aspect of the present application, an electronic device is provided, which includes the above-mentioned gate driving chip.

[0233] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0234] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0235] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0236] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0237] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0238] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0239] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0240] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some modules in the article analysis device according to the embodiment of the present application. The present application can also be implemented as a device program (e.g., computer program and computer program product) for executing part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0241] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0242] The above is only a specific implementation method or description of a specific implementation method of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit comprises: A discharge circuit, the discharge circuit comprising: A first constant current reference generating circuit, used for outputting an adjustable first current; A first current mirror circuit, configured to output a second current based on the first current; a first output stage circuit, configured to operate based on the second current so that a third current outputted by the power device to the first output stage circuit is adjustable; A charging circuit, the charging circuit comprising: A second constant current reference generating circuit, used for outputting an adjustable fourth current; a second current mirror circuit, configured to output a fifth current based on the fourth current; The second output stage circuit is configured to operate based on the fifth current so that a sixth current output by the second output stage circuit to the power device is adjustable, wherein the power device is connected to the output end of the first output stage circuit and the output end of the second output stage circuit.

2. The gate driving circuit according to claim 1, characterized in that: The discharge circuit further comprises: a first clamping circuit, connected between the first current mirror circuit and the first output stage circuit, configured to operate based on the second current, and whose output acts on the first output stage circuit; and / or The charging circuit further comprises: The second clamping circuit is connected between the second current mirror circuit and the second output stage circuit, and is used for operating based on the fifth current, and the output of the second clamping circuit acts on the second output stage circuit.

3. The gate driving circuit according to claim 2, characterized in that: The discharge circuit further comprises: a first buffer circuit, connected between the first clamp circuit and the first output stage circuit, and configured to operate based on an output of the first clamp circuit, wherein the output of the first buffer circuit acts on the first output stage circuit; and / or The charging circuit further comprises: The second buffer circuit is connected between the second clamp circuit and the second output stage circuit and is used for operating based on the output of the second clamp circuit, and the output of the second buffer circuit acts on the second output stage circuit.

4. The gate driving circuit according to claim 3, characterized in that: The charging circuit further comprises: The third current mirror circuit is connected between the second current mirror circuit and the second clamp circuit, and is used to operate based on the fifth current, and the output of the third current mirror circuit serves as the input of the second clamp circuit.

5. The gate drive circuit according to any one of claims 1 to 4, characterized in that: The first constant current reference generating circuit and the second constant current reference generating circuit both include: an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of an adjustable resistance element, and an output terminal thereof is connected to a gate of a transistor; The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the adjustable resistance element; The second end of the adjustable resistance element is grounded.

6. The gate driving circuit according to claim 5, characterized in that: The adjustable resistance element comprises: A plurality of resistors are connected in series, wherein two ends of each resistor in at least some of the resistors are connected in parallel with a switch element, and each of the switch elements is controlled by a respective control signal.

7. The gate drive circuit according to any one of claims 1 to 4, characterized in that: The first constant current reference generating circuit and the second constant current reference generating circuit both include: an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of a resistor element, and an output terminal thereof is connected to a gate of a transistor; The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the resistor element; The resistance element has a second end connected to the interface; The interface is used to connect an external resistor.

8. The gate drive circuit according to any one of claims 1 to 4, characterized in that: The first current mirror circuit and the second current mirror circuit both include: an operational amplifier, wherein a positive input terminal is connected to the gate of the first transistor and the gate of the second transistor, a negative input terminal is connected to the drain of the second transistor and the source of the third transistor, and an output terminal is connected to the gate of the third transistor; The first transistor has a source connected to a power supply signal and a drain connected to the corresponding constant current reference generating circuit; The second transistor has a source connected to a power signal; The drain of the third transistor serves as the output end of the current mirror circuit.

9. The gate driving circuit according to claim 8, characterized in that: The first current mirror circuit and the second current mirror circuit both include: The filter circuit is connected between the gate of the first transistor and the gate of the second transistor.

10. The gate driving circuit according to any one of claims 3 or 4, characterized in that: The first output stage circuit comprises: a first operational amplifier, wherein a positive input terminal of the first operational amplifier is connected to the output terminal of the first current mirror circuit, a negative input terminal of the first operational amplifier is connected to the source of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor, and an output terminal of the first operational amplifier is connected to the gate of the fourth transistor; The fourth transistor has a drain connected to the first end of the first resistor element; The fifth transistor has a source connected to the ground and a gate connected to the output end of the first buffer circuit; The sixth transistor has a source connected to the ground and a gate connected to the first control signal; The first resistance element, a second end of the first resistance element is connected to the power device; The second output stage circuit comprises: a second operational amplifier, wherein a positive input terminal of the second operational amplifier is connected to the output terminal of the second current mirror circuit, a negative input terminal of the second operational amplifier is connected to the source of the seventh transistor, the drain of the eighth transistor and the drain of the ninth transistor, and an output terminal of the second operational amplifier is connected to the gate of the seventh transistor; The seventh transistor has a drain connected to the first end of the second resistor element; The eighth transistor has a source connected to a power supply and a gate connected to an output end of the second buffer circuit; The ninth transistor has a source connected to the power supply and a gate connected to the second control signal; The second resistance element, a second end of the second resistance element is connected to the power device.

11. A gate drive circuit, characterized in that: The gate drive circuit comprises: A first constant current reference generating circuit, used for outputting an adjustable first current; A first current mirror circuit, configured to output a second current based on the first current; a first output stage circuit, configured to operate based on the second current so that a third current outputted by the power device to the first output stage circuit is adjustable; The second output stage circuit is used to operate based on the second current so that a fourth current output by the second output stage circuit to the power device is adjustable, wherein the power device is connected to the output end of the first output stage circuit and the output end of the second output stage circuit.

12. The gate driving circuit according to claim 11, characterized in that: The gate drive circuit further includes: a first clamping circuit, connected between the first current mirror circuit and the first output stage circuit, configured to operate based on the second current, and whose output acts on the first output stage circuit; and / or The second clamping circuit is connected between the first current mirror circuit and the second output stage circuit, and is used for operating based on the second current, and the output of the second clamping circuit acts on the second output stage circuit.

13. The gate driving circuit according to claim 12, characterized in that: The gate drive circuit further includes: a first buffer circuit, connected between the first clamp circuit and the first output stage circuit, and configured to operate based on an output of the first clamp circuit, wherein the output of the first buffer circuit acts on the first output stage circuit; and / or The second buffer circuit is connected between the second clamp circuit and the second output stage circuit and is used for operating based on the output of the second clamp circuit, and the output of the second buffer circuit acts on the second output stage circuit.

14. The gate driving circuit according to claim 13, characterized in that: The gate drive circuit further includes: The second current mirror circuit is connected between the first current mirror circuit and the second clamp circuit and is used to operate based on the second current, and the output of the second current mirror circuit serves as the input of the second clamp circuit.

15. The gate driving circuit according to any one of claims 11 to 14, characterized in that: The first constant current reference generating circuit comprises: an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of an adjustable resistance element, and an output terminal thereof is connected to a gate of a transistor; The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the adjustable resistance element; The second end of the adjustable resistance element is grounded.

16. The gate driving circuit according to claim 15, characterized in that: The adjustable resistance element comprises: A plurality of resistors are connected in series, wherein two ends of each resistor in at least some of the resistors are connected in parallel with a switch element, and each of the switch elements is controlled by a respective control signal.

17. The gate driving circuit according to any one of claims 11 to 14, characterized in that: The first constant current reference generating circuit comprises: an operational amplifier, wherein a positive input terminal thereof is connected to a reference signal, a negative input terminal thereof is connected to a first end of a resistor element, and an output terminal thereof is connected to a gate of a transistor; The transistor, a drain of which is connected to the corresponding current mirror circuit, and a source of which is connected to the first end of the resistor element; The resistance element has a second end connected to the interface; The interface is used to connect an external resistor.

18. The gate driving circuit according to any one of claims 11 to 14, characterized in that: The first current mirror circuit comprises: an operational amplifier, wherein a positive input terminal is connected to the gate of the first transistor and the gate of the second transistor, a negative input terminal is connected to the drain of the second transistor and the source of the third transistor, and an output terminal is connected to the gate of the third transistor; The first transistor has a source connected to a power supply signal and a drain connected to the corresponding constant current reference generating circuit; The second transistor has a source connected to a power signal; The drain of the third transistor serves as the output end of the current mirror circuit.

19. The gate driving circuit according to claim 18, characterized in that: The first current mirror circuit further includes: The filter circuit is connected between the gate of the first transistor and the gate of the second transistor.

20. The gate driving circuit according to claim 14, characterized in that: The first output stage circuit comprises: a first operational amplifier, wherein a positive input terminal of the first operational amplifier is connected to the output terminal of the first current mirror circuit, a negative input terminal of the first operational amplifier is connected to the source of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor, and an output terminal of the first operational amplifier is connected to the gate of the fourth transistor; The fourth transistor has a drain connected to the first end of the first resistor element; The fifth transistor has a source connected to the ground and a gate connected to the output end of the first buffer circuit; The sixth transistor has a source connected to the ground and a gate connected to the first control signal; The first resistance element, a second end of the first resistance element is connected to the power device; The second output stage circuit comprises: a second operational amplifier, wherein a positive input terminal of the second operational amplifier is connected to the output terminal of the second current mirror circuit, a negative input terminal of the second operational amplifier is connected to the source of the seventh transistor, the drain of the eighth transistor and the drain of the ninth transistor, and an output terminal of the second operational amplifier is connected to the gate of the seventh transistor; The seventh transistor has a drain connected to the first end of the second resistor element; The eighth transistor has a source connected to a power supply and a gate connected to an output end of the second buffer circuit; The ninth transistor has a source connected to the power supply and a gate connected to the second control signal; The second resistance element, a second end of the second resistance element is connected to the power device.

21. A gate driver chip, characterized in that: The gate driving chip comprises the gate driving circuit according to any one of claims 1-20.

22. An electronic device, characterized in that: The electronic device comprises the gate driving chip according to claim 21.

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