Display driving architecture based on multi-level chip and construction method and maintenance method thereof

Abstract

The invention discloses a display driving architecture based on a multi-level chip and a construction method and a maintenance method thereof, and belongs to the field of display driving architectures.The method comprises the steps that a plurality of peripheral chips are called according to the processing flow of a video stream; the initial priority of each peripheral chip is configured according to the sequence of the processing steps; performing initialization operation on each peripheral chip in sequence from low to high according to the priorities; and the related chips are initialized again according to the priority from the fault chip. According to the method and the device, the peripheral chips required by the display driving architecture are called according to the processing flows of different video streams, the peripheral chips corresponding to the priorities are preliminarily configured according to the sequence of the processing steps, and the peripheral chips are sequentially initialized according to the priorities from low to high, so that the display driving architecture based on the multi-level chips is constructed; the construction efficiency of the display driving architecture is improved, when it is judged that the chips are abnormal, all the chips with the priorities larger than those of the abnormal chips are initialized again from the abnormal chips, and the fault repairing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of display driver architecture, and in particular to a display driver architecture based on a multi-level chip and a construction method and a maintenance method thereof. Background Art

[0002] There are many types of LCD instruments in cars, and the peripheral chips that realize screen display are also diverse. There are direct drives, such as SoC chips directly connected to the display screen, first-level chip drives, and second-level, third-level or even more-level chip drives. How to quickly configure the display driver architecture required for different display screens is a problem that needs to be solved at present.

[0003] In addition, the existing fault diagnosis methods for display driver architectures change with the architecture. After different architectures are built, corresponding fault diagnosis methods need to be specified for the architecture. There is a lack of unified planning, and it is impossible to quickly restore the screen when the display is abnormal. Summary of the invention

[0004] The present application provides a display driver architecture based on a multi-level chip and a construction method and a maintenance method thereof, which can solve the technical problems existing in the prior art that a display driver architecture that can adapt to different video stream processing requirements cannot be quickly constructed and fault handling cannot be quickly performed during the operation of the display driver architecture.

[0005] In a first aspect, an embodiment of the present application provides a method for constructing a display driver architecture based on a multi-level chip, the method comprising:

[0006] According to the processing flow of the video stream, multiple peripheral chips are retrieved, each of which is used to complete a processing step in the processing flow; according to the order of the processing steps, chip-related attributes and initial priorities of each peripheral chip are configured, the chip-related attributes are used for the operation and maintenance of the chip, and the initial priority gradually increases according to the order of the processing flow; the peripheral chips include SoC chips and multiple video processing chips, and the SoC chip has the lowest initial priority;

[0007] Initialize each peripheral chip in order from low to high priority to build a display driver architecture based on multi-level chips.

[0008] In combination with the first aspect, in one implementation, the chip-related attributes include power operation attributes, initialization and deinitialization attributes, input and output interface attributes, operation interface attributes, and fault diagnosis interface attributes;

[0009] The power operation attribute is used to obtain and control the power state of the peripheral chip;

[0010] Initialization and deinitialization attributes are used to initialize and deinitialize peripheral chips;

[0011] The input and output interface properties are used to obtain and control the input video stream format and output video stream format of the peripheral chip;

[0012] The operation interface attribute is used to obtain and control the internal operation of the peripheral chip, wherein the internal operation includes processing operations in the video and control operations for controlling the working state of the peripheral chip, wherein the working state of the peripheral chip includes a normal working state, an abnormal working state, and a dormant state;

[0013] The fault diagnosis interface attributes are used to obtain the fault cause of the peripheral chip and to control the fault repair operation on the peripheral chip.

[0014] In combination with the first aspect, in one implementation, the method further includes:

[0015] A peripheral chip whose initialization operation does not depend on the operation result of the initialization operation of other peripheral chips is defined as a single-rank chip, and the priority of the single-rank chip is adjusted according to the custom information to obtain the final priority of all peripheral chips.

[0016] In a second aspect, an embodiment of the present application provides a display driver architecture based on a multi-level chip, which is constructed using the construction method of the display driver architecture based on a multi-level chip.

[0017] In a third aspect, an embodiment of the present application provides a maintenance method for a display driver architecture based on a multi-level chip, based on the display driver architecture based on the multi-level chip; the maintenance method comprises:

[0018] A variable cycle detection method is used to detect whether each video processing chip is operating normally, and a detection result is obtained; the variable cycle detection method is to divide the detection cycle into a fast cycle and a slow cycle, the fast cycle detects the video processing chip according to a first frequency, and the slow cycle detects the video processing chip according to a second frequency, the first frequency is greater than the second frequency, and within a first specified time after the video processing chip is powered on or awakened, the video processing chip is detected according to the fast cycle, and when the detection results are abnormal for multiple consecutive times, it is determined that the video processing chip is operating abnormally, and when the fast cycle lasts for more than the second specified time and the detection results are normal, switch to the slow cycle, and when the detection result is abnormal, switch back to the fast cycle, and the first specified time is less than the second specified time;

[0019] When the detection result is that the video processing chip operates abnormally, initialization operations are performed on each peripheral chip in order of priority, starting with the video processing chip that operates abnormally.

[0020] In conjunction with the third aspect, in one implementation, determining whether the detection result is abnormal specifically includes the following steps:

[0021] The actual register value of the video processing chip is obtained, and it is determined whether the actual register value is consistent with the theoretical register value of the video processing chip. If so, the detection result of the video processing chip is determined to be normal; if not, the detection result of the video processing chip is determined to be abnormal.

[0022] In conjunction with the third aspect, in one implementation, determining whether the detection result is abnormal specifically includes the following steps:

[0023] Obtain whether the video input parameter of the video processing chip of the next priority is normal. If so, determine that the detection result of the video processing chip of the previous priority is normal; if not, determine that the detection result of the video processing chip of the previous priority is abnormal.

[0024] In conjunction with the third aspect, in one implementation, the method further includes:

[0025] After receiving the system sleep command, the peripheral chips at each level are deinitialized in sequence from high to low priority.

[0026] In conjunction with the third aspect, in one implementation, the maintenance method further includes:

[0027] Check whether the video stream received by the SoC chip is normal. If so, use a variable period detection method to check whether each video processing chip is operating normally; if not, control the SoC chip to perform fault handling according to the built-in fault handling process.

[0028] In conjunction with the third aspect, in one implementation, the maintenance method further includes:

[0029] Check whether the picture output by the connected display screen is normal. If so, use a variable period detection method to check whether each video processing chip is operating normally. If not, while using a variable period detection method to check whether each video processing chip is operating normally, control the display screen to perform fault handling according to the built-in fault handling process.

[0030] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:

[0031] According to the processing flow of different video streams, the peripheral chips required by the display driver architecture are called, and the peripheral chips corresponding to each priority are preliminarily configured in the order of the processing steps. Each peripheral chip is initialized in order from low to high priority, so as to build a display driver architecture based on multi-level chips and improve the construction efficiency of the display driver architecture. During the operation of the display driver architecture, a variable period detection method is used to detect whether each video processing chip is operating normally, thereby improving the detection accuracy and reducing the calculation load. When it is determined that the chip is abnormal, starting from the abnormal chip, all chips with a priority greater than the abnormal chip are reinitialized to improve the fault repair efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a flow chart of an embodiment of a method for constructing a display driver architecture based on a multi-level chip of the present application;

[0033] Figure 2 This is a flow chart of an embodiment of a maintenance method of a display driver architecture based on a multi-level chip of the present application. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0036] In a first aspect, an embodiment of the present application provides a method for constructing a display driver architecture based on a multi-level chip.

[0037] In one embodiment, referring to Figure 1 , Figure 1 FIG. 1 is a flow chart of an embodiment of a method for constructing a display driver architecture based on a multi-level chip of the present application. Figure 1 As shown, the construction method of the display driver architecture based on the multi-level chip includes:

[0038] Step S1, calling multiple peripheral chips according to the processing flow of the video stream, each peripheral chip is used to complete a processing step in the processing flow.

[0039] Step S2: configure the chip-related attributes and initial priority of each peripheral chip according to the order of the processing steps. The chip-related attributes are used for the operation and maintenance of the chip, and the initial priority gradually increases according to the order of the processing flow. The above peripheral chips include SoC chips and various video processing chips, and the SoC chip has the lowest initial priority.

[0040] Step S3: Initialize each peripheral chip in order from low to high priority to build a display driver architecture based on multi-level chips.

[0041] In this embodiment, the peripheral chips required by the display driver architecture are called according to the processing flow of different video streams, and the peripheral chips corresponding to each priority are preliminarily configured in the order of processing steps, and each peripheral chip is initialized in sequence from low to high priority, thereby constructing a display driver architecture based on multi-level chips and improving the construction efficiency of the display driver architecture.

[0042] Furthermore, in one embodiment, the above chip-related attributes include power operation attributes, initialization and deinitialization attributes, input and output interface attributes, operation interface attributes, and fault diagnosis interface attributes.

[0043] The power operation properties are used to obtain and control the power state of the peripheral chip.

[0044] The initialization and deinitialization properties are used to initialize and deinitialize the peripheral chip.

[0045] The input and output interface properties are used to obtain and control the input video stream format and output video stream format of the peripheral chip.

[0046] The operation interface attributes are used to obtain and control the internal operations of the peripheral chip. The above internal operations include processing operations in the video and control operations on the working state of the peripheral chip. The working state of the peripheral chip includes normal working state, abnormal working state, and sleep state.

[0047] The fault diagnosis interface attributes are used to obtain the fault cause of the peripheral chip and to control the fault repair operation on the peripheral chip.

[0048] In this embodiment, while configuring the priority of the peripheral chip, the chip-related attributes of the peripheral chip are configured, so as to quickly build a display driver architecture that adapts to different video stream processing flows.

[0049] In a specific embodiment, after configuring the power operation attribute, the power state of the peripheral chip can be grasped and controlled in real time. For example, the external terminal obtains and controls the power state of the SoC chip, and after the SoC chip is started, the control software inside the SoC chip can obtain and control the power state of the remaining video processing chips.

[0050] After configuring the initialization and deinitialization properties, you can set the initialization method and deinitialization method of the register.

[0051] After configuring the input and output interface properties, you can set the video input interface properties and video output interface properties of the peripheral chip. For example, the video format that the peripheral chip can receive or output through the video input interface is RGB, LVDS, MIPI-DSI, etc. Among them, the video format that the video input interface can receive is determined by the video format output by the previous level chip, and the video format that the video output interface can output is determined by the video processing operation to be performed by the current level chip.

[0052] After configuring the operation interface properties, you can obtain, modify and control the working status of the current chip. The working status is divided into normal working status (also called running status), abnormal working status (also called fault status or abnormal status), and sleep status.

[0053] After configuring the fault diagnosis interface properties, you can set and obtain the diagnosis method of the peripheral chip.

[0054] Furthermore, in one embodiment, the above method further includes:

[0055] Before initializing the first peripheral chip, check whether the video stream is normal and output the video stream detection result.

[0056] After initialization operation is performed on each peripheral chip, the operation result of the initialization operation is output.

[0057] Furthermore, in one embodiment, the above method further includes:

[0058] A peripheral chip whose initialization operation does not depend on the operation result of the initialization operation of other peripheral chips is defined as a single-rank chip, and the priority of the single-rank chip is adjusted according to the custom information to obtain the final priority of all peripheral chips.

[0059] In this embodiment, the peripheral chips required for the display driver architecture are called according to the processing flow of different video streams, and the peripheral chips corresponding to each priority are preliminarily configured in the order of the processing steps. Then, according to whether different chip components have dependencies when performing initialization operations, the priorities of the peripheral chips that do not depend on the initialization operation results of other peripheral chips are set separately, thereby quickly completing the initialization and forming the display driver architecture.

[0060] In a specific embodiment, the processing flow of the video stream includes step one, step two, step three, and step four. Assuming that step one is video stream transparent transmission, step two is video format conversion (for example, RGB to LVDS or MIPI-DSI), step three is image synthesis and segmentation, and step four is image color adjustment, then, according to the above processing flow, the SoC chip, video processing chip a1, video processing chip a2, and video processing chip a3 are called up. The SoC chip is used to complete step one, the video processing chip a1 is used to complete step two, the video processing chip a2 is used to complete step three, and the video processing chip a3 is used to complete step four.

[0061] The initial priority of the SoC chip is 1, the initial priority of the video processing chip a1 is 2, the initial priority of the video processing chip a2 is 3, and the initial priority of the video processing chip a3 is 4, wherein the video processing chip a1 depends on the initialization operation result of the SoC chip, regardless of whether the SoC chip is initialized successfully, and the video processing chip a1 can be initialized only after the SoC chip is initialized, the video processing chip a2 depends on the initialization operation result of the video processing chip a1, and the video processing chip a3 does not depend on the initialization operation results of other chips, at this time, the final priorities of the SoC chip, the video processing chip a1, and the video processing chip a2 are 1, 2, and 3, and the final priority of the video processing chip a3 can be set according to the user's customization. Chips with the same priority can be initialized at the same time, thereby improving the efficiency of architecture construction.

[0062] In a second aspect, an embodiment of the present application further provides a display driver architecture based on a multi-level chip, which is constructed using a construction method of a display driver architecture based on a multi-level chip.

[0063] In a third aspect, an embodiment of the present application provides a maintenance method for a display driver architecture based on a multi-level chip.

[0064] In one embodiment, referring to Figure 2 , Figure 2 FIG. 1 is a flow chart of an embodiment of a maintenance method for a display driver architecture based on a multi-level chip of the present application. Figure 2 As shown, the maintenance method of the display driver architecture based on the multi-level chip includes:

[0065] Step A1, using a variable cycle detection method to detect whether each video processing chip is operating normally, and obtain a detection result. The variable cycle detection method is to divide the detection cycle into a fast cycle and a slow cycle, the fast cycle detects the video processing chip according to a first frequency, and the slow cycle detects the video processing chip according to a second frequency, the first frequency is greater than the second frequency, and within a first specified time after the video processing chip is powered on or awakened, the video processing chip is detected according to the fast cycle. When the detection results are abnormal for multiple consecutive times, it is determined that the video processing chip is operating abnormally. When the fast cycle lasts for more than the second specified time and the detection results are normal, switch to the slow cycle, and when the detection result is abnormal, switch back to the fast cycle, and the first specified time is less than the second specified time.

[0066] Step A2: When the detection result shows that the video processing chip is operating abnormally, starting from the video processing chip operating abnormally, initialization operations are performed on each peripheral chip in order of priority.

[0067] In this embodiment, a variable period detection method is used to detect whether each video processing chip is operating normally, thereby improving the detection accuracy and reducing the computing load. When a chip is determined to be abnormal, all chips with a priority greater than the abnormal chip are reinitialized starting from the abnormal chip, thereby improving fault repair efficiency.

[0068] In a specific embodiment, the detection cycle of the video processing chip is divided into two cycles, fast and slow. The fast cycle is executed within 1 minute after power-on or wake-up, and is detected every 1S. If the video processing chip is detected abnormally for 2 consecutive times, the video processing chip is judged to be faulty. The slow cycle is entered after no fault is detected within 1 minute of the fast cycle detection. The slow cycle is detected once every 5S. After the video processing chip fault is detected, it is immediately switched to the fast cycle detection. The video processing chip fault is judged by the fast cycle. This method can reduce the CPU usage while ensuring that it can be recovered.

[0069] Furthermore, in one embodiment, the above-mentioned determination of whether the detection result is abnormal specifically includes the following steps:

[0070] The actual register value of the video processing chip is obtained, and it is determined whether the actual register value is consistent with the theoretical register value of the video processing chip. If so, the detection result of the video processing chip is determined to be normal. If not, the detection result of the video processing chip is determined to be abnormal.

[0071] Furthermore, in one embodiment, the above-mentioned determination of whether the detection result is abnormal specifically includes the following steps:

[0072] Obtain whether the video input parameter of the video processing chip of the next priority is normal, if so, determine that the detection result of the video processing chip of the previous priority is normal. If not, determine that the detection result of the video processing chip of the previous priority is abnormal.

[0073] In this embodiment, by judging whether the video input parameters of the next-level chip are normal, and then judging whether the video output parameters of the previous level are normal, this method can perform detection through chips at different levels to ensure the integrity of input and output.

[0074] Furthermore, in one embodiment, the above method further includes:

[0075] After receiving the system sleep command, the peripheral chips at each level are deinitialized in sequence from high to low priority.

[0076] Furthermore, in one embodiment, the maintenance method further includes:

[0077] Check whether the video stream received by the SoC chip is normal. If so, use a variable period detection method to check whether each video processing chip is running normally. If not, control the SoC chip to handle the fault according to the built-in fault handling process.

[0078] Furthermore, in one embodiment, the maintenance method further includes:

[0079] Check whether the image output by the connected display screen is normal. If so, use a variable period detection method to check whether each video processing chip is operating normally. If not, while using a variable period detection method to check whether each video processing chip is operating normally, control the display screen to perform fault handling according to the built-in fault handling process.

[0080] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0081] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0082] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0083] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B. "And / or" in the text is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0084] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0085] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as mentioned above, including a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0086] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for constructing a display driver architecture based on a multi-level chip, characterized in that: The construction method comprises: According to the processing flow of the video stream, multiple peripheral chips are retrieved, each of which is used to complete a processing step in the processing flow; according to the order of the processing steps, chip-related attributes and initial priorities of each peripheral chip are configured, the chip-related attributes are used for the operation and maintenance of the chip, and the initial priority gradually increases according to the order of the processing flow; the peripheral chips include SoC chips and multiple video processing chips, and the SoC chip has the lowest initial priority; Initialize each peripheral chip in order from low to high priority to build a display driver architecture based on multi-level chips.

2. The method for constructing a display driver architecture based on a multi-level chip according to claim 1, characterized in that: The chip-related attributes include power operation attributes, initialization and deinitialization attributes, input and output interface attributes, operation interface attributes, and fault diagnosis interface attributes; The power operation attribute is used to obtain and control the power state of the peripheral chip; Initialization and deinitialization attributes are used to initialize and deinitialize peripheral chips; The input and output interface properties are used to obtain and control the input video stream format and output video stream format of the peripheral chip; The operation interface attribute is used to obtain and control the internal operation of the peripheral chip, wherein the internal operation includes processing operations in the video and control operations for controlling the working state of the peripheral chip, wherein the working state of the peripheral chip includes a normal working state, an abnormal working state, and a dormant state; The fault diagnosis interface attributes are used to obtain the fault cause of the peripheral chip and to control the fault repair operation on the peripheral chip.

3. The method for constructing a display driver architecture based on a multi-level chip according to claim 1, characterized in that: The construction method also includes: A peripheral chip whose initialization operation does not depend on the operation result of the initialization operation of other peripheral chips is defined as a single-rank chip, and the priority of the single-rank chip is adjusted according to the custom information to obtain the final priority of all peripheral chips.

4. A display driver architecture based on a multi-level chip, characterized in that: The display driver architecture is constructed by using the construction method based on a multi-level chip as claimed in claim 1.

5. A maintenance method for a display driver architecture based on a multi-level chip, characterized in that: Based on the multi-level chip based display driver architecture described in claim 4; The maintenance method comprises: A variable cycle detection method is used to detect whether each video processing chip is operating normally, and a detection result is obtained; the variable cycle detection method is to divide the detection cycle into a fast cycle and a slow cycle, the fast cycle detects the video processing chip according to a first frequency, and the slow cycle detects the video processing chip according to a second frequency, the first frequency is greater than the second frequency, and within a first specified time after the video processing chip is powered on or awakened, the video processing chip is detected according to the fast cycle, and when the detection results are abnormal for multiple consecutive times, it is determined that the video processing chip is operating abnormally, and when the fast cycle lasts for more than the second specified time and the detection results are normal, switch to the slow cycle, and when the detection result is abnormal, switch back to the fast cycle, and the first specified time is less than the second specified time; When the detection result is that the video processing chip operates abnormally, initialization operations are performed on each peripheral chip in order of priority, starting with the video processing chip that operates abnormally.

6. The maintenance method of the display driver architecture based on the multi-level chip according to claim 5, characterized in that: The step of determining whether the detection result is abnormal specifically includes the following steps: The actual register value of the video processing chip is obtained, and it is determined whether the actual register value is consistent with the theoretical register value of the video processing chip. If so, the detection result of the video processing chip is determined to be normal; if not, the detection result of the video processing chip is determined to be abnormal.

7. The maintenance method of the display driver architecture based on the multi-level chip according to claim 5, characterized in that: The step of determining whether the detection result is abnormal specifically includes the following steps: Obtain whether the video input parameter of the video processing chip of the next priority is normal. If so, determine that the detection result of the video processing chip of the previous priority is normal; if not, determine that the detection result of the video processing chip of the previous priority is abnormal.

8. The maintenance method of the display driver architecture based on the multi-level chip as claimed in claim 5, characterized in that: The maintenance method further comprises: After receiving the system sleep command, the peripheral chips at each level are deinitialized in sequence from high to low priority.

9. The maintenance method of the display driver architecture based on the multi-level chip according to claim 5, characterized in that: The maintenance method further comprises: Check whether the video stream received by the SoC chip is normal. If so, use a variable period detection method to check whether each video processing chip is operating normally; if not, control the SoC chip to perform fault handling according to the built-in fault handling process.

10. The maintenance method of the display driver architecture based on the multi-level chip according to claim 5, characterized in that: The maintenance method further comprises: Check whether the picture output by the connected display screen is normal. If so, use a variable period detection method to check whether each video processing chip is operating normally. If not, while using a variable period detection method to check whether each video processing chip is operating normally, control the display screen to perform fault handling according to the built-in fault handling process.

Images