Clamping circuit and storage and calculation integrated device

Abstract

The embodiment of the invention provides a clamping circuit and a storage and calculation integrated device. The clamping circuit comprises a clamping branch module, an amplifier module, a feedforward sampling module and a feedback sampling module, and the feedback sampling module is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first working state stage to generate a feedback output; the amplifier module is configured to amplify feedback output received from the feedback sampling module and then output the amplified feedback output to the feed-forward sampling module; the feed-forward sampling module is configured to sample a second voltage difference between the voltage of the output end of the amplifier module and the first reference voltage to generate feed-forward output; the clamping branch module is configured to clamp the clamping node to an ideal clamping voltage according to the feed-forward output in a second operating state. The clamping circuit can eliminate quiescent current errors caused by input voltage offset and voltage mismatch of the clamp itself.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a clamping circuit and a storage-computing integrated device. Background Art

[0002] Computing in memory (CIM) based on resistive memory cell arrays has shown great potential in achieving high-computing power neural network hardware acceleration. The network weights are stored based on the non-volatile adjustable conductivity of the device, and after applying a voltage pulse representing the input value, the matrix-vector multiplication result represented by the analog current value can be obtained. In order to achieve high parallelism and multi-bit input, the CIM array requires a large number of analog voltage drive circuits to apply input voltage to the bit line (BL) of the CIM array. At the same time, the readout circuit needs to accurately clamp the connected source line (SL), and finally quantize the current on the source line to obtain accurate matrix multiplication and addition results. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a clamping circuit, comprising: a clamping branch module, an amplifier module, a feedforward sampling module and a feedback sampling module, wherein the feedback sampling module is coupled to the clamping branch module and the clamping node, and the feedback sampling module is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first working state stage to generate a feedback output, wherein the ideal clamping voltage is a floating voltage; an input end of the amplifier module is coupled to the feedback sampling module, an output end of the amplifier module is coupled to the feedforward sampling module, and the amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module; the feedforward sampling module is coupled to the clamping branch module, and is configured to sample a second voltage difference between a voltage at an output end of the amplifier module and a first reference voltage to generate a feedforward output, and provide the feedforward output to the clamping branch module; the clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in a second working state.

[0004] For example, at least one embodiment of the present disclosure provides a clamping circuit that also includes: a first reference voltage generating module, coupled to the feedforward sampling module through a third node, coupled to the feedback sampling module through the clamping node, and configured to generate the first reference voltage.

[0005] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, wherein the first reference voltage generating module includes a first current generating unit, a second current generating unit and a second transistor, the control end of the second transistor is coupled to the first end of the second transistor, and the control end of the second transistor is coupled to the feedforward sampling module through the third node; the first current generating unit is coupled to the second end of the second transistor through the clamping node, and is configured to generate a first current; and the second current generating unit is coupled to the first end of the second transistor, and is configured to generate a second current, wherein the second current is equal to the first current.

[0006] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, wherein the clamping branch module includes a third current generating unit and a first transistor, wherein the control end of the first transistor is coupled to the feedforward sampling module through a first node, and the second end of the first transistor is coupled to the feedback sampling module through a second node; the third current generating unit is coupled to the second end of the first transistor and is configured to generate a third current, wherein a ratio of the third current to the first current is equal to a ratio of a width-to-length ratio of the first transistor to a width-to-length ratio of the second transistor, and a gate length of the first transistor is equal to a gate length of the second transistor.

[0007] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, wherein the feedback sampling module includes a first switch, a third switch and a first capacitor, and the feedforward sampling module includes a second switch and a second capacitor, and according to the closed state of the first switch, the second switch and the third switch, the first capacitor samples the first voltage difference, and the second capacitor samples the second voltage difference.

[0008] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, wherein the amplifier module includes a differential amplifier or a single-ended amplifier.

[0009] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, in which the positive input terminal of the differential amplifier is coupled to the first end of the first switch and is configured to receive the clamping reference voltage, the negative input terminal of the differential amplifier is coupled to the second end of the first switch, and the output terminal of the differential amplifier is coupled to the first end of the second capacitor.

[0010] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, in which the single-ended amplifier includes a first resistor, a third transistor and a fifth transistor, the control end of the third transistor is coupled to the second end of the first switch, the first end of the third transistor is coupled to the second end of the fifth transistor, the first end of the fifth transistor is coupled to the first resistor, and the first end of the fifth transistor is coupled to the first end of the second capacitor as the output end of the amplifier module.

[0011] For example, in at least one embodiment of the present disclosure, a clamp circuit is provided, wherein the clamp circuit further includes a second reference voltage generating module, the second reference voltage generating module is coupled to the first end of the second switch and is configured to provide the clamp reference voltage.

[0012] For example, in at least one embodiment of the present disclosure, a clamping circuit is provided, wherein the second reference voltage generating module includes a fourth current generating unit, a fourth transistor and a sixth transistor, the fourth current generating unit is coupled to the first end of the sixth transistor and is configured to generate a fourth current, the second end of the sixth transistor is coupled to the first end of the fourth transistor, the control end of the fourth transistor is coupled to the first end of the sixth transistor, and the control end of the fourth transistor is coupled to the first end of the first switch, wherein a ratio of a current flowing through the third transistor to the fourth current is equal to a ratio of a width-to-length ratio of the fourth transistor to a width-to-length ratio of the third transistor, and a gate length of the fourth transistor is equal to a gate length of the third transistor.

[0013] For example, at least one embodiment of the present disclosure provides a clamping circuit that also includes: a low-resistance path module and a fourth switch, wherein the first ends of the low-resistance path module and the fourth switch are coupled to the clamping node, and the low-resistance path module is configured to provide the ideal clamping voltage to the clamping node when the fourth switch is closed.

[0014] At least one embodiment of the present disclosure also provides a storage and computing integrated device, comprising: a memristor array, an input circuit and an output circuit, wherein the output circuit comprises a plurality of clamping circuits as described in any of the above embodiments, the input circuit is coupled to the memristor array, and is configured to provide a plurality of input voltages to the memristor array, the memristor array is respectively coupled to a plurality of clamping circuits through a plurality of clamping nodes of the plurality of clamping circuits, and is configured to provide the floating voltage as the ideal clamping voltage to the plurality of clamping circuits respectively when the plurality of input voltages are zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0016] Figure 1 A current-type storage-computation integrated circuit structure is shown;

[0017] Figure 2 A self-zeroing input drive and clamping structure is shown;

[0018] Figure 3A A schematic structural diagram of a clamping circuit provided by at least one embodiment of the present disclosure is shown;

[0019] Figure 3B A schematic structural diagram of another clamping circuit provided by at least one embodiment of the present disclosure is shown;

[0020] Figure 4 A schematic structural diagram of a clamping circuit based on differential amplification provided by at least one embodiment of the present disclosure is shown;

[0021] Figure 5 A schematic diagram showing the structure of a clamping circuit based on single-ended amplification provided by at least one embodiment of the present disclosure is shown; and

[0022] Figure 6 A schematic diagram of the structure of a storage-computing integrated device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] A memristor (such as a resistive memory cell, a phase change memory cell, a conductive bridge memory cell, etc.) is a non-volatile device whose conductance state can be adjusted by applying an external stimulus. As a two-terminal device, a memristor has the characteristics of adjustable resistance and non-volatility, so it is widely used in storage-computing (or in-memory computing).

[0026] Computing in memory (CIM) based on resistive memory cell arrays has shown great potential in achieving high-computation neural network hardware acceleration. The non-volatile adjustable conductivity of the device is used to store network weights, and after applying voltage pulses representing the input values, the matrix-vector multiplication results represented by analog current values ​​can be obtained.

[0027] However, due to factors such as process fluctuations and layout parasitic effects, there are a lot of mismatch-induced offset voltages in the circuit. For example, under the influence of mismatch, the actual output voltage of the unit gain buffer used for the bit line (BL) driver circuit and the source line (SL) clamp circuit deviates from the ideal voltage of the reference input, resulting in errors between the calculated result and the ideal result. In order to solve the mismatch problem, for example, dynamic self-calibration or static calibration can be used to calibrate the errors of the clamp current on the BL driver circuit and the source line. However, the additional overhead of the calibration circuit will lead to a decrease in computational density, and frequent calibration refreshes will cause a decrease in system efficiency.

[0028] For example, Figure 1 A current-type storage-computation-in-one circuit structure is shown.

[0029] like Figure 1As shown, the weight is stored in the memristor array in the form of conductance G[i,j] of a storage unit (also called a "memristor" or "weight unit"), and the storage unit can be a 2T2R structure or a 1T1R structure. The weight unit of the 1T1R structure includes a switching transistor and a memristor, and the weight unit of the 2T2R structure includes two switching transistors and two memristors. For example, the 2T2R structure is arranged as a difference type, which can be used to characterize positive and negative weight values. For example, a memristor can be a resistive memory, a phase change memory, a conductive bridge memory, etc., which is a non-volatile device whose conductivity state can be adjusted.

[0030] like Figure 1 As shown, the digital-to-analog converter DAC applies the analog voltage VCM+VIN[i] representing the input data to the bit line BL[i] of the memristor array (for example, arranged in the horizontal direction), and the source line SL of the memristor array (for example, arranged in the vertical direction) is clamped to a fixed voltage VCM. In the case of all 0 inputs (i.e., VIN[i] = 0), the voltage difference across all storage cells in the memristor array is 0, and the current on the source line SL. After applying the input voltage VIN[i], the current on SL[j] represents the result of the matrix multiplication operation:

[0031]

[0032] That is, it represents the result of vector dot product, and finally the readout circuit quantizes and reads out the current to obtain the calculation result.

[0033] However, due to process fluctuations and layout parasitic effects, there is a mismatch problem in the circuit, which leads to static deviations between the input voltage of BL and the clamping voltage of SL and their ideal values. Figure 1 As shown in the figure, the analog voltage output by the DAC changes from VCM+VIN[i] to VCM+VIN[i]+ΔV[i], and the clamping voltage on the SL changes to VCM+ΔVC[j]. Due to the mismatch problem in the circuit, in the case of all-zero input (i.e., VIN[i]=0), the current of SL[j] is no longer the ideal zero current, but is:

[0034]

[0035] After that, when the input voltage is applied, according to the linear current superposition theorem, there will always be a static error ΔI between the actual current on SL and the ideal current. SL[j] .

[0036] In order to eliminate the mismatch in the storage-computation integrated circuit, for example, Figure 2 The self-zeroing input drive and clamping structure shown is used to eliminate the input mismatch error of the unity gain buffer used for input drive and SL clamp in the storage-computation integrated circuit.

[0037] First, switches SW.1 and SW.2 are closed, and switch SW.3 is opened, and the mismatch between the positive and negative inputs is sampled at both ends of the zeroing capacitor C1; then, switch SW.1 is opened to end the sampling; after that, switch SW.2 is opened and switch SW.3 is closed, and the sampled mismatch voltage is compensated into the loop, so that the voltage output by the amplifier (the voltage applied to the bit line BL) is the ideal voltage. Based on a similar principle, the clamping voltage on the source line SL can be the ideal clamping voltage.

[0038] The inventors of the present disclosure have noticed that a high-parallelism storage-computation integrated array requires a large number of input drive circuits, and accordingly also requires the use of a large number of self-zeroing input drives and clamping structures. The use of zeroing capacitors will reduce circuit density, thereby reducing computing density, and due to leakage of zeroing capacitors, the storage-computation integrated circuit needs to be refreshed frequently, which in turn causes a decrease in system efficiency.

[0039] In view of the above shortcomings, one or more embodiments of the present disclosure propose a clamping circuit and a storage-computing integrated device including the clamping circuit.

[0040] The clamping circuit of at least one embodiment of the present disclosure includes: a clamping branch module, an amplifier module, a feedforward sampling module and a feedback sampling module, wherein the feedback sampling module is coupled to the clamping branch module and the clamping node, and the feedback sampling module is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first working state stage to generate a feedback output, wherein the ideal clamping voltage is a floating voltage; the input end of the amplifier module is coupled to the feedback sampling module, the output end of the amplifier module is coupled to the feedforward sampling module, and the amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module; the feedforward sampling module is coupled to the clamping branch module, and is configured to sample a second voltage difference between a voltage at an output end of the amplifier module and the first reference voltage to generate a feedforward output, and provide the feedforward output to the clamping branch module; the clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in the second working state.

[0041] The clamping circuit adaptively changes the clamping voltage of SL so that the current of SL is 0 when all inputs are zero, thereby eliminating the static current error caused by input voltage offset and the voltage mismatch of the clamp itself, improving the robustness to input circuit mismatch, and thus improving system efficiency and density.

[0042] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0043] Figure 3A A schematic structural diagram of a clamping circuit provided by at least one embodiment of the present disclosure is shown.

[0044] like Figure 3A As shown, the clamping circuit includes: a clamping branch module 310, an amplifier module 320, a feedforward sampling module 330 and a feedback sampling module 340. The feedback sampling module 340 is coupled to the clamping branch module 310 and the clamping node SLC, and the feedback sampling module 340 is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage (hereinafter referred to as “V_SLC”) received by the feedback sampling module 340 from the clamping node SLC in the first working state stage to generate a feedback output. The input end of the amplifier module 320 is coupled to the feedback sampling module 340, the output end of the amplifier module 320 is coupled to the feedforward sampling module 330, and the amplifier module 320 is configured to amplify the feedback output received from the feedback sampling module 340 and output it to the feedforward sampling module 330. The feedforward sampling module 330 is coupled to the clamping branch module 310, and is configured to sample a second voltage difference between the voltage at the output terminal AOUT of the amplifier module 320 and the first reference voltage to generate a feedforward output, and provide the feedforward output to the clamping branch module 310. The clamping branch module 310 is configured to clamp the clamping node SLC to an ideal clamping voltage according to the feedforward output in the second working state.

[0045] In the embodiment of the present disclosure, the first working state stage is the sampling stage, and the external array provides the ideal clamping voltage to the feedback sampling module 340 through the clamping node; the second working state is the clamping working state, at which time the clamping branch 310 clamps the clamping node SLC to the ideal clamping voltage. The ideal clamping voltage is a floating voltage, that is, the voltage when the bit line BL of the external array is in the all-0 input and the source line SL is in the floating state. The feedback sampling module 340 is also configured to receive a clamping reference voltage VCM.

[0046] For example, the amplifier module 320 may include a differential amplifier (eg, Figure 3A as shown) or a single-ended amplifier (as Figure 3B When the amplifier module 320 includes a differential amplifier, the positive input terminal of the amplifier module 320 receives the clamp reference voltage VCM, and the negative input terminal receives the feedback output output by the feedback sampling module 340 .

[0047] Figure 3B FIG. 2 shows a schematic diagram of the structure of another clamping circuit provided by at least one embodiment of the present disclosure. Figure 3B As shown, the amplifier module 320 includes a single-ended amplifier, and the input end of the amplifier module 320 receives the feedback output output by the feedback sampling module 340. Figure 3B In the clamp circuit shown, the structure and function of the clamp branch module, the feedforward sampling module and the feedback sampling module can refer to Figure 3A The clamping branch module 310 , the feedforward sampling module 330 and the feedback sampling module 340 are not described in detail here.

[0048] Figure 4 A schematic structural diagram of a clamping circuit based on differential amplification provided by at least one embodiment of the present disclosure is shown.

[0049] like Figure 4 As shown, the clamp circuit 400 includes a clamp branch module 410, a feedforward sampling module 430, a feedback sampling module 440, and an amplifier module 420, wherein the amplifier module 420 includes a differential amplifier.

[0050] like Figure 4 As shown, the clamp circuit 400 further includes a reference voltage generating module G1, which is coupled to the feedforward sampling module 430 via the node N3 and to the feedback sampling module 440 via the clamp node SLC. The reference voltage generating module G1 is configured to generate a reference voltage REFG and provide it to the feedforward sampling module 430.

[0051] For example, the reference voltage generating module G1 includes a current generating unit I.G1, a current generating unit I.G2 and a transistor NM2. The control terminal (e.g., gate) of the transistor NM2 is coupled to the first terminal (e.g., source) of the transistor NM2, and the control terminal of the transistor NM2 is coupled to the feedforward sampling module 430 through the node N3. The current generating unit I.G1 is coupled to the second terminal (e.g., drain) of the transistor NM2 through the clamping node SLC, and is configured to generate a first current I1. The current generating unit I.G2 is coupled to the first terminal (e.g., source) of the transistor NM2, and is configured to generate a second current I2, wherein the second current I2 is equal to the first current I1.

[0052] For example, the clamping branch module 410 includes a current generating unit I.C1 and a transistor NM1, wherein a control terminal (e.g., a gate) of the transistor NM1 is coupled to the feedforward sampling module 430 through a node N1, and a second terminal (e.g., a source) of the transistor NM1 is coupled to the feedback sampling module 440 through a node N2. The current generating unit I.C1 is coupled to the second terminal of the transistor NM1 through a node N2, and is configured to generate a third current I3. The ratio of the third current I3 to the first current I1 is equal to the ratio of the width-to-length ratio of the transistor NM1 to the width-to-length ratio of the transistor NM2, i.e., I3 / I2=(W / L) NM1 / (W / L) NM2 , and the gate length of transistor NM1 is equal to the gate length of transistor NM2.

[0053] It should be noted that based on the matching relationship between the clamping branch and the reference voltage generating module G1 (ie, I3 / I2 = (W / L) NM1 / (W / L) NM2 , and the gate length of the first transistor NM1 is equal to the gate length of the transistor NM2), the first reference voltage REFG is an ideal clamping gate voltage that makes the voltage of the second end (ie, the source) of the transistor NM1 equal to the ideal clamping voltage V_SLC.

[0054] For example, the feedback sampling module 440 includes a switch SW.1, a switch SW.3 and a capacitor C1, and the feedforward sampling module 430 includes a switch SW.2 and a capacitor C2. According to the closed state of the switches SW.1, SW.2 and SW.3, the capacitor C1 samples the first voltage difference, and the capacitor C2 samples the second voltage difference. As mentioned above, the first voltage difference is the voltage difference between the clamp reference voltage VCM and the ideal clamp voltage V_SLC received by the feedback sampling module 340 from the clamp node SLC in the first working state; the second voltage difference is the voltage difference between the voltage of the output terminal AOUT of the amplifier module 320 and the first reference voltage REFG.

[0055] For example, the positive input terminal of the differential amplifier 420 is coupled to the first terminal of the switch SW.1 and is configured to receive the clamp reference voltage VCM, the negative input terminal of the differential amplifier is coupled to the second terminal of the switch SW.1, and the output terminal AOUT of the differential amplifier is coupled to the first terminal of the capacitor C2.

[0056] For example, the clamp circuit 400 may further include a low resistance path module 450 and a switch SW.4. The first ends of the low resistance path module 450 and the switch SW.4 are coupled to the clamp node SLC, and the low resistance path module 450 is configured to provide an ideal clamp voltage V_SLC to the clamp node SLC when the switch SW.4 is closed. The second end of the switch SW.4 is coupled to a source line SL of a memristor array (e.g., a resistive random access memory (RRAM) array 460). For example, the switch SW.4 may be a high voltage switch.

[0057] For example, the low-resistance path module 450 includes a switch SW.5 and a resistor R2, the first end of the switch SW.5 applies a clamp reference voltage VCM, the second end of the switch SW.5 is coupled to the first end of the resistor R2, the second end of the resistor R2 is coupled to the first end of the switch SW.4, that is, the second end of the resistor R2 is coupled to the clamp node SLC.

[0058] In the clamping circuit provided in the above embodiment of the present disclosure, based on the low-resistance path module 4 controlled by the switch SW.5, it is possible to avoid the problem that the floating voltage on the source line is unstable and the charging speed of the capacitor C1 is too slow, which is caused by the memory cells in the RRAM array 460 being in an unformed (or initialized or pre-processed) state (i.e., an unforming state) or most devices being in a high-resistance state. Figure 4 and Figure 5 A low-impedance path controlled by SW.4 is added to the structure to connect to VCM, which is used to provide an ideal clamping voltage VCM when the array is a high-impedance load.

[0059] When a plurality of memory cells in the RRAM array 460 are in an unformed state, the switch SW.5 is closed, and the source line SL voltage of the RRAM array 460 is clamped to the clamp reference voltage VCM. At this time, due to the input circuit ( Figure 4 Not shown, please refer to Figure 6 ) has mismatch, and there is still a fixed current deviation on the source line SL. Therefore, during the programming verification process, the output circuit ( Figure 4 Not shown, please refer to Figure 6 ) First read the current I when all 0 inputs are present OS , and then read the current I after applying the read voltage to the memory cell corresponding to the programmed row DAT , then the actual cell current (i.e., the current passing through the memory cell) at the ideal read voltage is I DAT -I OS , iterative programming and read verification are performed based on the actual cell current.

[0060] After a plurality of memory cells are formed, the load impedance of the RRAM array 460 becomes low. At this time, clamping the source line SL voltage to the clamp reference voltage VCM will result in excessive deviation current, causing the range of the analog-to-digital converter (ADC) to be saturated, thereby reducing the dynamic range of the ADC. Therefore, the switch SW.5 is disconnected, and the voltage of the source line SL after the array is floated is used as the ideal clamp voltage, and then clamping and quantization can be performed normally.

[0061] It should be noted that Figure 4 The clamping reference voltage VCM in is the zero input voltage under the condition of no mismatch, and is also the input voltage of the positive input terminal of the differential amplifier 420.

[0062] For example, the working process of the clamp circuit 400 when reading the source line current of the RRAM array 460 is as follows.

[0063] In the first working state stage: the RRAM array 460 is in the computing mode, the switch SW.5 is closed, and the bit lines BL of the array are all 0 inputs (i.e. Figure 1 VIN[i]=0 in the input voltage). Switches SW.1 and SW.2 are closed, switch SW.3 is opened, source line SL of RRAM array 460 is coupled only to reference voltage generating module G1, current generated by current generating unit I.G1 is equal to current generated by current generating unit I.G2, source line SL is in floating state, voltage on source line SL is taken as ideal clamping voltage V_SLC, so that current on source line SL is 0 when all BL are input as 0. At this time, capacitor C1 in feedback sampling module 440 samples voltage difference (i.e., first voltage difference) between clamping reference voltage VCM and ideal clamping voltage V_SLC, and capacitor C2 of feedforward sampling module 430 samples voltage difference (i.e., second voltage difference) between voltage at output terminal AOUT of differential amplifier 420 and reference voltage REFG.

[0064] In the second working state stage: switch SW.1 is first opened, and after a period of time (i.e., after the voltage at the output terminal AOUT of the differential amplifier 420 becomes stable), switch SW.2 is opened, and the capacitors C1 and C2 finish sampling one after another. Then switch SW.3 is closed, and a closed loop is established between, for example, the feedforward sampling module 430, the clamping branch module 410, the feedback sampling module 440, and the amplifier module 420 (the schematic diagram of the closed loop can also be referred to Figure 3A ), at this time, the voltage of the clamping node SLC is clamped to the ideal clamping voltage V_SLC.

[0065] In the third working state stage: multiple rounds of reading calculations are performed until the capacitors C1 and C2 leak, C1 and C2 are refreshed, and the sampling is returned to the first working state stage.

[0066] In the above embodiment, the clamping circuit 400 eliminates the deviation between the clamping reference voltage VCM (i.e., the actual clamping voltage) and the ideal clamping voltage V_SLC through a feedback sampling module (e.g., the sampling operation of capacitor C1), thereby eliminating the influence of the input (driving) circuit mismatch; and eliminates the deviation between the output voltage of the amplifier module and the standard clamping gate voltage REFG through a feedforward sampling module (e.g., the sampling operation of capacitor C2), thereby eliminating the mismatch of the clamping structure itself.

[0067] Figure 5 A schematic structural diagram of a clamping circuit based on single-ended amplification provided by at least one embodiment of the present disclosure is shown.

[0068] like Figure 5 As shown, the clamping circuit 500 includes a clamping branch module 510, a feedforward sampling module 530, a feedback sampling module 540, an amplifier module 520 and a reference voltage generating module G1, wherein the amplifier module 520 includes a single-ended amplifier, and the matching relationship between the clamping branch module 510 and the reference voltage generating module G1 is Figure 4 The matching relationship between the middle clamping branch module 410 and the reference voltage generating module G1 is the same.

[0069] For example, the single-ended amplifier includes a resistor R1, a transistor NM3 and a transistor NM3, the control end of the transistor NM3 is coupled to the second end NBIAS of the switch SW.1, the first end of the transistor NM3 is coupled to the second end of the transistor NM3, the first end of the transistor NM3 is coupled to the resistor R1, and the first end of the transistor NM5 in the amplifier module 520 serves as the output end AOUT of the amplifier module 520 and is coupled to the first end of the capacitor C2 of the feedforward sampling module 530.

[0070] For example, the clamping circuit 500 further includes a reference voltage generating module G2, which is coupled to a first end of the switch SW.1 in the feedback sampling module 540 and is configured to provide a clamping reference voltage REFB (equivalent to Figure 3A , Figure 3B and Figure 4 The clamping reference voltage VCM in .

[0071] For example, the reference voltage generating module G2 includes a current generating unit I.B1, a transistor NM4, and a transistor NM6. The current generating unit I.B1 is coupled to the first end of the transistor NM6 and is configured to generate a fourth current I4. The end of the transistor NM6 is coupled to the first end of the transistor NM4, and the control end of the transistor NM4 and the first end of the transistor NM6 are both coupled to the first end of the switch SW.1 in the feedback sampling module 540. The ratio of the current flowing through the transistor NM3 to the fourth current I4 is equal to the ratio of the width-to-length ratio of the transistor NM4 to the width-to-length ratio of the transistor NM3, that is, I(NM3) / I4=(W / L) NM3 / (W / L) NM4 =k, and the gate length of transistor NM4 is equal to the gate length of transistor NM3.

[0072] In addition, for Figure 5 The structures and functions of other modules of the clamping circuit 500 shown in the figure, such as the clamping branch module 510, the feedforward sampling module 530, the feedback sampling module 540, the reference voltage generating module G1, etc., can refer to the above Figure 4The clamping branch module 410 , the feedforward sampling module 430 , the feedback sampling module 440 and the reference voltage generating module G1 in the clamping circuit 400 are not described in detail here.

[0073] For example, the working process of the clamp circuit 500 when reading the source line current of the RRAM array 560 is as follows.

[0074] In the first working state stage: the RRAM array 560 is in the computing mode, the switch SW.5 is closed, and the bit lines BL of the array are all 0 inputs (i.e. Figure 1 VIN[i]=0 in the figure). Switches SW.1 and SW.2 are closed, and switch SW.3 is open. The source line SL of the RRAM array 560 is only coupled to the reference voltage generating module G1. The current generated by the current generating unit I.G1 is equal to the current generated by the current generating unit I.G2. The source line SL is in a floating state. The voltage on the source line SL is used as the ideal clamping voltage V_SLC, so that the current on the source line SL is 0 when all BL inputs are 0. At this time, the first reference voltage REFG voltage is the ideal clamping gate voltage that makes the source voltage of the transistor NM1 V_SLC, and the clamping reference voltage REFB is equivalent to Figure 3A , Figure 3B and Figure 4 The capacitor C1 in the feedback sampling module 540 samples the voltage difference (i.e., the first voltage difference) between the clamping reference voltage REFB and the ideal clamping voltage V_SLC, and the capacitor C2 of the feedforward sampling module 530 samples the voltage difference (i.e., the second voltage difference) between the voltage at the output terminal AOUT of the single-ended common source amplifier 520 and the first reference voltage REFG.

[0075] In the second working state stage: switch SW.1 is turned off, and after a period of time (i.e., after the voltage at the output terminal AOUT of the single-ended common source amplifier 520 becomes stable), switch SW.2 is turned off, and capacitors C1 and C2 finish sampling one after another. Then switch SW.3 is closed, and a closed loop is established between, for example, the feedforward sampling module 530, the clamping branch module 510, the feedback sampling module 540, and the amplifier module 520 (the schematic diagram of the closed loop can also be referred to Figure 3B ), at this time, the voltage of the clamping node SLC is clamped to the ideal clamping voltage V_SLC, the gate voltage of the transistor NM3 (i.e., the voltage at the node N1) still maintains the clamping reference voltage REFB under the action of the closed loop, and the current flowing through the transistor NM3 satisfies the relationship I(NM3)=k×I4.

[0076] In the third working state stage: multiple rounds of reading calculations are performed until the capacitors C1 and C2 leak, C1 and C2 are refreshed, and the sampling is returned to the first working state stage.

[0077] In the above embodiment, the clamping circuit 500 eliminates the deviation between the clamping reference voltage REFB (i.e., the actual clamping voltage) and the ideal clamping voltage V_SLC through the feedback sampling module 540 (e.g., the sampling operation of the capacitor C1), thereby eliminating the influence of the input (driving) circuit mismatch; and eliminates the deviation between the output voltage of the amplifier module 520 and the standard clamping gate voltage REFG through the feedforward sampling module 530 (e.g., the sampling operation of the capacitor C2), thereby eliminating the mismatch of the clamping structure itself.

[0078] Figure 6 A schematic diagram of the structure of a storage-computing integrated device provided by at least one embodiment of the present disclosure is shown.

[0079] like Figure 6 As shown, the storage-computing integrated device 600 includes a memristor array, an input circuit and an output circuit, wherein the output circuit (such as Figure 5 The "clamping / readout circuit" in Figure 3A , Figure 3B , Figure 4 or Figure 5 The input circuit is coupled to the memristor array and is configured to provide multiple input voltages to the memristor array. The memristor array is coupled to multiple clamping circuits through multiple clamping nodes of the multiple clamping circuits, respectively, and is configured to provide floating voltages to the multiple clamping circuits as ideal clamping voltages when the multiple input voltages are zero. The multiple clamping circuits sample the ideal clamping voltages respectively, and clamp the source line SL of the memristor array to the ideal clamping voltage under any computing load condition through the feedback sampling module.

[0080] For example, the storage and computing integrated device of any embodiment of the present disclosure can be used to implement a data processing device, such as for preparing a neural network processor chip, or as a coprocessor to collaborate with a central processing unit to implement data processing functions, etc., and the present disclosure does not limit this.

[0081] In addition to the above exemplary descriptions, there are a few points that need to be explained:

[0082] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0083] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0084] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A clamping circuit, comprising: Clamping branch module, amplifier module, feedforward sampling module and feedback sampling module, wherein, The feedback sampling module is coupled to the clamping branch module and the clamping node, and the feedback sampling module is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first working state stage to generate a feedback output, wherein the ideal clamping voltage is a floating voltage; The input end of the amplifier module is coupled to the feedback sampling module, the output end of the amplifier module is coupled to the feedforward sampling module, and the amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module; The feedforward sampling module is coupled to the clamping branch module and is configured to sample a second voltage difference between a voltage at an output terminal of the amplifier module and a first reference voltage to generate a feedforward output, and provide the feedforward output to the clamping branch module; The clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in a second working state.

2. The clamping circuit according to claim 1, further comprising: The first reference voltage generating module is coupled to the feedforward sampling module through a third node and coupled to the feedback sampling module through the clamping node, and is configured to generate the first reference voltage.

3. The clamping circuit according to claim 2, wherein: The first reference voltage generating module includes a first current generating unit, a second current generating unit and a second transistor. The control terminal of the second transistor is coupled to the first terminal of the second transistor, and the control terminal of the second transistor is coupled to the feedforward sampling module through the third node; The first current generating unit is coupled to the second end of the second transistor through the clamping node and is configured to generate a first current; as well as The second current generating unit is coupled to the first end of the second transistor and is configured to generate a second current, wherein the second current is equal to the first current.

4. The clamping circuit according to claim 3, wherein: The clamping branch module includes a third current generating unit and a first transistor. The control terminal of the first transistor is coupled to the feedforward sampling module through a first node, and the second terminal of the first transistor is coupled to the feedback sampling module through a second node; The third current generating unit is coupled to the second end of the first transistor and is configured to generate a third current. The ratio of the third current to the first current is equal to the ratio of the width-to-length ratio of the first transistor to the width-to-length ratio of the second transistor, and the gate length of the first transistor is equal to the gate length of the second transistor.

5. The clamping circuit according to claim 1, wherein: The feedback sampling module includes a first switch, a third switch and a first capacitor, and the feedforward sampling module includes a second switch and a second capacitor. According to the closing states of the first switch, the second switch, and the third switch, the first capacitor samples the first voltage difference, and the second capacitor samples the second voltage difference.

6. The clamping circuit according to claim 5, wherein: The amplifier module includes a differential amplifier or a single-ended amplifier.

7. The clamping circuit according to claim 6, wherein: The positive input terminal of the differential amplifier is coupled to the first end of the first switch and is configured to receive the clamp reference voltage, the negative input terminal of the differential amplifier is coupled to the second end of the first switch, and the output terminal of the differential amplifier is coupled to the first end of the second capacitor.

8. The clamping circuit according to claim 6, wherein: The single-ended amplifier includes a first resistor, a third transistor and a fifth transistor, The control terminal of the third transistor is coupled to the second terminal of the first switch, the first terminal of the third transistor is coupled to the second terminal of the fifth transistor, The first end of the fifth transistor is coupled to the first resistor, and the first end of the fifth transistor is coupled to the first end of the second capacitor as an output end of the amplifier module.

9. The clamping circuit as claimed in claim 8, wherein: The clamp circuit further includes a second reference voltage generating module, which is coupled to the first end of the second switch and configured to provide the clamp reference voltage.

10. The clamping circuit according to claim 9, wherein: The second reference voltage generating module includes a fourth current generating unit, a fourth transistor and a sixth transistor. The fourth current generating unit is coupled to the first end of the sixth transistor and is configured to generate a fourth current, the second end of the sixth transistor is coupled to the first end of the fourth transistor, the control end of the fourth transistor is coupled to the first end of the sixth transistor, and the control end of the fourth transistor is coupled to the first end of the first switch, The ratio of the current flowing through the third transistor to the fourth current is equal to the ratio of the width-to-length ratio of the fourth transistor to the width-to-length ratio of the third transistor, and the gate length of the fourth transistor is equal to the gate length of the third transistor.

11. The clamping circuit of claim 1 , further comprising: A low resistance path module and a fourth switch, wherein: The low-resistance path module and the first end of the fourth switch are coupled to the clamp node, and the low-resistance path module is configured to provide the ideal clamp voltage to the clamp node when the fourth switch is closed.

12. A storage and computing integrated device, comprising: A memristor array, an input circuit and an output circuit, wherein: The output circuit includes a plurality of clamping circuits as described in any one of claims 1 to 11, The input circuit is coupled to the memristor array and is configured to provide a plurality of input voltages to the memristor array. The memristor array is coupled to the plurality of clamping circuits respectively through the plurality of clamping nodes of the plurality of clamping circuits, and is configured to provide the floating voltage as the ideal clamping voltage to the plurality of clamping circuits respectively when the plurality of input voltages are zero.

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