Glass substrate structure, semiconductor packaging structure and manufacturing method thereof

Abstract

The invention discloses a glass substrate structure, a semiconductor packaging structure and a manufacturing method thereof, and the glass substrate structure comprises a glass core plate which is provided with a first surface and a second surface which are opposite to each other; the blind groove is formed in the glass core plate from the first surface; the one or more first conductive through holes penetrate through the glass core plate and are exposed out of the blind groove and the second surface; the one or more second conductive through holes penetrate through the glass core plate and are exposed on the first surface and the second surface; the TSV chip is embedded in the blind groove, the TSV chip is provided with one or more first micro convex points formed on the surface of the TSV chip, and the first micro convex points are connected with the first conductive through holes in a thermocompression bonding mode; and the insulating layer is formed between the TSV chip and the blind slot. According to the glass substrate structure, the glass substrate and the active component can be systematically integrated, the active component is embedded in the glass substrate, the wiring density is improved, meanwhile, back power supply is provided, and high-precision, high-strength, high-reliability interconnection and high-integration-level multi-chip packaging can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a glass substrate structure, a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] The current AI computing and processor chip packaging size is getting larger and larger, and large-size FCBGA warpage is facing a bottleneck. As large-size chips continue to increase the thickness of the core board to overcome the warpage problem, the through-hole distance will become longer and the through-hole transmission loss will increase, and it is impossible to simultaneously meet the high modulus and dielectric constant D k , dielectric loss factor D f Indicators: Small expansion and contraction deformation under high temperature, which can reduce graphic distortion by 50%. Glass substrates can improve the yield and reliability of the system. If mass production is successfully achieved, it will bring about a new generation of optical communication revolution. The advantages of glass substrates are: glass substrates can overcome the warping problem of organic substrates in large-size packaging of AI chips, strengthen the structure of GPUs and achieve better electrical and mechanical reliability (can be shared with ABF / PI) to achieve ultra-large size and high assembly yield packaging; glass substrates have ultra-low roughness (super flatness), which can improve the focus of lithography; can provide the dimensional stability required for tight stacked interconnections, and have the potential to increase interconnection density and optical interconnection integration by 10 times; glass substrates provide AI chip designers with greater creative space in terms of design rules for power transmission and signal routing; can be seamlessly interconnected and integrated with optical components, and can embed inductors and capacitors into glass substrates at higher temperature processes; there are also better power transmission solutions, while achieving the required high-speed signals at a lower cost; glass substrates are expected to be used in artificial intelligence, high-performance storage and large-model high-performance computing (optoelectronic-based computing and RF, silicon photonic integration, high-bandwidth memory), 6G communications and other fields.

[0003] However, in the production process of glass substrates, there are still many process problems. How to systematically integrate glass substrates and active components to achieve high-precision, high-strength, high-reliability interconnection and high-integration packaging remains to be improved. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the above-mentioned technology to a certain extent. To this end, the purpose of the present invention is to provide a glass substrate structure, a semiconductor packaging structure and a manufacturing method thereof, wherein the glass substrate structure can integrate the glass substrate and active components into a system, embed active components on the glass substrate to improve the wiring density and provide back power supply, and realize high-precision, high-strength, high-reliability interconnection and high-integration multi-chip packaging.

[0005] To achieve the above object, the present invention provides a glass substrate structure in a first aspect, which includes:

[0006] a glass core board having opposing first and second surfaces;

[0007] a blind groove formed in the glass core board from the first surface;

[0008] One or more first conductive through holes, penetrating the glass core board and exposed at the blind groove and the second surface;

[0009] One or more second conductive vias extending through the glass core board and exposed at the first surface and the second surface;

[0010] A TSV chip is embedded in the blind groove, the TSV chip has one or more first micro bumps formed on the surface of the TSV chip, and the first micro bumps are connected to the first conductive vias by thermocompression bonding;

[0011] An insulating layer is formed between the TSV chip and the blind trench.

[0012] According to a glass substrate structure of the present invention, a glass core board is used as a support, and a TSV chip is embedded in the glass core board. The micro-bumps on the back of the TSV chip are connected to the conductive through holes on the glass core board by thermocompression bonding, so that the glass core board and active components can be systematically integrated in 3D. Active components are embedded in the glass core board to improve the wiring density while providing back power supply, so that high-precision, high-strength, high-reliability interconnection and high-integration multi-chip packaging can be achieved in the subsequent packaging structure.

[0013] In addition, the glass substrate structure proposed in the present invention may also have the following additional technical features:

[0014] Optionally, the TSV chip is an active chip having one or more conductive TSVs, and the conductive TSVs are electrically connected to the first micro bumps.

[0015] Optionally, the insulating layer is formed between the bottom of the TSV chip and the blind trench.

[0016] To achieve the above object, the second aspect of the present invention provides a method for manufacturing a glass substrate structure, which comprises the following steps:

[0017] providing a glass core panel having opposing first and second surfaces;

[0018] Opening a hole in the glass core board from the first surface to form a blind groove;

[0019] Through-glass vias (TGVs) are formed by drilling holes in the glass core plate from the first surface and from the bottom of the blind groove to form one or more first TGV holes and a second TGV hole;

[0020] Filling the first TGV hole and the second TGV hole with a conductive material to form a first conductive via and a second conductive via;

[0021] Providing a TSV chip, and connecting a first micro bump of the TSV chip to the first conductive via by thermocompression bonding, so as to embed the TSV chip in the blind groove;

[0022] An insulating layer is formed between the TSV chip and the blind trench.

[0023] According to the manufacturing method of the glass substrate structure of the present invention, a TSV chip is embedded in a glass core board, and the micro-bumps on the back side of the TSV chip are connected to the conductive through holes on the glass core board by thermocompression bonding, so that the glass core board and active components can be systematically 3D integrated, and active components are embedded in the glass core board to improve the wiring density while providing back power supply, so that high-precision, high-strength, high-reliability interconnection and high-integration multi-chip packaging can be achieved in the subsequent packaging structure.

[0024] In addition, the manufacturing method of the glass substrate structure proposed in the present invention may also have the following additional technical features:

[0025] Optionally, the step of filling the first TGV hole and the second TGV hole with a conductive material comprises:

[0026] forming a seed layer on the first surface, the second surface, the inner surface of the blind groove, the inner wall of the first TGV hole, and the inner wall of the second TGV hole;

[0027] Filling a conductive layer in the first TGV hole and the second TGV hole;

[0028] The first surface, the second surface, the seed layer in the blind trench, and the overfilled conductive layer are etched to form the first conductive via and the second conductive via.

[0029] Optionally, the TSV chip is an active chip having one or more conductive TSVs, and the conductive TSVs are electrically connected to the first micro bumps.

[0030] Optionally, the insulating layer is formed between the bottom of the TSV chip and the blind trench.

[0031] To achieve the above object, the third aspect of the present invention provides a semiconductor packaging structure, which includes:

[0032] A glass substrate, wherein the glass substrate is the above-mentioned glass substrate structure or a glass substrate structure manufactured by the above-mentioned manufacturing method;

[0033] a high-density wiring structure formed on the first surface of the glass core board of the glass substrate and the top surface of the TSV chip, the high-density wiring structure being electrically connected to the second conductive vias and to the conductive TSV of the TSV chip;

[0034] a redistribution structure formed on the second surface of the glass core board, the redistribution structure being electrically connected to the second conductive via and to the first conductive via;

[0035] a first solder resist layer formed on the high-density wiring structure and having a plating column electrically connected to the high-density wiring structure;

[0036] At least two chips, each of which has a second micro-bump formed on the surface of the chip, and the second micro-bump is connected to the electroplating column by thermocompression bonding, so as to flip-chip each chip on the first solder resist layer.

[0037] According to the semiconductor packaging structure of the present invention, the glass substrate is a TSV chip embedded in the glass core board, and the back micro-bumps of the TSV chip are connected to the conductive through-holes on the glass core board by thermocompression bonding, so as to realize the 3D integration of the glass core board and the active components, and provide back power supply while embedding the active components on the glass core board to improve the wiring density; the connection between the TSV chip and the multi-chip is realized through the high-density wiring structure on the glass substrate, and the high-density wiring structure is connected by thermocompression bonding of the electroplated columns and the back micro-bumps of the multi-chips, rather than soldering the chips through ball planting technology; thus, high-precision, high-strength, high-reliability interconnection and high-integration multi-chip packaging can be realized. In addition, compared with the traditional wafer-level fan-out packaging structure, the size of the glass substrate of this packaging structure is larger, the unit cost is lower, and it has obvious economic benefits.

[0038] In addition, the semiconductor packaging structure proposed in the present invention may also have the following additional technical features:

[0039] Optionally, it also includes: a second solder resist layer formed on the redistribution structure and having solder balls electrically connected to the redistribution structure.

[0040] Optionally, the first solder resist layer has at least two electroplated columns, wherein at least one electroplated column is electrically connected to the conductive TSV of the TSV chip through the high-density wiring structure, and at least one electroplated column is electrically connected to the second conductive through-hole through the high-density wiring structure.

[0041] Optionally, the line width / line spacing of the lines of the high-density wiring structure is 2 / 2 μm to 5 / 5 μm; the line width / line spacing of the lines of the heavy wiring structure is 8 / 8 μm to 10 / 10 μm.

[0042] To achieve the above object, a fourth aspect of the present invention provides a method for manufacturing a semiconductor package structure, which comprises the following steps:

[0043] Providing a glass substrate, wherein the glass substrate is the above-mentioned glass substrate structure or a glass substrate structure manufactured by the above-mentioned manufacturing method;

[0044] Fabricating a high-density wiring structure on the first surface of the glass core board of the glass substrate and the top surface of the TSV chip, wherein the high-density wiring structure is electrically connected to the second conductive via and to the conductive TSV of the TSV chip;

[0045] Making a redistribution structure on the second surface of the glass core board, wherein the redistribution structure is electrically connected to the second conductive through hole and to the first conductive through hole;

[0046] A first solder resist layer is formed on the high-density wiring structure, and windows are opened and electroplated on the first solder resist layer to form electroplated columns, wherein the electroplated columns are electrically connected to the high-density wiring structure; a second solder resist layer is formed on the rewiring structure, and pads are formed on the second solder resist layer, wherein the pads are electrically connected to the rewiring structure;

[0047] Providing at least two chips, and connecting the second micro-bumps of each chip to the electroplating pillars by thermocompression bonding, so as to flip-chip each chip onto the first solder resist layer;

[0048] A solder ball electrically connected to the pad is formed on the second solder resist layer.

[0049] Optionally, the step of manufacturing a high-density wiring structure on the first surface of the glass core board and the top surface of the TSV chip includes:

[0050] forming a photosensitive dielectric layer on the first surface of the glass core board and the top surface of the TSV chip;

[0051] Exposing and developing the photosensitive dielectric layer to produce a first layer wiring pattern;

[0052] Manufacturing a first wiring layer on the first wiring pattern, wherein the first wiring layer includes a metal line and a metal pad electrically connected to the second conductive via and the conductive TSV;

[0053] The first wiring layer is repeatedly covered with a photosensitive dielectric layer, and wiring patterns and wiring layers are fabricated to build up layers to form the high-density wiring structure.

[0054] Optionally, the redistribution structure is fabricated on the second surface of the glass core board by an additive process or a semi-additive process.

[0055] Optionally, the first solder resist layer has at least two electroplated columns, wherein at least one electroplated column is electrically connected to the conductive TSV of the TSV chip through the high-density wiring structure, and at least one electroplated column is electrically connected to the second conductive through-hole through the high-density wiring structure.

[0056] Furthermore, the surface of the chip has at least two of the second micro-bumps, and the at least two of the second micro-bumps of each chip are connected to the top end surfaces of at least two of the electroplated columns in a one-to-one correspondence by hot pressing bonding, so as to flip-chip each chip on the first solder resist layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a schematic structural diagram of a glass substrate according to an embodiment of the present invention;

[0058] Figure 2 (A) to (G) are cross-sectional schematic diagrams of intermediate structures in various steps of the method for manufacturing a glass substrate structure in an embodiment of the present invention;

[0059] Figure 3 is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention;

[0060] Figure 4 (A) to (E) are cross-sectional schematic diagrams of intermediate structures in various steps of the method for manufacturing a semiconductor package structure in an embodiment of the present invention;

[0061] Figure 5 (A1) to (A 11 ) is a cross-sectional schematic diagram of intermediate structures in various steps of a method for manufacturing a high-density wiring structure in a semiconductor packaging structure according to an embodiment of the present invention;

[0062] Figure 6 (B1) to (B 10 ) is a cross-sectional schematic diagram of intermediate structures in various steps of a method for manufacturing a redistribution structure in a semiconductor packaging structure according to an embodiment of the present invention;

[0063] Figure 7 (C1) to (C6) are cross-sectional schematic diagrams of intermediate structures of various steps of the method for manufacturing a solder resist layer in a semiconductor packaging structure in an embodiment of the present invention;

[0064] Description of labels:

[0065] Glass substrate structure 100;

[0066] Glass core board 110, first surface 110a, second surface 110b;

[0067] Blind slot 120;

[0068] A first conductive via 130, a first TGV hole 131;

[0069] A second conductive via 140, a second TGV hole 141;

[0070] TSV chip 150, first micro bump 151, conductive TSV 152;

[0071] Insulation layer 160;

[0072] High-density wiring structure 200, photosensitive dielectric layer 210, first wiring layer 220, metal line 221, metal pad 222, second wiring layer 230;

[0073] Rewiring structure 300;

[0074] First solder resist layer 400, electroplating column 410, electroplating column 410a, electroplating column 410b, electroplating column 410c;

[0075] Chip 500, second micro bump 510;

[0076] A second solder resist layer 600 , a solder ball 610 , and a solder pad 620 . DETAILED DESCRIPTION

[0077] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0078] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0079] Example 1

[0080] Please refer to Figure 1, the embodiment described in the present application provides a glass substrate structure, which can be used as an IC packaging substrate. The glass substrate structure 100 includes a glass core board 110, the glass core board 110 has a first surface 110a and a second surface 110b opposite to each other; a blind groove 120, formed in the glass core board 110 from the first surface 110a; one or more first conductive vias 130, penetrating the glass core board 110 and exposed to the blind groove 120 and the second surface 110b; one or more second conductive vias 140, penetrating the glass core board 110 and exposed to the first surface 110a and the second surface 110b; a TSV chip 150, embedded in the blind groove 120, the TSV chip 150 has one or more first micro bumps 151 formed on the surface of the TSV chip 150, and the first micro bumps 151 are connected to the first conductive vias 130 by thermocompression bonding; an insulating layer 160, formed between the TSV chip 150 and the blind groove 120.

[0081] As an example, the TSV chip 150 is an active chip having one or more conductive TSVs 152, and the conductive TSVs 152 are electrically connected to the first micro bumps 151. It can be understood that the TSV chip 150 is an active chip with TSVs, such as a silicon TSV chip, which is manufactured using existing technology and will not be described in detail here. Figure 1 One or more first micro bumps 151 are formed on the bottom of the TSV chip 150. The first micro bumps 151 are connected to the front side of the TSV chip 150 (i.e. Figure 1 The top of the TSV chip 150 is connected and powered by the conductive TSV 152. More specifically, in this embodiment, the number of the first micro bumps 151 of the TSV chip 150 is consistent with the number of the conductive TSV 152 and corresponds one to one. The first micro bumps 151 can be copper pillars or solder balls.

[0082] As an example, the insulating layer 160 is formed between the bottom of the TSV chip 150 and the blind groove 120. That is to say, except for the position where the first micro-bump 151 is connected to the first conductive via 130 by thermocompression bonding, the bottom of the TSV chip 150 and the bottom surface of the blind groove 120 are separated by the insulating layer 160. Among them, the insulating material of the insulating layer 160 can be a non-conductive film, a non-conductive slurry, etc. The insulating layer 160 can be pre-coated and pasted on the bottom of the TSV chip 150, and then the TSV chip 150 is placed in the blind groove 120, and then the first micro-bump 151 is bonded to the first conductive via 130 by thermocompression, and then the insulating layer 160 is cured, and finally the TSV chip 150 is embedded in the glass core board 110. Of course, in other examples, the insulating layer 160 can also be filled into the blind groove 120 by filling at a later stage.

[0083] Therefore, according to the glass substrate structure 100 provided in the embodiment of the present invention, a glass core board 110 is used as a support, and a TSV chip 150 is embedded on the glass core board 110. The micro-bumps on the back side of the TSV chip 150 are connected to the conductive through holes on the glass core board 110 by thermocompression bonding. In this way, the glass core board 110 and active components can be systematically integrated in 3D. Active components are embedded in the glass core board 110 to improve the wiring density while providing back power supply. High-precision, high-strength, high-reliability interconnection and high-integration multi-chip packaging can be achieved in the subsequent packaging structure.

[0084] On the other hand, please refer to Figure 2 (A) to (G) show schematic cross-sectional views of intermediate structures in various steps of the method for manufacturing the above-mentioned glass substrate structure.

[0085] The manufacturing method of the glass substrate structure comprises the following steps:

[0086] like Figure 2 As shown in (A), a glass substrate is prepared as a core board material to provide a glass core board 110 after surface polishing and cleaning. The glass core board 110 mainly plays a supporting and connecting role, and materials such as quartz and boric acid glass can be selected. The type of glass can take into account the mechanical parameters of the chip and the PCB substrate, such as selecting glass that matches their CTE; the glass core board 110 has a first surface 110a and a second surface 110b relative to each other.

[0087] As an example, the glass core board 110 has a thickness of 200 μm to 1 mm.

[0088] Then, if Figure 2 As shown in (B), on the glass core board 110, a blind groove 120 is formed by opening the glass core board 110 from its first surface 110a. The blind groove 120 can be made by plasma etching, laser ablation, laser induced etching, focused discharge, or by photolithography, dry etching, degumming and other process steps. The opening of the blind groove 120 is facing upward. The size of the blind groove is determined according to the size of the embedded active chip, and the size of the blind groove can be 3.0mm×3.0mm×0.1mm~8.0mm×8.0mm×1.0mm.

[0089] Then, if Figure 2As shown in (C), on the glass core board 110, a through glass via (TGV) is made by opening the glass core board 110 from the first surface 110a and the bottom of the blind groove 120 to form one or more first TGV holes 131 and second TGV holes 141. The TGV can be made by plasma etching, laser ablation, laser induced etching, focused discharge and other methods. The TGV completely penetrates the glass core board 110; the TGV aperture is determined according to the product design and the board thickness, and the first TGV hole 131 and the second TGV hole 141 may not be of different sizes, for example Figure 2 As shown in (C), the aperture of the first TGV hole 131 is smaller than the aperture of the second TGV hole 141. More specifically, the aperture of the first TGV hole 131 is 20 μm to 60 μm, and the aperture of the second TGV hole 141 is 50 μm to 100 μm.

[0090] Then, if Figure 2 As shown in (D) to (F), conductive materials are filled in the first TGV hole 131 and the second TGV hole 141 to form the first conductive via 130 and the second conductive via 140. That is, the glass through hole is metallized using metal plating or deposition to form a plurality of conductive vias.

[0091] As an example, the step of filling the first TGV hole 131 and the second TGV hole 141 with a conductive material includes: Figure 2 As shown in (D), a seed layer is formed on the first surface 110a, the second surface 110b, the inner surface of the blind groove 120, the inner wall of the first TGV hole 131 and the inner wall of the second TGV hole 141; that is, a seed layer is formed on the blind groove 120, the inside of the through glass hole and the surface of the glass core board 110. The seed layer can be formed by physical vapor deposition (PVD Physical Vapor Deposition), chemical copper deposition (PTH) and the like. In this embodiment, the seed layer can be a copper layer with a thickness. Then, as Figure 2 As shown in (E), a conductive layer is filled in the first TGV hole 131 and the second TGV hole 141. Specifically, the conductive layer in the first TGV hole 131 and the second TGV hole 141 can be filled by electroplating filling, metal conductive glue filling, etc. The conductive layer can be a copper layer with a certain thickness. In this embodiment, when electroplating is used to fill the hole, a copper layer is formed that fills the TGV hole and is higher than the end surface of the TGV hole. In other examples, the seed layer and the conductive layer can also be other suitable conductive materials, such as tin, nickel, etc. Then, as Figure 2As shown in (F), the first surface 110a, the second surface 110b, the seed layer in the blind groove 120 and the overfilled conductive layer are etched to form the first conductive via 130 and the second conductive via 140. Specifically, the seed copper layer and the over-plated electroplated copper layer can be etched away by using methods such as excimer laser etching and plasma etching.

[0092] Finally, if Figure 2 As shown in (G), a TSV chip 150 is provided, and the first micro bump 151 of the TSV chip 150 is connected to the first conductive via 130 by thermocompression bonding to embed the TSV chip 150 in the blind groove 120. An insulating material is pasted on the bottom of the TSV chip 150. After the TSV chip 150 is buried in the blind groove 120, the insulating material is cured to form an insulating layer 160 between the bottom of the TSV chip 150 and the blind groove 120. The TCB bonding technology has an alignment and pressing temperature of 200°C to 500°C, a pressing pressure of 10MPa to 500MPa, a curing temperature of the insulating layer 160 of 60°C to 120°C, and a curing pressure of 100kPa to 500kPa.

[0093] This can provide Figure 1 The glass substrate with the TGV active chip embedded therein is shown. The glass substrate structure 100 can integrate the glass substrate and active components into a system, overcome the warping problem in the large-size packaging of AI chips, and realize the appearance packaging of ultra-large size and high assembly yield.

[0094] Example 2

[0095] Please refer to Figure 3 The embodiment of the present invention also proposes a semiconductor packaging structure made by using the glass substrate structure 100 of the above-mentioned embodiment 1 as a packaging substrate. The semiconductor packaging structure includes a glass substrate structure 100; a high-density wiring structure 200 formed on the first surface 110a of the glass core board 110 and the top surface of the TSV chip 150 (the front surface of the TSV chip 150), and the high-density wiring structure 200 is electrically connected to the second conductive via 140 and connected to the conductive TSV of the TSV chip 150. 152 is electrically connected; a redistribution structure 300 is formed on the second surface 110b of the glass core board 110, the redistribution structure 300 is electrically connected to the second conductive through hole 140, and is electrically connected to the first conductive through hole 130; a first solder resist layer 400 is formed on the high-density wiring structure 200, and has an electroplated column 410 electrically connected to the high-density wiring structure 300; at least two chips 500, each chip 500 has a second micro-bump 510 formed on the surface of the chip 500, and the second micro-bump 510 is connected to the electroplated column 410 by hot pressing bonding, so as to flip-chip each chip 500 on the first solder resist layer 400.

[0096] Therefore, according to the semiconductor packaging structure of the present invention, the glass substrate is embedded with TSV chip 150 on the glass core board 110, and the back micro-bumps of TSV chip 150 are connected with the conductive through-holes on the glass core board 110 by thermocompression bonding, so as to realize the 3D integration of the glass core board 110 and the active components, and embed the active components on the glass core board 110 to improve the wiring density while providing back power supply; the connection between the TSV chip 150 and the multi-chip 500 is realized by the high-density wiring structure 200 on the glass substrate, and the high-density wiring structure 200 is connected with the back micro-bumps of the multi-chip 500 by thermocompression bonding through the electroplating column 410, rather than soldering the chips by ball planting technology; thus, high-precision, high-strength, high-reliability interconnection and high-integration multi-chip packaging can be realized. In addition, compared with the traditional wafer-level fan-out packaging structure, the size of the glass substrate of this packaging structure is larger, the unit cost is lower, and it has obvious economic benefits.

[0097] As an example, Figure 3 As shown, it also includes a second solder resist layer 600 formed on the redistribution structure 300 and having solder balls 610 electrically connected to the redistribution structure 300. The solder balls 610 are used to connect to the PCB board so that the semiconductor package structure is disposed on the PCB board.

[0098] As an example, the first solder resist layer 400 has at least two electroplated pillars 410, wherein at least one electroplated pillar 410a is electrically connected to the conductive TSV 152 of the TSV chip 150 through the high-density wiring structure 200, and at least one electroplated pillar 410b is electrically connected to the second conductive through-hole 140 through the high-density wiring structure 200. It can be understood that the electroplated pillar 410 is connected to the second micro-bump 510 of the chip 500 by thermocompression bonding, part of the electroplated pillar 410a is interconnected with the TSV chip 150, so that the TSV chip 150 is interconnected with the multi-chip 500, and part of the electroplated pillar 410b is interconnected with the second conductive through-hole 140, which can realize power supply to the chip 500 and connection of the chip 500 with the PCB board.

[0099] More specifically, if Figure 3 As shown, the first solder resist layer 400 has three electroplated columns 410, one electroplated column 410a is electrically connected to the conductive TSV 152 of the TSV chip 150 through the high-density wiring structure 200, one electroplated column 410b is electrically connected to the second conductive through-hole 140 through the high-density wiring structure 200, and another electroplated column 410c is electrically connected to the line of the high-density wiring structure 200.

[0100] In this way, chips 500 with different functions can be flipped on the first solder resist layer 400 to achieve multi-chip 500 integration. The second micro-bumps 510 of the chip 500 can be copper pillars or solder balls. The number of the second micro-bumps 510 is consistent with the number of the electroplating pillars 410 and corresponds one to one. In this embodiment, the height of the second micro-bumps is 40 μm to 100 μm, and the height of the electroplating pillars 410 is 2 μm to 20 μm.

[0101] As an example, the line width / line spacing of the high-density wiring structure 200 is 2 / 2μm to 5 / 5μm, and the line width / line spacing of the redistribution wiring structure 300 is 8 / 8μm to 10 / 10μm. In this way, the high-density wiring structure 200 can achieve the effect of local high-density interconnection.

[0102] On the other hand, please refer to Figure 4 (A) to (E) show schematic cross-sectional views of intermediate structures in various steps of the method for manufacturing the semiconductor package structure.

[0103] The manufacturing method of the semiconductor packaging structure comprises the following steps:

[0104] First, a glass substrate is provided. The glass substrate is the glass substrate structure 100 described above or the glass substrate structure 100 manufactured by the above manufacturing method.

[0105] Then, if Figure 4 As shown in (A), a high-density wiring structure 200 is manufactured on the first surface 110a of the glass core board 110 of the glass substrate and the top surface of the TSV chip 150. The high-density wiring structure 200 is electrically connected to the second conductive through hole 140 and to the conductive TSV 152 of the TSV chip 150. The high-density wiring structure 200 is used for wiring electronic signals. The high-density wiring structure 200 includes one or more dielectric layers and one or more wiring layers. The dielectric layer can be an organic dielectric material or an inorganic dielectric material. When an organic dielectric material is used, the process difficulty of its manufacture is small. When an inorganic dielectric material is used, the RDL line width can be made thinner. The organic dielectric material can be a photosensitive material such as a photoresist and a dry film; non-photosensitive thin film materials such as ABF can also be used. The wiring layer can be copper or other suitable conductive materials.

[0106] Specifically, if Figure 5 (A1) to (A 11 ), the steps of manufacturing the high-density wiring structure 200 on the first surface 110a of the glass core board 110 and the top surface of the TSV chip 150 include:

[0107] like Figure 5As shown in (A1), the glass substrate structure 100 of the above-mentioned embodiment 1 or the glass substrate structure 100 manufactured by the manufacturing method of the above-mentioned embodiment 1 is provided.

[0108] Then, if Figure 5 As shown in (A2), a photosensitive dielectric layer 210 is formed on the first surface 110a of the glass core board 110 and the top surface of the TSV chip 150. The photosensitive dielectric layer 210 can be photosensitive polyimide, which is formed on the first surface 110a of the glass core board 110 and the top surface of the TSV chip 150 by coating / vacuum lamination.

[0109] Afterwards, if Figure 5 As shown in (A3) to (A4), the photosensitive dielectric layer 210 is exposed and developed to produce a first-layer wiring pattern, and the first-layer wiring pattern includes a pad cavity and a line cavity penetrating the photosensitive dielectric layer 210, the pad cavity exposes the top of the second conductive via 140 and the conductive TSV 152 of the TSV chip 150, and the line cavity exposes the first surface 110a. The exposure and development are performed using existing processes in the art.

[0110] Then, if Figure 5 (A5) to (A 11 ), a first wiring layer 220 is formed on the first wiring pattern, and the first wiring layer 220 includes a metal line 221 and a metal pad 222 electrically connected to the second conductive via 140 and the conductive TSV 152. The first wiring layer 220 can be formed by electroplating, etching, and other processes at the pad cavity and line cavity of the photosensitive dielectric layer 210. Specifically, as Figure 5 As shown in (A5), a seed layer is formed on the top surface of the photosensitive dielectric layer 210 by sputtering / deposition. Figure 5 (A6) to (A 11 ), photoresist coating / filming is performed on the seed layer → photolithography (exposure) → photolithography (development) → electroplating (RDL metal pad / line) → photoresist removal → etching (removing the seed layer outside the RDL). Among them, exposure, development, electroplating, photoresist removal, and etching are performed using existing processes in the art.

[0111] Then, if Figure 4 As shown in (A), a second wiring layer 230 can be added on the first wiring layer 220 to form a high-density wiring structure 200 with two wiring layers as shown in the figure. The specific number of wiring layers of the high-density wiring structure 200 can be designed according to actual application needs and is not limited to the two layers shown in the figure. The way of adding layers, for example, the second wiring layer 230 in the figure is formed by repeating the above Figure 5 (A2) to (A 11) is used in the process involved to produce the added layer circuit.

[0112] In this way, a RDL high-definition wiring layer (ie, a high-density wiring structure 200 ) can be manufactured on the top surface of the glass substrate.

[0113] Then, based on the above, a glass substrate of a high-density wiring structure 200 is manufactured. Figure 4 As shown in FIG. 5B , a redistribution structure 300 is fabricated on the second surface 110 b of the glass core board 110 . The redistribution structure 300 is electrically connected to the second conductive via 140 and to the first conductive via 130 .

[0114] As an example, the redistribution structure 300 may be fabricated by using an additive method or a semi-additive method.

[0115] Specifically, if Figure 6 (B1) to (B 10 ) and 4 (B), on the second surface 110b of the glass core board 110, the first redistribution layer of the redistribution structure 300 is manufactured on the bottom surface of the glass substrate (the second surface 110b of the glass core board 110) by attaching an ABF film → laser drilling → chemical Desmear removal of glue residues + copper PTH → attaching a dry film → exposure → development → VCP → film removal → flash etching. Among them, the above-mentioned laser drilling, chemical Desmear removal of glue residues, copper PTH, attaching a dry film, exposure, development, VCP, film removal, flash etching, etc. are carried out using existing processes in the field.

[0116] Then, if Figure 4 As shown in (B), a second redistribution layer can be added on the first redistribution layer of the redistribution structure 300 to form a redistribution structure 300 having two redistribution layers as shown in the figure. The specific number of redistribution layers of the redistribution structure 300 can be designed according to actual application needs and is not limited to the two layers shown in the figure. The way of adding layers, for example, the second redistribution layer in the figure is to repeat the above Figure 6 (B2) to (B 10 ) is used in the process involved to produce the added layer circuit.

[0117] Next, based on the above, a glass substrate with a high-density wiring structure 200 and a redistribution wiring structure 300 is fabricated. Figure 4As shown in (C), a first solder resist layer 400 is made on the high-density wiring structure 200, and a window is opened on the first solder resist layer 400, and electroplating is performed to make a plated column 410, and the plated column 410 is electrically connected to the high-density wiring structure 200; a second solder resist layer 600 is made on the rewiring structure 300, and a pad 620 is made on the second solder resist layer 600, and the pad 620 is electrically connected to the rewiring structure 300. Among them, the first solder resist layer 400 and the second solder resist layer 600 can be made at the same time, or they can be made on one side in sequence, and the manufacturing methods of the first solder resist layer 400 and the second solder resist layer 600 are different; the first solder resist layer 400 is made by solder resist exposure and development, solder resist window opening (UV drilling small holes), electroplating copper columns, etc., and the second solder resist layer 600 is made by solder resist exposure and development, surface treatment, etc., and then the bottom ball is planted.

[0118] For example Figure 7 As shown in (C1) to (C6) and 4 (C), the first solder resist layer 400 and the electroplated pillar 410 are manufactured on the high-density wiring structure 200 through the steps of green oil coating → green oil (whole board exposure) → green oil (development) → solder resist window opening (UV drilling small hole) → solder resist copper → film pasting → exposure and development → electroplating copper pillar / nickel / tin → film removal → flash etching → reflow soldering Reflow. The second solder resist layer 600 and the pad 620 are manufactured on the rewiring structure 300 through the steps of green oil coating → green oil (exposure) → green oil (development) → surface treatment (ENEPIG / OSP / ENIG) and the like. Among them, the above-mentioned green oil coating, green oil (exposure), green oil (development), surface treatment (ENEPIG / OSP / ENIG), solder mask window opening, electroplating copper pillar / nickel / tin, solder mask copper, film pasting, film stripping, flash etching, Reflow, etc. are carried out using existing processes in the field.

[0119] Subsequently, based on the above Figure 4 (C) A glass substrate having a first solder resist layer 400 and a second solder resist layer 600 is fabricated. Figure 4 As shown in (D), at least two chips 500 are provided, and the second micro-bumps 510 of each chip 500 are connected to the electroplated pillars 610 by thermocompression bonding, so as to flip each chip 500 on the first solder resist layer 400. The second micro-bumps 510 of the chip 500 are pre-made on the front side of the chip 500 (i.e., the bottom of the chip 500 in the figure), and then the second micro-bumps 510 of the chip 500 are connected to the electroplated pillars 410 on the first solder resist layer 400 by thermocompression bonding. Among them, the chip 500 can be an active chip. In this way, the high-precision, high-strength, and high-reliability interconnection between the front micro-bumps (front side facing down) of the active chip 500 and the electroplated copper pillars can be achieved by thermocompression bonding. Among them, the TCB bonding technology has an alignment pressing temperature of 200°C to 500°C and a pressing pressure of 10MPa to 500MPa.

[0120] Finally, based on the above Figure 4 (D) The glass substrate of the flip-chip multi-chip 500 is manufactured. Figure 4 As shown in (E), solder balls 610 (solder balls) are implanted on the pads 620 of the second solder resist layer 600 by a bottom ball implantation process such as solder paste printing or ball implantation. Figure 3 The semiconductor package structure shown.

[0121] In summary, the semiconductor packaging structure does not need to produce a circuit layer in a blind groove embedded in a glass substrate, but directly connects the back micro-bumps of the TGV active chip to the electroplated copper in the blind groove through hot-press bonding, thereby realizing high-precision, high-strength, and high-reliability interconnection between the back micro-bumps of the active chip and the conductive through-holes; the connection between the TGV active chip and multiple chips is realized through the RDL high-precision circuit layer on the glass substrate; after the glass substrate is processed with a solder mask layer and metal surface treatment is performed to form a solder mask window, the RDL high-precision circuit layer connects multiple chips through electroplated copper pillars, rather than connecting chips through solder balls through ball planting technology; in this way, high-precision, high-strength, and high-reliability interconnection between the front micro-bumps of multiple chips and the electroplated copper pillars is realized through hot-press bonding.

[0122] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0123] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0124] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0125] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0126] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily being directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0127] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A glass substrate structure, characterized in that: include: a glass core board having opposing first and second surfaces; a blind groove formed in the glass core board from the first surface; One or more first conductive through holes, penetrating the glass core board and exposed at the blind groove and the second surface; One or more second conductive vias extending through the glass core board and exposed at the first surface and the second surface; A TSV chip is embedded in the blind groove, the TSV chip has one or more first micro bumps formed on the surface of the TSV chip, and the first micro bumps are connected to the first conductive vias by thermocompression bonding; An insulating layer is formed between the TSV chip and the blind trench.

2. The glass substrate structure according to claim 1, wherein: The TSV chip is an active chip having one or more conductive TSVs, and the conductive TSVs are electrically connected to the first micro-bumps.

3. The glass substrate structure according to claim 1, wherein: The insulating layer is formed between the bottom of the TSV chip and the blind groove.

4. A method for manufacturing a glass substrate structure, characterized in that: The following steps are involved: providing a glass core panel having opposing first and second surfaces; Opening a hole in the glass core board from the first surface to form a blind groove; Through-glass vias (TGVs) are formed by drilling holes in the glass core plate from the first surface and from the bottom of the blind groove to form one or more first TGV holes and a second TGV hole; Filling the first TGV hole and the second TGV hole with a conductive material to form a first conductive via and a second conductive via; Providing a TSV chip, and connecting a first micro-bump of the TSV chip to the first conductive via by thermocompression bonding, so as to embed the TSV chip in the blind groove; An insulating layer is formed between the TSV chip and the blind trench.

5. The method for manufacturing a glass substrate structure according to claim 4, wherein: The step of filling the first TGV hole and the second TGV hole with a conductive material comprises: forming a seed layer on the first surface, the second surface, the inner surface of the blind groove, the inner wall of the first TGV hole, and the inner wall of the second TGV hole; Filling a conductive layer in the first TGV hole and the second TGV hole; The first surface, the second surface, the seed layer in the blind trench, and the overfilled conductive layer are etched to form the first conductive via and the second conductive via.

6. The method for manufacturing a glass substrate structure according to claim 4, wherein: The TSV chip is an active chip having one or more conductive TSVs, and the conductive TSVs are electrically connected to the first micro-bumps.

7. The method for manufacturing a glass substrate structure according to claim 4, wherein: The insulating layer is formed between the bottom of the TSV chip and the blind groove.

8. A semiconductor packaging structure, characterized in that: include: A glass substrate, wherein the glass substrate is a glass substrate structure according to any one of claims 1 to 3 or a glass substrate structure manufactured by the manufacturing method according to any one of claims 4 to 7; a high-density wiring structure formed on the first surface of the glass core board of the glass substrate and the top surface of the TSV chip, the high-density wiring structure being electrically connected to the second conductive vias and to the conductive TSV of the TSV chip; a redistribution structure formed on the second surface of the glass core board, the redistribution structure being electrically connected to the second conductive via and to the first conductive via; a first solder resist layer formed on the high-density wiring structure and having a plating column electrically connected to the high-density wiring structure; At least two chips, each of which has a second micro-bump formed on the surface of the chip, and the second micro-bump is connected to the electroplating column by thermocompression bonding, so as to flip-chip each chip on the first solder resist layer.

9. The semiconductor package structure according to claim 8, wherein: Also includes: The second solder resist layer is formed on the redistribution structure and has solder balls electrically connected to the redistribution structure.

10. The semiconductor package structure according to claim 8, wherein: The first solder resist layer has at least two electroplated columns, wherein at least one electroplated column is electrically connected to the conductive TSV of the TSV chip through the high-density wiring structure, and at least one electroplated column is electrically connected to the second conductive through-hole through the high-density wiring structure.

11. The semiconductor package structure according to claim 8, wherein: The line width / line spacing of the lines of the high-density wiring structure is 2 / 2 μm to 5 / 5 μm; the line width / line spacing of the lines of the heavy wiring structure is 8 / 8 μm to 10 / 10 μm.

12. A method for manufacturing a semiconductor packaging structure, characterized in that: The following steps are involved: Providing a glass substrate, wherein the glass substrate is the glass substrate structure according to any one of claims 1 to 3 or the glass substrate structure manufactured by the manufacturing method according to any one of claims 4 to 7; Fabricating a high-density wiring structure on the first surface of the glass core board of the glass substrate and the top surface of the TSV chip, wherein the high-density wiring structure is electrically connected to the second conductive via and to the conductive TSV of the TSV chip; Making a redistribution structure on the second surface of the glass core board, wherein the redistribution structure is electrically connected to the second conductive through hole and to the first conductive through hole; Making a first solder resist layer on the high-density wiring structure, and opening windows and electroplating on the first solder resist layer to make electroplated columns, wherein the electroplated columns are electrically connected to the high-density wiring structure; Making a second solder resist layer on the rewiring structure, and making a pad on the second solder resist layer, wherein the pad is electrically connected to the rewiring structure; Providing at least two chips, and connecting the second micro-bumps of each chip to the electroplating pillars by thermocompression bonding, so as to flip-chip each chip onto the first solder resist layer; A solder ball electrically connected to the pad is formed on the second solder resist layer.

13. The method for manufacturing a semiconductor package structure according to claim 12, wherein: The steps of fabricating a high-density wiring structure on the first surface of the glass core board and the top surface of the TSV chip include: forming a photosensitive dielectric layer on the first surface of the glass core board and the top surface of the TSV chip; Exposing and developing the photosensitive dielectric layer to produce a first layer wiring pattern; Manufacturing a first wiring layer on the first wiring pattern, wherein the first wiring layer includes a metal line and a metal pad electrically connected to the second conductive via and the conductive TSV; The first wiring layer is repeatedly covered with a photosensitive dielectric layer, and wiring patterns and wiring layers are fabricated to build up layers to form the high-density wiring structure.

14. The method for manufacturing a semiconductor package structure according to claim 12, wherein: The redistribution structure is manufactured on the second surface of the glass core board by an additive method or a semi-additive method.

15. The method for manufacturing a semiconductor package structure according to claim 12, wherein: The first solder resist layer has at least two electroplated columns, at least one of which is electrically connected to the conductive TSV of the TSV chip through the high-density wiring structure, and at least one of which is electrically connected to the second conductive through-hole through the high-density wiring structure.

16. The method for manufacturing a semiconductor package structure according to claim 15, wherein: The surface of the chip has at least two of the second micro-bumps, and the at least two of the second micro-bumps of each chip are connected to the top end surfaces of at least two of the electroplated columns in a one-to-one correspondence by thermal compression bonding, so as to flip-chip each chip on the first solder resist layer.

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