Semiconductor power module and method for manufacturing semiconductor power module

Abstract

The invention provides a semiconductor power module and a preparation method of the semiconductor power module, and relates to the technical field of semiconductors. The semiconductor power module comprises a bearing substrate, a double-sided metal substrate, a chip, a conductive connecting layer and a connecting wire, the double-sided metal substrate is arranged on the bearing substrate, and the double-sided metal substrate comprises a bearing insulating layer, a first metal layer, a second metal layer and a third metal layer; the chip is arranged on the second metal layer; the conductive connecting layer is sintered and fixed on the surface of one side, deviating from the second metal layer, of the chip and covers an electrode of the chip; the connecting wire is bonded between the conductive connecting layer and the third metal layer. Compared with the prior art, the method has the advantages that the conductive connecting layer fixed through sintering does not need to be additionally welded with copper foil during actual lead bonding, the copper foil preparation and welding steps in the conventional technology are omitted, the lead bonding process can be simplified, the process difficulty is low, and the process cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor power module and a method for preparing the semiconductor power module. Background Art

[0002] Power modules are widely used in modern power electronic devices, especially in electric vehicles, power transmission, renewable energy, and industrial automation. These modules are responsible for efficiently converting, controlling, and distributing electrical energy to support the normal operation of various devices. In these application scenarios, power modules usually need to handle currents with high power density and work for long periods of time under extreme conditions, which places stringent requirements on their performance. As the power demand of power electronic devices increases, power modules need to be able to withstand higher voltages and currents. This requires the modules to have higher power handling capabilities while maintaining stability and reliability. Secondly, since high-power operation generates a lot of heat, the heat dissipation performance of the power module becomes one of its key performance indicators. Especially in the electric drive system of new energy vehicles, the operating temperature of the power module is basically above 60 degrees Celsius. If the module cannot effectively dissipate heat, it may cause excessive temperature, causing failures or even damage.

[0003] The inventors have found that in related technologies, wire bonding technology is usually used to achieve electrical connection between chips and substrates. During bonding, it is usually necessary to first solder copper foil on the chip and then perform wire bonding. The welding process and precision requirements between the copper foil and the chip pad are high, and the copper foil structure needs to be prepared in advance. The process is more complicated and more difficult, so high-precision equipment and strict process control are required, which undoubtedly increases the cost. Summary of the invention

[0004] The purpose of the present invention includes providing a semiconductor power module and a method for preparing the semiconductor power module, which can simplify the wire bonding process, do not require additional copper foil welding, have low process difficulty, and reduce process costs.

[0005] The embodiments of the present invention can be implemented as follows: In a first aspect, the present invention provides a semiconductor power module, comprising: A carrier substrate; A double-sided metal substrate, the double-sided metal substrate comprising a bearing insulating layer, a first metal layer, a second metal layer and a third metal layer, the first metal layer being arranged on one side surface of the bearing insulating layer, the second metal layer and the third metal layer being arranged at intervals on the other side surface of the bearing insulating layer, and the first metal layer being arranged on the bearing substrate; at least one chip, wherein the chip is disposed on the second metal layer; A conductive connection layer, which is sintered and fixed on a surface of the chip that is away from the second metal layer and covers the electrodes of the chip; A connecting wire is bonded between the conductive connection layer and the third metal layer.

[0006] In an optional embodiment, the conductive connection layer is a uniform layer of equal thickness, and the thickness of the conductive connection layer is between 0.1 mm and 0.2 mm.

[0007] In an optional embodiment, the conductive connection layer is a sintered copper layer, and the first metal layer, the second metal layer and the third metal layer are all copper layers.

[0008] In an optional embodiment, a first sintered copper layer is disposed between the first metal layer and the carrier substrate, and the first sintered copper layer is used to fix the first metal layer and the carrier substrate together through a sintering process.

[0009] In an optional embodiment, a second sintered copper layer is further provided between the chip and the second metal layer, and the second sintered copper layer is used to fix the chip and the second metal layer through a sintering process, and the chip and the second metal layer are electrically connected through the second sintered copper layer.

[0010] In an optional embodiment, the thickness of the first sintered copper layer and the second sintered copper layer is between 0.12 mm and 0.15 mm.

[0011] In an optional embodiment, the thickness of the first metal layer and the second metal layer is between 0.2 mm and 0.8 mm, and the thickness of the load-bearing insulating layer is between 0.2 mm and 0.6 mm.

[0012] In an optional embodiment, a plurality of heat dissipation ribs are further provided on a side of the carrier substrate away from the chip.

[0013] In a second aspect, the present invention provides a method for preparing a semiconductor power module, which is used to prepare a semiconductor power module as described in any one of the above embodiments, and the preparation method comprises: Providing a double-sided metal substrate, wherein the double-sided metal substrate comprises a load-bearing insulating layer, a first metal layer located on one side of the load-bearing insulating layer, and a second metal layer and a third metal layer located on the other side of the load-bearing insulating layer and spaced from each other; attaching a chip to the second metal layer; Sintering a conductive connection layer on a surface of the chip facing away from the second metal layer; Sintering and fixing the first metal layer on the supporting substrate; A connecting wire is bonded between the conductive connecting layer and the third metal layer.

[0014] In an optional embodiment, the step of sintering a conductive connection layer on a surface of the chip facing away from the second metal layer comprises: Dispensing glue on a surface of the chip on a side away from the second metal layer to form nano copper paste dots; The nano copper paste dots are flattened and sintered to form a conductive connection layer.

[0015] In an optional embodiment, the step of flattening the nano copper paste dots and sintering to form a conductive connection layer comprises: Flattening the nano copper paste dots to form a nano copper paste layer; Both sides of the nano copper paste layer are heated simultaneously and sintered to form a conductive connection layer with uniform thickness.

[0016] The semiconductor power module and the method for preparing the semiconductor power module provided by the embodiments of the present invention have the following beneficial effects: The semiconductor power module and its preparation method provided by the embodiment of the present invention are as follows: a double-sided metal substrate is arranged on a carrier substrate, wherein the first metal layer of the double-sided metal substrate is arranged on the carrier substrate downward, the second metal layer and the third metal layer are arranged upward, and the chip is arranged on the second metal layer. After the chip is mounted, a conductive connection layer is sintered on the surface of the chip facing away from the second metal layer to form a conductive connection layer, and the conductive connection layer can cover the electrode of the chip, and then a wire bonding technology is used to bond one end of the connecting wire to the conductive connection layer and the other end to the third metal layer. Compared with the prior art, the embodiment of the present invention uses a conductive connection layer fixed by sintering, and in actual wire bonding, it only needs to bond the copper wire to the conductive connection layer, and there is no need to additionally weld the copper foil and then perform wire bonding, which saves the step of welding the copper foil and the step of preparing the copper foil, simplifies the process steps, reduces the process difficulty, and thus reduces the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of a semiconductor power module provided in this embodiment; Figures 2 to 7 A process flow chart of the method for preparing a semiconductor power module provided in this embodiment.

[0019] Icons: 100-semiconductor power module; 110-carrying substrate; 120-double-sided metal substrate; 121-carrying insulation layer; 122-first metal layer; 123-second metal layer; 124-third metal layer; 130-chip; 131-nano copper paste dots; 132-power circuit area; 133-signal circuit area; 140-conductive connection layer; 150-connecting wire; 160-first sintered copper layer; 170-second sintered copper layer; 180-heat dissipation ribs; 200-pressing head; 210-buffer film; 300-heating base plate. DETAILED DESCRIPTION

[0020] In related technologies, wire bonding process is usually used to realize the connection between chip and substrate. Conventional wire bonding process requires additional welding of copper foil on the chip. The preparation and welding process of copper foil is complicated, and the copper foil precision is required during welding. The process is more complicated and more difficult. Therefore, high-precision bonding equipment and strict process control are required, which undoubtedly pushes up the cost.

[0021] Furthermore, in the prior art, the connection method of the components in the power module is usually achieved by reflow soldering, which is a welding process widely used in electronic assembly, mainly used to solder surface mount components to metal electrodes. This process melts the solder paste by heating, thereby forming a firm electrical connection between the component and the metal electrode. The reflow soldering process has the characteristics of high efficiency, high degree of automation and stable welding quality, and is one of the indispensable technologies in modern electronic manufacturing. However, the existing reflow soldering process has the problem of thermal fatigue. The soldering point is prone to thermal fatigue under high temperature and thermal cycle environment, especially when the power module is frequently switched. Due to the difference in thermal expansion coefficients between solder and chip materials, long-term use will cause stress concentration at the soldering point, resulting in microcracks or desoldering, affecting the reliability of the module. At the same time, the thermal conductivity of the reflow soldering process is low, which increases the risk of module overheating.

[0022] Of course, there are also solutions in the prior art to achieve component connection through silver sintering process. Silver sintering process is an advanced chip interconnection technology, which is particularly suitable for high-power and high-reliability applications such as power electronic modules, LED packaging and radio frequency devices. This process uses nano-scale or micron-scale silver powder to connect silver particles to each other without melting through heating and pressure, forming a solid silver layer with high conductivity and high thermal conductivity, thereby achieving electrical and thermal connection between the chip and the substrate or heat sink. The existing silver sintering cost is relatively high. As a precious metal, the cost of silver is much higher than that of other interconnection materials. The silver powder particles used in the sintering silver process are expensive, and the complex process equipment makes the overall cost high. This may become a limiting factor in cost-sensitive applications, especially in large-scale production, where the accumulation of material and process costs will increase significantly. At the same time, sintering silver has strict requirements on the surface state of the substrate, so the surface metal of the metal ceramic needs to be selectively silver-plated, which further increases the cost.

[0023] In view of the above problems, the present invention provides a semiconductor power module and a method for preparing the same, which can solve the accuracy and cost problems of conventional wire bonding technology, and solve the problems caused by conventional reflow soldering and silver sintering process.

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0027] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, it is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when used. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0028] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0029] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0030] The overall structure, working principle and technical effects of the semiconductor power module provided by the present invention and the detailed steps, implementation principle and technical effects of the preparation method of the corresponding conductor power module are described in detail below through embodiments and in combination with the accompanying drawings.

[0031] See also Figure 1 The embodiment of the present invention provides a semiconductor power module 100, which has a simple structure and can simplify the wire bonding process. It does not require copper foil welding, has low process difficulty, and reduces process costs.

[0032] The semiconductor power module 100 provided in the embodiment of the present invention includes a carrier substrate 110, a double-sided metal substrate 120, at least one chip 130, a conductive connection layer 140 and a connecting wire 150. The carrier substrate 110 is located at the bottom layer of the overall module, and the double-sided metal substrate 120 is arranged on the carrier substrate 110. The double-sided metal substrate 120 includes a carrier insulating layer 121, a first metal layer 122, a second metal layer 123 and a third metal layer 124. The first metal layer 122 is arranged on one side surface of the carrier insulating layer 121, and the second metal layer 123 and the third metal layer 124 are arranged on the other side surface of the carrier insulating layer 121. The first metal layer 122 is arranged on the carrier substrate 110; the chip 130 is arranged on the second metal layer 123; the conductive connection layer 140 is sintered and fixed on the side surface of the chip 130 away from the second metal layer 123, and covers the electrode of the chip 130; the connecting wire 150 is bonded between the conductive connection layer 140 and the third metal layer 124, wherein one end of the connecting wire 150 is bonded to the conductive connection layer 140 and is electrically connected to the chip 130 through the conductive connection layer 140, and the other end of the connecting wire 150 is bonded to the third metal layer 124, so that the third metal layer 124 is electrically connected to the chip 130 through the connecting wire 150.

[0033] It should be noted that, in this embodiment, the second metal layer 123 and the third metal layer 124 are independently spaced apart from each other, the chip 130 may be a single chip or multiple chips, and the chips 130 are all disposed on the second metal layer 123. Of course, the second metal layer 123 here may be a continuous integral metal layer, and the chip 130 is mounted in the middle area of ​​the second metal layer 123. In other preferred embodiments, the second metal layer 123 may also be a plurality of discontinuously distributed metal blocks, and the chip 130 may be distributed on a plurality of metal blocks at the same time, or a plurality of chips 130 may be distributed on a plurality of metal blocks respectively. The distribution between the chip 130 and the second metal layer 123 is not specifically limited here.

[0034] It should also be noted that in this embodiment, the carrier substrate 110 can be a copper substrate, which is located at the bottom layer and mainly plays a role in mechanical support of the entire module structure and can also play a role in heat dissipation. The copper substrate has good thermal conductivity and can conduct the heat generated by the chip 130 to an external radiator or other heat dissipation system. The double-sided metal substrate 120 is a double-sided copper-clad ceramic substrate. The first metal layer 122 of the double-sided metal substrate 120 is arranged downward on the carrier substrate 110, and the second metal layer 123 is upward. The chip 130 is arranged on the second metal layer 123. After the chip 130 is mounted, a conductive connection layer 140 is sintered on the surface of the side of the chip 130 away from the second metal layer 123. The conductive connection layer 140 can cover the electrode of the chip 130, and then the wire bonding technology is used to bond one end of the connecting wire 150 to the conductive connection layer 140, and the other end is bonded to the third metal layer 124. Since the conductive connection layer 140 is fixed by sintering, there is no need to align the pad point of the chip 130 for copper foil welding during actual wire bonding, which also eliminates the copper foil preparation and welding steps, thereby simplifying the wire bonding process. The conductive connection layer 140 is directly sintered to form on the surface of the chip, which reduces the process difficulty and reduces the process cost.

[0035] In some embodiments, the conductive connection layer 140 is a uniform and equal thickness layer, and the thickness of the conductive connection layer 140 is between 0.1 mm and 0.2 mm. Preferably, when sintering to form the conductive connection layer 140, the upper and lower sides can be heated simultaneously to ensure the uniformity of sintering, thereby forming a uniform and equal thickness conductive connection layer 140. Among them, the connecting wire 150 can be a copper bonding wire, and the conductive connection layer 140 is a copper layer, which is used to connect the chip 130 and the copper bonding wire part to ensure a firm connection between the connecting wire 150 and the chip 130. The conductive connection layer 140 has good mechanical strength and electrical conductivity, and can support the electrical connection of the connecting wire 150. The connecting wire 150 can realize the connection between the chip 130 and the external circuit, and is a key component for realizing the electrical connection between the chip 130 and other parts of the circuit board. The copper bonding wire has high conductivity, can carry high current and reduce power loss.

[0036] It is worth noting that in traditional wire bonding technology, due to the difference in thermal expansion coefficients between solder and chip materials, long-term use will cause stress concentration at the welding points, thereby generating microcracks / hidden cracks that affect the welding effect, and even cause desoldering, affecting the reliability of the module. In this embodiment, copper wire and copper conductive connection layer 140 are used. Using the same material can effectively avoid the stress concentration caused by different thermal expansion coefficients, thereby ensuring welding reliability.

[0037] In some embodiments, the conductive connection layer 140 is a sintered copper layer, the first metal layer 122, the second metal layer 123 and the third metal layer 124 are all copper layers, and the load-bearing insulating layer 121 is a ceramic layer. Specifically, the first metal layer 122 is located below the load-bearing insulating layer 121, and provides heat dissipation below the ceramic layer. The ceramic layer is sandwiched between the upper and lower copper layers, and plays the role of insulation and support. The ceramic material has excellent electrical insulation and thermal stability, and can maintain stable performance under high temperature and high pressure environments. The second metal layer 123 and the third metal layer 124 are located on the upper side of the ceramic layer, which can guide the current to the chip 130 and other electrical connection parts, and provide a further heat conduction path. Among them, the thickness of the first metal layer 122, the second metal layer 123 and the third metal layer is between 0.2mm-0.8mm, the thickness of the load-bearing insulating layer 121 is between 0.3mm-0.6mm, the material of the load-bearing insulating layer 121 includes but is not limited to ceramic materials such as aluminum oxide, silicon nitride, and aluminum nitride, and the first metal layer 122, the second metal layer 123 and the third metal layer 124 are preferably copper layers, which have good electrical connection performance and thermal conductivity, and can achieve full copper interconnection.

[0038] In some embodiments, a first sintered copper layer 160 is disposed between the first metal layer 122 and the carrier substrate 110, and the first sintered copper layer 160 is used to fix the first metal layer 122 and the carrier substrate 110 through a sintering process. Specifically, the first sintered copper layer 160 is located above the carrier substrate 110, and serves as a medium connecting the carrier substrate 110 and the first metal layer 122. The first sintered copper layer 160 firmly combines the carrier substrate 110 and the first metal layer 122 through a sintering process, thereby ensuring good mechanical strength and heat dissipation performance.

[0039] Furthermore, the thickness of the first sintered copper layer 160 is between 0.12 mm and 0.15 mm, which can be specifically determined according to the voltage level and heat dissipation requirements of the module. The coverage range of the first sintered copper layer 160 is roughly the same as the extension range of the first metal layer 122, which can ensure that the first metal layer 122 is sintered and fixed on the carrier substrate 110 through the first sintered copper layer 160. Since the first metal layer 122 and the carrier substrate 110 are both copper layers, the bonding effect of the first sintered copper layer 160 is better and the sintering effect is better, forming a fixed copper layer with high electrical conductivity and high thermal conductivity, thereby ensuring the electrical and thermal connection between the first metal layer 122 and the carrier substrate 110.

[0040] It is worth noting that the coverage of the first sintered copper layer 160 here is roughly the same as the extension range of the first metal layer 122, which means that the planar size difference between the first sintered copper layer 160 and the first metal layer 122 is small. Taking into account the process difficulty, without affecting the performance, the planar size of the first sintered copper layer 160 can be larger or smaller, and the specific error requirements can be determined based on the actual size.

[0041] In some embodiments, a second sintered copper layer 170 is further provided between the chip 130 and the second metal layer 123, and the second sintered copper layer 170 is used to fix the chip 130 and the second metal layer 123 through a sintering process, and the chip 130 and the second metal layer 123 are electrically connected through the second sintered copper layer 170. Specifically, the second sintered copper layer 170 is a key layer connecting the second metal layer 123 and the chip 130, and the chip 130 is fixed on the second metal layer 123 through a sintering process, ensuring a low resistance connection between the chip 130 and the second metal layer 123, and being able to withstand thermal cycles.

[0042] Further, the thickness of the second sintered copper layer 170 is between 0.12mm and 0.15mm, which can be specifically determined according to the voltage level and heat dissipation requirements of the module. The second sintered copper layer 170 can be prepared by printing nano copper paste and sintering. When printing nano copper paste, the printing area is 90%-95% of the area of ​​the chip 130, and the printing thickness is 0.12mm-0.15mm. The printing range of the second sintered copper layer 170 can be determined according to the position and size of the chip 130 to be mounted later, which can ensure that the chip 130 is sintered and fixed on the second metal layer 123 through the second sintered copper layer 170, and because the second metal layer 123 and the second sintered copper layer 170 are both copper layers, the sintering effect of the second sintered copper layer 170 is better, forming a fixed copper layer with high electrical conductivity and high thermal conductivity, and ensuring the electrical and thermal connection between the second metal layer 123 and the chip 130. The chip 130 is the core functional component of the entire module and directly affects the performance of the entire circuit. The chip 130 is connected to the second metal layer 123 through the second sintered copper layer 170, and its electrical performance determines the function and efficiency of the final device. The copper wire, the copper sintered layer on the surface, and the surface copper layer of the double-sided copper-clad substrate are all made of copper, and the whole adopts a full copper structure, so there is no risk of thermal mismatch and the reliability is higher.

[0043] In some embodiments, a plurality of heat dissipation ribs 180 are further disposed on one side of the carrier substrate 110 away from the chip 130. Specifically, the heat dissipation ribs 180 may extend in a direction away from the chip 130 and be integrally disposed on the bottom side of the carrier substrate 110, thereby greatly increasing the heat dissipation area and thus improving the heat dissipation effect.

[0044] The embodiment of the present invention further provides a method for preparing a semiconductor power module 100, which is used to prepare the semiconductor power module 100 as described above. The method comprises the following steps: S1: Provide a double-sided metal substrate 120 .

[0045] See also Figure 2 Specifically, first, a double-sided metal substrate 120 is provided, and the double-sided metal substrate 120 can be prepared in advance.

[0046] The double-sided metal substrate 120 is a double-sided copper-clad ceramic substrate, including a load-bearing insulating layer 121, a first metal layer 122, a second metal layer 123 and a third metal layer 124, wherein the first metal layer 122 is arranged on one side surface of the load-bearing insulating layer 121, and the second metal layer 123 and the third metal layer 124 are arranged at intervals on the other side surface of the load-bearing insulating layer 121, wherein the first metal layer 122, the second metal layer 123 and the third metal layer 124 are all copper layers, and the thickness is between 0.2mm-0.8mm, which is determined according to the power level of the power module. The load-bearing insulating layer 121 is a ceramic layer, and the material of the intermediate ceramic layer includes but is not limited to aluminum oxide, silicon nitride, aluminum nitride, etc., and its thickness is between 0.3mm-0.6mm, which is determined according to the voltage level and heat dissipation requirements of the module.

[0047] S2 : attaching the chip 130 to the second metal layer 123 .

[0048] See also Figure 3 Specifically, a layer of nano copper paste can be first printed on the second metal layer 123, and the nano copper paste layer is used to form the second sintered copper layer 170 in the subsequent sintering process; then the chip 130 is aligned and attached to the nano copper paste layer. In actual preparation, the nano copper paste can be first printed on the surface of the second metal layer 123 by a printing process, and the printing area is 90%-95% of the area of ​​the chip 130, and the printing thickness is 0.12mm-0.15mm. Then use a chip mounter to place the chip 130 on the printed nano copper paste layer. At this time, it is necessary to pay attention to the alignment of the center of the chip 130 with the center of the nano copper paste layer.

[0049] S3: Sintering to form a conductive connection layer 140 on a surface of the chip 130 that is away from the second metal layer 123 .

[0050] See also Figures 4 to 6 Specifically, the nano copper paste dots 131 can be firstly applied on the surface of the chip 130 away from the second metal layer 123; then the nano copper paste dots 131 can be flattened and sintered to form the conductive connection layer 140. In actual preparation, a glue dispenser can be firstly used to apply the nano copper paste dots 131 on the surface of the chip 130, wherein the diameter of the nano copper paste dots 131 in the power circuit area 132 of the chip 130 is between 0.3mm and 0.6mm, and the diameter of the nano copper paste dots 131 in the signal circuit area 133 is between 0.1mm and 0.2mm, such as Figure 4 , Figure 4 Then the first metal layer 122 of the double-sided carrier substrate 110 is placed on the heated base plate 300, using a press sintering device, a sintering operation is performed, such as Figure 5During actual sintering, the pressure head 200 can be used to flatten the nano-copper paste dots 131 and form a nano-copper paste layer. The pressure head 200 and the heating base plate 300 are then used to heat both sides of the nano-copper paste layer at the same time, and sinter to form a conductive connection layer 140 of uniform thickness. The pressure head 200 of the sintering equipment needs to be coated with a buffer film 210. The buffer film 210 has a certain ductility and is resistant to high temperatures. It also has high chemical and physical stability. The nano-copper paste dots 131 can be flattened by the pressure head 200. Sintering under pressure will make the sintering more compact. Here, the pressure head 200 and the heating base plate 300 at the bottom are heated at the same time. Double-sided heating can ensure the uniformity of sintering. After sintering, a conductive connection layer 140 of uniform thickness is formed. Figure 6 structure.

[0051] It should be noted that the buffer film 210 here can preferably be a PI film (Polyimide), which has excellent mechanical properties, thermal stability and chemical stability. Of course, in other preferred embodiments, the buffer film 210 can also be a silicone film, polyphenylene sulfide (PPS) or liquid crystal polymer (LCP) and other materials. At the same time, the pressure sintering temperature can be between 220°C and 280°C. By additionally designing the buffer film 210, on the one hand, it can ensure that the nano copper paste layer is evenly flattened, and on the other hand, it can maintain a pressurized state during the sintering process and smoothly detach from the conductive connection layer 140 after sintering is completed.

[0052] S4: sintering and fixing the first metal layer 122 on the carrier substrate 110 .

[0053] See also Figure 7 Specifically, the first sintered copper layer 160 can be first printed on the surface of the carrier substrate 110, and then the first metal layer 122 and the first sintered copper layer 160 are sintered. In actual preparation, the nano copper paste layer can be printed on the surface of the carrier substrate 110. Since the carrier substrate 110 is preferably a copper substrate, and the first sintered copper layer 160 is also a copper layer, and the copper substrate with full copper interconnection has a smaller warpage than the ordinary copper substrate, between 0-0.005mm, and the printing area of ​​the nano copper paste layer here is bare copper, and the printing thickness is between 0.12mm-0.15mm. After printing, the double-sided metal substrate 120 and the growth substrate are sintered again using a press sintering machine, and the first metal layer 122 is sintered and fixed on the carrier substrate 110 through the first sintered copper layer 160.

[0054] S5: Bonding the connection wire 150 between the conductive connection layer 140 and the third metal layer.

[0055] Please continue to see Figure 1Specifically, one end of the connecting wire 150 is bonded to the conductive connection layer 140, and is electrically connected to the chip 130 through the conductive connection layer 140, and the other end of the connecting wire 150 is bonded to the third metal layer 124, so that the third metal layer 124 is electrically connected to the chip 130 through the connecting wire 150. In actual preparation, a copper wire bonding machine is used to bond copper wires on the conductive connection layer 140 and the second metal layer 123 on the surface of the chip 130. The wire diameter of the copper wire can be 10mil-15mil, and the number of copper wires is between 6-12. Since bonding only needs to be performed on the conductive connection layer 140 at this time, there is no need to additionally design a copper foil structure for precise welding, which reduces the process difficulty.

[0056] It is worth noting that for the plastic-encapsulated module, after completing the step of bonding the copper wire, the injection molding and curing light operations can be carried out, while for the potting module, sealing, glue pouring, curing and other operations can be carried out to finally obtain the finished power module.

[0057] In summary, the semiconductor power module 100 and the preparation method thereof provided by the embodiment of the present invention are as follows: a double-sided metal substrate 120 is arranged on a carrier substrate 110, wherein the first metal layer 122 of the double-sided metal substrate 120 is arranged on the carrier substrate 110 downward, and the second metal layer 123 is arranged upward, and the chip 130 is arranged on the second metal layer 123. After the chip 130 is mounted, a conductive connection layer 140 is sintered to form a surface on the side of the chip 130 away from the second metal layer 123, and the conductive connection layer 140 can cover the electrode of the chip 130. Then, the wire bonding technology is used to bond one end of the connecting wire 150 to the conductive connection layer 140, and the other end to the third metal layer 124. Compared with the prior art, the embodiment of the present invention uses the conductive connection layer 140 fixed by sintering, and does not require additional copper foil welding during actual wire bonding, thereby eliminating the copper foil preparation and welding steps, simplifying the wire bonding process, and directly sintering the conductive connection layer 140 on the surface of the chip, which has low process difficulty and reduces process cost. In addition, compared with the conventional reflow soldering process, the embodiment of the present invention adopts the full copper sintering process, which has lower thermal resistance and higher reliability. Compared with the nano silver sintering process, the embodiment of the present invention has lower cost, and the double-sided copper-clad substrate does not need additional treatment such as silver plating, which simplifies the preparation process.

[0058] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A semiconductor power module, characterized in that: include: A carrier substrate; A double-sided metal substrate, the double-sided metal substrate comprising a bearing insulating layer, a first metal layer, a second metal layer and a third metal layer, the first metal layer being arranged on one side surface of the bearing insulating layer, the second metal layer and the third metal layer being arranged at intervals on the other side surface of the bearing insulating layer, and the first metal layer being arranged on the bearing substrate; at least one chip, wherein the chip is disposed on the second metal layer; A conductive connection layer, which is sintered and fixed on a surface of the chip that is away from the second metal layer and covers the electrodes of the chip; A connecting wire is bonded between the conductive connection layer and the third metal layer.

2. The semiconductor power module according to claim 1, characterized in that: The conductive connection layer is a uniform layer of equal thickness, and the thickness of the conductive connection layer is between 0.1 mm and 0.2 mm.

3. The semiconductor power module according to claim 1, characterized in that: The conductive connection layer is a sintered copper layer, and the first metal layer, the second metal layer and the third metal layer are all copper layers.

4. The semiconductor power module according to claim 3, characterized in that: A first sintered copper layer is disposed between the first metal layer and the carrier substrate, and the first sintered copper layer is used to fix the first metal layer and the carrier substrate together through a sintering process.

5. The semiconductor power module according to claim 4, characterized in that: A second sintered copper layer is further provided between the chip and the second metal layer. The second sintered copper layer is used to fix the chip and the second metal layer together through a sintering process, and the chip and the second metal layer are electrically connected through the second sintered copper layer.

6. The semiconductor power module according to claim 5, characterized in that: The thickness of the first sintered copper layer and the second sintered copper layer is between 0.12 mm and 0.15 mm.

7. The semiconductor power module according to claim 3, characterized in that: The thickness of the first metal layer and the second metal layer is between 0.2 mm and 0.8 mm, and the thickness of the load-bearing insulating layer is between 0.2 mm and 0.6 mm.

8. A method for preparing a semiconductor power module, for preparing the semiconductor power module according to any one of claims 1 to 7, characterized in that: The preparation method comprises: Providing a double-sided metal substrate, the double-sided metal substrate comprising a load-bearing insulating layer, a first metal layer located on one side of the load-bearing insulating layer, and a second metal layer and a third metal layer located on the other side of the load-bearing insulating layer and spaced from each other; attaching a chip to the second metal layer; Sintering a conductive connection layer on a surface of the chip facing away from the second metal layer; Sintering and fixing the first metal layer on the supporting substrate; A connecting wire is bonded between the conductive connecting layer and the third metal layer.

9. The method for preparing a semiconductor power module according to claim 8, characterized in that: The step of sintering a conductive connection layer on a surface of the chip facing away from the second metal layer comprises: Dispensing glue on a surface of the chip on a side away from the second metal layer to form nano copper paste dots; The nano copper paste dots are flattened and sintered to form a conductive connection layer.

10. The method for preparing a semiconductor power module according to claim 9, characterized in that: The step of flattening the nano copper paste dots and sintering to form a conductive connection layer comprises: Flattening the nano copper paste dots to form a nano copper paste layer; Both sides of the nano copper paste layer are heated simultaneously and sintered to form a conductive connection layer with uniform thickness.

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