Feedback current dependent ramp generator for switched mode power supply

Abstract

In order to reduce sub-harmonic oscillations in a switched mode power supply (SMPS), a ramp generator circuit of the SMPS generates a ramp signal having an amplitude corresponding to a sense current flowing through an energy storage device (e.g., an inductor) of the SMPS. The ramp signal is used to control the duty cycle of the SMPS. The ramp generator circuit may include a reference current circuit, a ramp capacitor, and a discharge circuit to periodically discharge the ramp capacitor. The ramp capacitor can be charged with a charging current generated by combining a feedback current corresponding to the sensing current and a reference current generated by the reference current circuit, and can be periodically discharged at a fixed frequency. Or the reference current can be used for charging and discharging at the time determined according to the feedback current.

Description

Technical Field

[0001] The present disclosure relates to switched-mode power supplies (SMPS), and more particularly to circuits and processes for preventing sub-harmonic oscillations in SMPS. Background Art

[0002] SMPS may be affected by subharmonic oscillations which cause noise on the output of the SMPS. When the current flowing through an energy storage device (e.g., an inductor) in the SMPS is less than the peak current, subharmonic oscillations may be reduced by controlling switches in the SMPS based on a sensed current in the energy storage device.

[0003] There is a need to reduce the complexity of circuits and processes used to prevent subharmonic oscillations in a SMPS. Summary of the invention

[0004] Embodiments of the present disclosure relate to preventing subharmonic oscillations in an SMPS, and more particularly to preventing subharmonic oscillations by controlling a rate of change, a frequency, or both of a ramp signal based on a feedback current reflecting a current flowing through an energy storage device and determining a duty cycle of the SMPS by comparing the ramp signal with an error signal corresponding to an error voltage in an output voltage of the SMPS.

[0005] In one embodiment, a switched-mode power supply (SMPS) includes an energy storage device, a current sensing circuit configured to generate a feedback current according to a current flowing through the energy storage device, and a ramp generator circuit configured to generate a ramp signal according to the feedback current. The SMPS determines a duty cycle of the current flowing through the energy storage device using the ramp signal, so that an increase in the magnitude of the feedback current causes a decrease in the duty cycle, and a decrease in the magnitude of the feedback current causes an increase in the duty cycle.

[0006] In another embodiment, a method of controlling an SMPS includes generating a feedback current corresponding to a current flowing through an energy storage device of the SMPS, generating a ramp signal having a slope, a frequency, or both corresponding to the feedback current, and controlling a duty cycle of a power switch using the ramp signal. When the power switch is turned on, a power source of the SMPS provides current to the energy storage device and to a load connected to an output of the SMPS, and when the power switch is turned off, the energy storage device provides the current to the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0008] Figure 1 A circuit according to one embodiment is shown.

[0009] Figure 2 An SMPS according to one embodiment is shown.

[0010] Figure 3 A ramp generator circuit is shown according to one embodiment.

[0011] Figure 4A and 4B Included are used to display Figure 2 The corresponding embodiments of the SMPS Figure 3 The waveform of the operation of the ramp generator.

[0012] Figure 5 A ramp generator circuit according to another embodiment is shown.

[0013] Figure 6 Including to display Figure 5 The waveform of the operation of the ramp generator.

[0014] Figure 7 Including to show the basis Figure 2 Example of operating waveforms of an SMPS.

[0015] Figure 8 An SMPS according to another embodiment is shown.

[0016] Fig. 9 A ramp generator circuit according to another embodiment is shown.

[0017] Fig.10 Including to display Fig. 9 The waveform of the operation of the ramp generator.

[0018] Fig.11 Including to show the basis Figure 8 Example of operating waveforms of an SMPS.

[0019] Fig.12 A ramp generator circuit according to another embodiment is shown. DETAILED DESCRIPTION

[0020] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the features of the present invention may be implemented in different forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to make the present disclosure comprehensive and complete and to fully convey the scope of the claims to those skilled in the art. In the present disclosure, similar reference numerals represent similar components in different drawings and embodiments.

[0021] It should be understood that although the terms "first" and / or "second" may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. Similarly, the second element may also be referred to as the first element.

[0022] The drawings are not necessarily drawn to scale and in some instances proportions may have been exaggerated in order to clearly illustrate features of the embodiments.

[0023] Figure 1 A circuit 100 is shown according to one embodiment. The circuit 100 includes a power source 102, a SMPS circuit 104, and a load 106.

[0024] The power source 102 supplies a direct current (DC) input voltage Vin to the SMPS circuit 104. The power source 102 may include a primary or secondary battery, an alternating current (AC) to direct current (DC) conversion circuit, a power factor correction (PFC) circuit, or a combination thereof.

[0025] The SMPS 104 generates an output voltage Vout using the input voltage Vin, and the output voltage Vout is provided to the load 106. The SMPS 104 generates the output voltage Vout by turning on and off an input current derived from the input voltage Vin.

[0026] SMPS 104 may use pulse width modulation (PWM), pulse frequency modulation (PFM), or a combination thereof to turn the input current on and off. In one embodiment, SMPS 104 may include a fixed frequency PWM circuit, in which pulses occur at a fixed frequency but have a varying duration (width, i.e., duty cycle). In another embodiment, SMPS 104 may include a variable frequency PWM circuit, in which both the frequency and duration of the pulses vary.

[0027] Feedback loops, including those caused by parasitic inductance and capacitance, may cause unintended oscillations in the output voltage Vout. These unintended oscillations may occur at a frequency less than the frequency at which the SMPS 104 switches the input current, and may therefore be referred to as subharmonic oscillations.

[0028] The SMPS 104 is configured to reduce or eliminate subharmonic oscillations, as described below.

[0029] Figure 2 SMPS 204 is shown according to one embodiment. SMPS 204 receives an input voltage Vin from power source 202 and provides an output voltage Vout to load 206. Power source 202, SMPS 204, and load 206 may correspond to Figure 1 The power supply 102, SMPS 104, and load 106 are provided. Figure 2 The SMPS 204 shown in FIG. 1 is a buck converter, but the embodiment is not limited thereto.

[0030] SMPS 204 includes a driver circuit 210, two power switches (a high switch 212 and a low switch 214), an energy storage device in the form of an inductor 216, a capacitor 218, a pulse width modulation (PWM) control circuit (including a pre-drive circuit 220 and a first comparator 222), a voltage feedback circuit 226, a ramp generator 228, a pulse width modulation (PWM) clock circuit 234, a current sensing circuit 236, and a current sensor 238.

[0031] SMPS 204 operates according to the PWM clock RCK generated by the PWM clock circuit 234. The PWM clock circuit 234 may generate the PWM clock RCK with a fixed frequency, but the embodiment is not limited thereto. In an embodiment, the frequency of the PWM clock RCK may be between 100 KHz and 100 MHz, but the embodiment is not limited thereto.

[0032] The driver circuit 210 generates a high gate signal HG and a low gate signal LG according to the PWM signal PWM. The driver circuit 210 may assert the high gate signal HG in response to the assertion of the PWM signal PWM, and de-assert the high gate signal HG in response to the de-assertion of the PWM signal PWM. The driver circuit 210 may assert the low gate signal LG in response to the de-assertion of the PWM signal PWM, and de-assert the low gate signal LG in response to the assertion of the PWM signal PWM. The driver circuit 210 may introduce a delay (referred to as a dead time) in the assertion of the high gate signal HG and in the assertion of the low gate signal LG to ensure that the switch driven by each signal is completely turned off before the switch driven by the other signal is turned on. The implementation details of various different embodiments of the driver circuit 210 are well known to those of ordinary skill in the art and are omitted for brevity.

[0033] The high switch 212 is turned on in response to the assertion of the high gate signal HG, and is turned off in response to the deassertion of the high gate signal HG. When the high switch 212 is turned on, current can flow from the input voltage Vin through the inductor 216 and reach the load 206, storing energy in the inductor 216. Figure 2 The high switch 212 in FIG. 2 is shown as a p-channel metal oxide semiconductor field effect transistor (pMOSFET), but the embodiment is not limited thereto.

[0034] A low switch 214 is turned on in response to the assertion of the low gate signal LG, and is turned off in response to the de-assertion of the low gate signal LG. When the low switch 214 is turned on, current generated by energy stored in the inductor 216 may flow to the load 206. Figure 2 The lower switch 214 in FIG. 2 is shown as an n-channel metal oxide semiconductor field effect transistor (nMOSFET), but the embodiment is not limited thereto.

[0035] Capacitor 218 operates to reduce fluctuations in the output voltage Vout.

[0036] The voltage feedback circuit 226 generates an error signal Verror, the magnitude of which is determined according to the output voltage Vout and the reference voltage Vref. The voltage value of the error signal Verror corresponds to the difference between the output voltage Vout and the desired output voltage (corresponding to the reference voltage Vref). The implementation details of various different embodiments of the voltage feedback circuit 226 are well known to those skilled in the art and are omitted for brevity.

[0037] In the embodiment shown herein, in order for the voltage feedback circuit 226 to generate the error signal Verror, the output voltage Vout is divided by a predetermined scaling factor S, and then the result of the division is subtracted from the reference voltage Vref, thereby obtaining

[0038] Verror=Vref-(Vout / S) Equation 1A.

[0039] Therefore, the increase and decrease of the error signal Verror correspond to the decrease and increase of the output voltage Vout, respectively. However, embodiments are not limited to this process of generating the error signal Verror.

[0040] The first comparator 222 compares the error signal Verror with the ramp signal Vramp generated by the ramp generator 228 to generate a phase control signal PC. When the ramp signal Vramp is greater than the error signal Verror, the first comparator 222 asserts the phase control signal PC, otherwise, the phase control signal PC is de-asserted.

[0041] The pre-driver circuit 220 generates a PWM signal SW according to the PWM clock RCK and the phase control signal PC. Figure 4A and 4B As described above, in some embodiments, the pre-driver circuit 220 may generate the PWM signal SW by asserting the PWM signal SW in response to the assertion of the PWM clock RCK and de-asserting the PWM signal SW in response to the assertion of the phase control signal PC, while in other embodiments, the pre-driver circuit 220 may generate the PWM signal SW by asserting the PWM signal SW in response to the assertion of the phase control signal PC and de-asserting the PWM signal SW in response to the assertion of the PWM clock RCK. However, the embodiments are not limited thereto. The implementation details of various different examples of the pre-driver circuit 220 are well known to those of ordinary skill in the art and are omitted for brevity.

[0042] The current sensing circuit 236 generates a feedback current Isense which is proportional to the inductor current I flowing in the inductor 216 sensed by the current sensor 238. L For example, when the inductor current I L In the example embodiment where the magnitude of Isense varies from 0 to 500 mA, the magnitude of the feedback current Isense may vary from 0 to 2.5 μA.

[0043] The current sensing circuit 236 may generate the feedback current Isense by using a current mirror that receives the output of the current sensor 238. The output generated by the current sensor 238 has a similar frequency to the inductor current I LProportional to the current.

[0044] Although the ramp generator 228 according to one embodiment performs an integration function on the feedback current Isense (as shown in the following equation 3B), in some embodiments, the current sensing circuit 236 may calculate the average value of the output of the current sensor 238 over a period of time, thereby generating a feedback current Isense corresponding to the inductor current I L The time period may correspond to a cycle of the PWM clock RCK, but the embodiment is not limited thereto.

[0045] Similarly, in some embodiments, the current sensing circuit 236 may perform additional low-pass filtering on the output of the current sensor 238, so that the magnitude of the generated feedback current Isense corresponds to the inductor current I L The cut-off frequency used to filter the output of the current sensor 238 may be substantially less than the frequency of the PWM clock RCK.

[0046] The ramp generator circuit 228 generates the ramp signal Vramp based on the PWM clock RCK and the feedback current Isense, as will be described below. Figure 3 described.

[0047] Figure 3 A ramp generator circuit 328 is shown according to one embodiment. The ramp generator circuit 328 may be included in Figure 2 The ramp generator circuit 228 receives the inductor current I L The feedback current Isense and the PWM clock RCK are used to generate the ramp signal Vramp according to the received signal.

[0048] The ramp generator circuit 328 includes a monostable multivibrator (one-shot) 342, a switch 344, a current source 346, and a ramp capacitor 348. The current source 346 can be a constant current source and can provide a current of 10 microamperes in an example embodiment, but the embodiment is not limited thereto. The current source 346, the ramp signal Vramp, the feedback current Isense, the switch 344, and the ramp capacitor 348 are all coupled to the output node N.

[0049] exist Figure 3 In the embodiment shown in FIG. 3 , the switch 344 is an nMOSFET, but the embodiment is not limited thereto.

[0050] Will refer to Figure 2 The SMPS204 and Figure 4AThe operation of the ramp generator circuit 328 according to the first embodiment is explained using the waveforms shown in FIG.

[0051] At the start time t0 , the PWM clock RCK is asserted, causing the one shot 342 to assert the ramp reset signal RReset for a predetermined interval Treset, which can provide enough time to fully discharge the ramp capacitor 348 through the switch 344 .

[0052] At the same time, in response to the assertion of the PWM clock RCK, the pre-driver 220 asserts the PWM signal SW, thereby closing the low switch 214 and opening the high switch 212 to allow current to flow from the power source 202 into the inductor 216 and the load 206. This causes energy to be stored in the inductor 216.

[0053] As a result of the ramp reset signal RReset being asserted, the switch 344 is turned on, thereby discharging the ramp capacitor 348 and clamping the ramp signal Vramp to ground.

[0054] After the assertion of the ramp reset signal RReset, after the interval Treset has passed, the one shot 342 de-asserts the ramp reset signal RReset, thereby closing the switch 344. Therefore, the ramp signal Vramp stops being clamped to ground.

[0055] Since the ramp signal Vramp is no longer clamped to ground, the ramp capacitor 348 is charged so that its voltage rises at a rate determined by the capacitance C of the ramp capacitor 348 and the charging current corresponding to the net current at the node generating the ramp signal Vramp. The ramp signal Vramp feeds a very high impedance load, and therefore, the charging current is determined by the reference current Iref provided by the current source 346 and the current provided by the feedback current Isense. Therefore, the voltage of the ramp signal Vramp increases at a rate R given by the following equation:

[0056] R=(Iref+Isense) / C Equation 2A

[0057] Thus the slope increases with the inductor current I L As the feedback current Isense increases, and for the specific example case where the value of the feedback current Isense is substantially constant in the interval from the start time t0 to the next start time t0′, the ramp signal Vramp has a voltage given by the following formula:

[0058] Vramp=(t-(t0+Treset))*(Iref+Isense) / C Equation 3A

[0059] Where t is the time between the start time t0 and the next start time t0'. L And therefore, in the more general case that the feedback current Isense changes in the interval from the start time t0 to the next start time t0′, the ramp signal Vramp has a voltage given by:

[0060]

[0061] Wherein, Isense(x) is the value of the feedback current Isense at time x, and Vramp(t) is the value of the ramp signal Vramp at time x.

[0062] At the switching time t1 , the voltage of the ramp signal Vramp becomes equal to or greater than the error signal Verror. Therefore, the first comparator 222 asserts the phase control signal PC.

[0063] In response to the assertion of the phase control signal PC, shortly after the switching time t1 , the pre-driver 220 de-asserts the PWM signal SW, thereby turning off the high switch 212 and turning on the low switch 214 to allow current generated by the energy stored in the inductor 216 to flow into the load 206 .

[0064] Therefore, the duration Dch of the charging phase of the SMPS 204 (corresponding to the interval between the start time t0 and the switching time t1 during which energy is stored in the inductor 216) is determined by:

[0065]

[0066] As can be seen from equation 4A, the duration Dch of the charging phase increases as the error signal Verror increases (that is, as the output voltage Vout decreases), and as the magnitude of the feedback current Isense increases (that is, as the inductor current I L increase) and decrease.

[0067] Then, starting from the next start time t0', the above events are repeated.

[0068] Will refer to Figure 2 The SMPS204 and Figure 4B The operation of the ramp generator circuit 328 according to the second embodiment is explained by referring to the waveforms shown in FIG. The operation of the ramp generator circuit 328 is different due to the difference of other components of the SMPS 204.

[0069] Specifically, in the second embodiment, the error signal Verror is generated by subtracting the scaled output voltage Vout from the reference voltage Vref:

[0070] Verror=(Vout / S)-Vref Equation 1B.

[0071] And therefore, when the output voltage Vout decreases, the error signal Verror increases.

[0072] Furthermore, in the second embodiment, the feedback current Isense is a sink rather than a source, so that the voltage of the ramp signal Vramp increases at a rate R given by the following equation:

[0073] R=(Iref-Isense) / C Equation 2B

[0074] Thus the slope increases with the inductor current I L Therefore, the ramp signal Vramp has a voltage given by:

[0075]

[0076] For the final difference, in the second embodiment, the pre-driver circuit 220 responds to the assertion of the phase control signal PC indicating that the error signal Verror is greater than the ramp signal Vramp, starts a charging interval for charging the inductor 216 by asserting the PWM signal SW, and responds to the assertion of the PWM clock RCK to end the charging interval by de-asserting the PWM signal SW.

[0077] That is, at the start time t0b, the PWM clock RCK is asserted, so that the one shot 342 asserts the ramp reset signal RReset for a predetermined interval Treset. The interval Treset can provide enough time to fully discharge the ramp capacitor 348 through the switch 344.

[0078] Simultaneously, in response to the assertion of the PWM clock RCK, the pre-driver 220 de-asserts the PWM signal SW, thereby turning on the low switch 214 and turning off the high switch 212 to allow the current generated by the energy stored in the inductor 216 to flow into the load 206 .

[0079] As a result of the ramp reset signal RReset being asserted, the switch 344 is turned on, thereby discharging the ramp capacitor 348 and clamping the ramp signal Vramp to ground.

[0080] After the assertion of the ramp reset signal RReset, after the interval Treset has passed, the one shot 342 de-asserts the ramp reset signal RReset, thereby closing the switch 344. Therefore, the ramp signal Vramp stops being clamped to ground.

[0081] Since the ramp signal Vramp is no longer clamped to ground, the ramp capacitor 348 is charged so that its voltage rises at a rate determined by the capacitance C of the ramp capacitor 348 and the charging current corresponding to the net current at the node generating the ramp signal Vramp. The ramp signal Vramp feeds a very high impedance load, and therefore, the charging current is determined by the reference current Iref provided by the current source 346 and the current injected by the feedback current Isense. Therefore, the voltage of the ramp signal Vramp increases at a rate R given by the above equation 2B, and the ramp voltage Vramp has a voltage value according to the above equation 3C.

[0082] At the switching time t1b, the voltage of the ramp signal Vramp becomes equal to or greater than the error signal Verror. Therefore, the first comparator 222 asserts the phase control signal PC.

[0083] In response to the assertion of the phase control signal PC, shortly after the switching time t1b, the pre-driver 220 asserts the PWM signal SW, thereby turning on the high switch 212 and turning off the low switch 214 to allow current to flow from the input voltage Vin into the inductor 216 and the load 206 , which causes energy to be stored in the inductor 216 .

[0084] Starting at the next start time t0b′, the above events are repeated (including the end of the charging cycle of the inductor 2116).

[0085] Therefore, the duration Dch of the charging phase of the SMPS 204 (corresponding to the interval between the switching time t1b and the start of the next clock cycle at the second start time t0b′, during which energy is stored in the inductor 216) is determined by:

[0086]

[0087] Wherein, Tc is the cycle time of the PWM clock RCK. As can be seen from equation 4B, the duration Dch of the charging phase increases as the error signal Verror decreases (that is, as the output voltage Vout decreases), and as the magnitude of the injection feedback current Isense increases (that is, as the inductor current I during the charging phase increases). L increase) and decrease.

[0088] In the two embodiments of the SMPS 204 described above, the ramp generator circuit 328 generates a voltage according to the inductor current I L The amplitude of the ramp signal Vramp is controlled so that for a given error signal Verror, the duty cycle of each embodiment of the SMPS 204 is respectively between the inductor current I L Although two embodiments are described above, the embodiments are not limited thereto.

[0089] Figure 5 A ramp generator circuit 528 is shown according to another embodiment. The ramp generator circuit 528 may be included in Figure 2 The ramp generator circuit 228 receives the inductor current I L The feedback current Isense and the PWM clock RCK are used to generate the ramp signal Vramp according to the received signal. Figure 3 Unlike the ramp generator circuit 328 (which generates a ramp signal Vramp whose ramp starting voltage corresponds to the ground voltage), the ramp generator circuit 528 generates a ramp signal Vramp whose ramp starting voltage corresponds to the ramp low voltage VL, which can simplify the design of the circuit receiving the ramp signal Vramp.

[0090] The ramp generator circuit 528 includes a second comparator 540 and a set-reset flip-flop (SRFF) 542. The ramp generator circuit 528 also includes a Figure 3 The switch 344, the current source 346, and the ramp capacitor 348 are all coupled to the output node N. The current source 346, the ramp signal Vramp, the feedback current Isense, the switch 344, and the ramp capacitor 348 are all coupled to the output node N.

[0091] Will refer to Figure 2 The SMPS204 and Figure 6 The operation of the ramp generator circuit 528 will be explained based on the waveforms shown in FIG. Figure 4A The operation is explained with reference to the first embodiment of the SMPS 204 described above, however, the embodiments are not limited thereto, and those skilled in the art will appreciate that the ramp generator circuit 528 may also operate as described above with reference to FIG. Figure 4B The second embodiment of the SMPS 204 is described.

[0092] At the start time tt0, the PWM clock RCK is asserted for a short interval (i.e., for one pulse), and thus, the SRFF 342 enters a reset state, wherein the inverted output QB of the SRFF 342 asserts the ramp reset signal RReset. As a result of the ramp reset signal RReset being asserted, the switch 344 is turned on, thereby discharging the ramp capacitor 348.

[0093] At the same time, in response to the assertion of the PWM clock RCK, the pre-driver 220 asserts the PWM signal SW, thereby turning off the low switch 214 and turning on the high switch 212 to allow current to flow from the power source 202 into the inductor 216 and the load 206 .

[0094] Shortly after the assertion of the ramp reset signal RReset, the ramp capacitor 348 is sufficiently discharged to cause the ramp signal Vramp to drop below the ramp low voltage VL. This causes the second comparator 540 to assert the comparison signal CMP.

[0095] As a result of the assertion of the comparison signal CMP, the SRFF 342 enters a set state in which the inverting output QB is low. This closes the switch 344, and thus, the ramp capacitor 348 begins to charge. When the ramp signal Vramp charges to a voltage level higher than the ramp low voltage VL, the second comparator 540 deasserts the comparison signal CMP.

[0096] When the switch 344 is closed, the ramp capacitor 348 is charged at a rate determined by the capacitance C of the ramp capacitor 348 and the charging current corresponding to the net current at the node generating the ramp signal Vramp. The ramp signal Vramp feeds a very high impedance load, and therefore, the charging current is determined by the reference current Iref provided by the current source 346 and the current injected by the feedback current Isense. Therefore, the ramp signal Vramp increases at a rate R given by the above equation 1A, and the ramp signal Vramp has a voltage given by the following equation:

[0097]

[0098] Wherein, Tdl is the discharge interval required for the ramp capacitor to discharge to the ramp low voltage VL, and t is the time between the start time tt0 and the next start time tt0'. In an exemplary embodiment, the discharge interval Tdl is less than 1% of the period of the PWM clock RCK, but the embodiment is not limited thereto.

[0099] At the switching time tt1 , the voltage of the ramp signal Vramp becomes equal to or greater than the error signal Verror. Therefore, the first comparator 222 asserts the phase control signal PC.

[0100] In response to the assertion of the phase control signal PC, shortly after the switching time tt1 , the pre-driver 220 de-asserts the PWM signal SW, thereby turning off the high switch 212 and turning on the low switch 214 to allow current generated by the energy stored in the inductor 216 to flow into the load 206 .

[0101] Therefore, the duration Dch of the charging phase of the SMPS 204 (corresponding to the interval between the start time t0 and the switching time tt1 during which energy is stored in the inductor 216) is determined by:

[0102]

[0103] As can be seen from equation 5, the duration Dch of the charging phase increases as the error signal Verror increases, and as the magnitude of the feedback current Isense increases (that is, as the inductor current I L increase) and decrease.

[0104] and Figure 3 Unlike the ramp generator circuit 328 of FIG. 5 , the ramp generator circuit 528 does not use a predetermined discharge interval at the beginning of each ramp cycle to discharge the ramp capacitor 348. Instead, the ramp generator circuit 528 uses a feedback circuit including a second comparator 540 to stop discharging the ramp capacitor 348 when the voltage across the ramp capacitor 348 reaches the desired starting voltage level for the ramp.

[0105] Figure 7 Included is a diagram showing a SMPS (eg Figure 2 The waveform of the operation of the SMPS204) includes a ramp signal Vramp, an error signal Verror, an inductor current I L , load current, the output voltage of the SMPS, a reference voltage Vref, and a driver duty cycle of the driver 210 that controls the charging and discharging of energy in the energy storage inductor of the SMPS.

[0106] like Figure 7 As can be seen from the figure, the change of the load current is reflected in the inductor current I during the switching cycle of the SMPS. L When the load current changes, the inductor current I L The change in the magnitude of lags behind the change in the load current.

[0107] Since the above embodiment changes the charging slope of the ramp signal Vramp, and since in the above embodiment, the duration of the ramp is fixed to the cycle time of the PWM clock RCK (here, it has a constant frequency), the maximum voltage reached by the ramp signal Vramp depends on the inductor current I L Specifically, when the inductor current I L When decreasing (e.g. Figure 7 between 2 and 5 microseconds), the maximum voltage reached by the ramp signal Vramp increases, and when the inductor current I L When increasing (for example, Figure 7 5 and 8 microseconds), the maximum voltage reached by the ramp signal Vramp decreases.

[0108] Figure 8 A SMPS 804 is shown according to another embodiment. Figure 8 The elements 802 to 818, 822, 826, 836 and 838 correspond to Figure 2 202 to 218, 222, 226, 236 and 238, and therefore, for the sake of brevity, the description of Figure 8 Description of the above elements.

[0109] SMPS 804 is a variable frequency PWM SMPS and does not require, for example, Figure 2 The PWM clock generated by the PWM clock circuit 234. Because the SMPS 804 does not rely on the PWM clock, therefore, Figure 8 The function of the pre-driver circuit 820 is different from Figure 2 The function of the pre-driver circuit 220 is different from that of the ramp generator circuit 828. Figure 2 Function of the ramp generator circuit 228.

[0110] The pre-driver circuit 820 controls the PWM signal SW according to the phase control signal PC, so that when the phase control signal PC is asserted, the PWM signal SW is asserted, and when the phase control signal PC is de-asserted, the PWM signal SW is de-asserted. Therefore, the pre-driver circuit 820 may include an amplifier, a level shifter, etc. Since such pre-drivers are well known in the art, additional description is omitted.

[0111] The ramp generator circuit 828 controls the frequency of the ramp signal Vramp according to the feedback current Isense. However, the slope of the ramp signal Vramp does not change with the change of the feedback current Isense, and therefore, for a given error signal Verror, the duty cycle changes according to the feedback current Isense, and thus the inductor current I corresponding to the feedback current Isense.L change.

[0112] Fig. 9 A ramp generator circuit 928 is shown according to another embodiment. The ramp generator circuit 928 may correspond to Figure 8 Ramp generator circuit 828.

[0113] The ramp generator circuit 928 includes a current-to-voltage converter 940, first and second comparators 941 and 942, and a set-reset flip-flop (SRFF) 944. The ramp generator circuit 928 also includes a current-to-voltage converter 940, a first comparator 941 and a second comparator 942, and a set-reset flip-flop (SRFF) 944. Figure 3 The switch 344 , the current source 346 , and the ramp capacitor 348 .

[0114] The I2V converter 940 receives the feedback current Isense and generates a feedback voltage Vsense corresponding to the current value of the feedback current Isense. The feedback voltage Vsense decreases in response to an increase in the magnitude of the feedback current Isense and decreases in response to an increase in the magnitude of the feedback current Isense and may include a predetermined offset voltage Voffset.

[0115] Therefore, in an embodiment, the value of the feedback voltage Vsense may correspond to:

[0116] Vsense=Voffset-k×|Isense| Equation 7

[0117] Wherein, k is a predetermined scaling factor, and Voffset corresponds to the maximum voltage of the ramp signal Vramp. However, embodiments are not limited to the linear relationship between the feedback current Isense and the feedback voltage Vsense as embodied in Equation 6, for example.

[0118] The second comparator 941 compares the voltage value of the feedback voltage Vsense with the voltage value of the ramp signal Vramp, and asserts the first comparison signal CMP1 when the ramp signal Vramp is greater than the feedback voltage Vsense, and de-asserts the first comparison signal CMP1 when the ramp signal Vramp is less than the feedback voltage Vsense. A person of ordinary skill in the relevant art will appreciate that various embodiments of the second comparator 941 may assert or de-assert the first comparison signal CMP1 when the ramp signal Vramp is equal to the feedback voltage Vsense, or may have a built-in hysteresis.

[0119] The third comparator 942 compares the voltage value of the ramp low voltage VL with the ramp signal Vramp, asserts the second comparison signal CMP2 when the ramp signal Vramp is less than the ramp low voltage VL, and de-asserts the second comparison signal CMP2 when the ramp signal Vramp is greater than the ramp low voltage VL. A person of ordinary skill in the relevant art will appreciate that various embodiments of the second comparator 941 may assert or de-assert the first comparison signal CMP1 when the ramp signal Vramp is equal to the feedback voltage Vsense, or may have a built-in hysteresis.

[0120] The SRFF 944 is reset in response to the first comparison signal CMP1 being asserted, and is set in response to the second comparison signal CMP2 being asserted. Therefore, the ramp reset signal RReset generated at the inverted output QB of the SRFF 944 is asserted in response to the first comparison signal CMP1 being asserted, and is de-asserted in response to the second comparison signal CMP2 being asserted.

[0121] The switch 344 is controlled by the ramp reset signal RReset, as described in relation to Figure 3 described.

[0122] Fig.10 Including to display Figure 8 The waveform of the operation of the ramp generator circuit 928. Fig.10 In the example, the first comparison signal CMP1 is asserted before the initial start time tt0 , so that the ramp reset signal RReset is asserted, thereby turning on the switch 344 .

[0123] The switch 344 is turned on to discharge the ramp capacitor 346 , thereby reducing the voltage value of the ramp signal Vramp.

[0124] When the voltage value of the ramp signal Vramp drops below the feedback voltage Vsense, the second comparator 941 de-asserts the first comparison signal CMP1 .

[0125] When the voltage value of the ramp signal Vramp drops below the voltage value of the error signal Verror, Figure 8 The first comparator 822 de-asserts the phase control signal PC, causing the PWM signal SW to be de-asserted, and thus, the high switch 812 is turned off and the low switch 814 is turned on, allowing the energy stored in the inductor 816 to provide current to the load 806.

[0126] When the voltage value of the ramp signal Vramp drops below the ramp low voltage VL, the second comparison signal CMP2 is asserted, so that the ramp reset signal RReset is de-asserted, thereby turning off the switch 344 .

[0127] The switch 344 is closed to allow the reference current Iref to charge the ramp capacitor 346, so that the voltage value of the ramp signal Vramp increases.

[0128] At a first time tt1, the ramp signal Vramp reaches and then exceeds the error signal Verror. In response, Figure 8 The first comparator 822 asserts the phase control signal PC, causing the PWM signal SW to be asserted, and therefore, the high switch 812 is turned on and the low switch 814 is turned off, allowing current to flow from the input voltage Vin to the inductor 816 and the load 806, which stores energy in the inductor 816, thereby starting a charging interval.

[0129] Subsequently, at the next start time tt0 ′, the voltage value of the ramp signal Vramp becomes greater than the feedback voltage Vsense, causing the second comparator 941 to assert the first comparison signal CMP1 , which causes the above sequence of events starting at the start time tt0 to repeat, thereby ending the charging interval.

[0130] like Fig.10 As can be seen in FIG. 9 , in the ramp generator circuit 928, the slope of the ramp signal Vramp depends only on the reference current Iref and the capacitance of the ramp capacitor 348, and the on time of the phase control signal PC is determined by the slope of the ramp signal Vramp and the error signal Verror. However, the cycle time (and therefore, the frequency) of the ramp signal Vramp is determined by the feedback current Isense, and therefore, the duty cycle of the phase control signal PC varies according to both the error signal Verror and the feedback current Isense.

[0131] Specifically, the voltage of the ramp signal Vramp increases at a rate R given by:

[0132] R=Iref / C Equation 8

[0133] Wherein, C is the capacitance of the ramp capacitor 348. The interval between the start time tt0 and the first time tt1 (during which the current flows into the inductor 816) is given by:

[0134] Tc-(tt1-tt0)=Tc-(Verror-VL) / R Equation 9.

[0135] Wherein, Tc is the cycle time Tc of the ramp signal Vramp. Considering the above equation 6, the cycle time Tc of the ramp signal Vramp is given by the following equation:

[0136]

[0137] Wherein, Vsense is the voltage value of the feedback voltage Vsense, and the ramp range voltage Vrr is the difference between the ramp low voltage VL and the maximum value (Voffset) of the feedback voltage Vsense, and corresponds to the maximum amplitude (Voffset-VL) of the ramp signal Vramp. Therefore, the duty cycle DC of the SMPS 804 is equal to:

[0138]

[0139] As can be seen from equation 11, the duty cycle DC of the SMPS 804 (ie, the PWM signal SW) increases as the error signal Verror increases, but decreases with the inductor current I L On the other hand, the frequency of the PWM signal SW (which is the inverse of the cycle time Tc determined according to equation 10) is proportional to the inductor current I L Correspondingly, the voltage increases when the sensing current Isense increases, and decreases when the sensing current Isense decreases.

[0140] Fig.11 Included is a diagram showing a SMPS (eg Figure 8 The waveform of the operation of the SMPS 804) includes a ramp signal Vramp, an error signal Verror, an inductor current I L , load current, output voltage of the SMPS, reference voltage Vref, duty cycle of the PWM signal SW provided to the driver circuit 810 (controlling charging and discharging of energy in the energy storage inductor of the SMPS), and frequency of the PWM signal SW.

[0141] like Fig.11 As can be seen from the figure, the change of the load current is reflected in the inductor current I during the switching cycle of the SMPS. L When the load current changes, the inductor current I L The change in the magnitude of the load current lags behind the change in the load current.

[0142] Since the embodiment changes the cycle time (and thus the frequency) of the ramp signal Vramp, and since in the illustrated embodiment the slope of the ramp signal Vramp is fixed, the maximum voltage reached by the ramp signal Vamp is dependent on the inductor current I L Specifically, when the inductor current I L When decreasing (e.g. Fig.11The maximum voltage reached by the ramp signal Vramp increases, and the cycle time increases, so that the driver frequency (corresponding to the frequency of the ramp signal Vramp) decreases. L When it increases (eg, between 3 and 6 microseconds), the cycle time and the maximum voltage reached by the ramp signal Vramp decrease, and the driver frequency (corresponding to the frequency of the ramp signal Vramp) increases.

[0143] Fig.12 A ramp generator circuit 1228 is shown according to another embodiment. The ramp generator circuit 928 may correspond to Figure 8 Ramp generator circuit 828.

[0144] Ramp generator circuit 1228 includes Fig. 9 The current-to-voltage (I2V) converter 940, the first and second comparators 941 and 942, and the set-reset flip-flop (SRFF) 944. The ramp generator circuit 928 also includes Figure 3 The switch 344, current source 346, and ramp capacitor 348 are described. Since the operation of these components is similar to that of Fig. 9 and 3 As described above, therefore, for the sake of brevity, further description is omitted.

[0145] The ramp generator circuit 1228 differs from the ramp generator circuit 928 in that the feedback current Isense controls not only the limitation on the maximum value of the ramp signal Vramp (as in the ramp generator circuit 928), but also controls the rate R at which the ramp signal Vramp increases.

[0146] Specifically, the voltage of the ramp signal Vramp increases at a rate R given by:

[0147] R=(Iref+Isense) / C Equation 12

[0148] Wherein, C is the capacitance of the ramp capacitor 348. The cycle time Tc of the ramp signal Vramp is given by the following formula:

[0149]

[0150] As can be seen from equation 13, the duty cycle DC of the SMPS 804 (ie, the PWM signal SW) increases as the error signal Verror increases, but decreases with the inductor current I LOn the other hand, the frequency of the PWM signal SW (which is the inverse of the cycle time Tc determined according to equation 10) is proportional to the inductor current I L Correspondingly, the sense current Isense increases when it decreases, and decreases when it increases.

[0151] By Figure 3 , 5 , 9 and 12 are compared with the related art and it can be seen that, compared with previously known solutions, the embodiments of the present invention use simpler circuits to reduce or prevent subharmonic oscillations in SMPS.

[0152] The scheme of the present disclosure has been described in conjunction with the specific embodiments of the present disclosure presented as examples. Various substitutions, modifications, and changes may be made to the embodiments described herein without departing from the scope of the claims set forth below. Therefore, the embodiments described herein are intended to be illustrative rather than limiting.

Claims

1. A switch mode power supply (SMPS), characterized in that include: Energy storage devices; a current sensing circuit configured to generate a feedback current according to a current flowing through the energy storage device; as well as a ramp generator circuit configured to generate a ramp signal according to the feedback current, The SMPS is configured to control the duty cycle of the current flowing through the energy storage device using the ramp signal.

2. The SMPS according to claim 1, characterized in that in, The generator circuit is configured to control the amplitude of the ramp signal according to the feedback current, the amplitude being the difference between the highest value and the lowest value of the ramp signal during a cycle.

3. The SMPS according to claim 1, characterized in that in, The increase in the magnitude of the feedback current causes a decrease in the duty cycle, and Therein, the reduction in the magnitude of the feedback current causes the duty cycle to increase.

4. The SMPS according to claim 3, characterized in that The ramp generator circuit includes: Reference current source; Output nodes, configured to: receiving the output of the reference current source and the feedback current, and generating a charging current according to the sum of the output of the reference current source and the feedback current; a ramp capacitor coupled to the output node; and A discharge circuit is coupled to both ends of the ramp capacitor and receives a clock signal, wherein the discharge circuit is configured to discharge the ramp capacitor in response to the clock signal. wherein the ramp capacitor is charged according to the charging current, and The ramp signal is generated at the output node.

5. The SMPS according to claim 4, characterized in that The increasing rate of the ramp signal varies according to the magnitude of the feedback current.

6. The SMPS according to claim 4, characterized in that The discharge circuit includes: A discharge switch coupled to both ends of the ramp capacitor; and A one-shot circuit controls the discharge switch according to the clock signal. The one-shot circuit turns on the switch for a preset interval in response to an edge of the clock signal.

7. The SMPS according to claim 4, characterized in that The discharge circuit includes: A discharge switch coupled to both ends of the ramp capacitor; and A comparator circuit outputs a comparison signal according to a comparison between the S voltage of the ramp signal and the ramp low voltage; and A control circuit configured to: In response to the edge of the clock signal, the discharge switch is turned on, and In response to the comparator signal indicating that the voltage of the ramp signal is less than or equal to the ramp low voltage, the discharge switch is turned off.

8. The SMPS according to claim 3, characterized in that The ramp generator is configured to control the cycle time of the ramp signal according to the magnitude of the feedback current.

9. The SMPS according to claim 3, characterized in that The ramp generator circuit includes: a current-to-voltage converter configured to generate a feedback voltage according to the feedback current; A reference current source generates a reference current; a ramp capacitor configured to be charged according to the reference current; and a discharge circuit coupled to both ends of the ramp capacitor and receiving the feedback voltage, the discharge circuit being configured to discharge the ramp capacitor in response to the ramp signal being greater than the feedback voltage; The ramp signal is generated at an output node coupled between the reference current source and the capacitor.

10. The SMPS according to claim 9, characterized in that The discharge circuit includes: A discharge switch coupled to both ends of the ramp capacitor; A control circuit configured to: In response to the ramp signal being less than or equal to a predetermined ramp low voltage, turning on the discharge switch, and In response to the ramp signal being greater than or equal to the feedback voltage, the discharge switch is closed.

11. The SMPS according to claim 1, wherein: The energy storage device is an inductor.

12. A method of controlling a switch mode power supply (SMPS), characterized in that: The method includes: generating a feedback current corresponding to a current flowing through an energy storage device of the SMPS; generating a ramp signal having an amplitude corresponding to the feedback current, the amplitude being a difference between a highest value and a lowest value of the ramp signal during one cycle; and The ramp signal is used to control the duty cycle of the power switch. wherein, when the power switch is turned on, the power supply of the SMPS provides current to the energy storage device and to a load connected to the output of the SMPS, and When the power switch is turned off, the energy storage device provides the current to the load.

13. The method according to claim 11, characterized in that in, The increase in the magnitude of the feedback current causes a decrease in the duty cycle, and Therein, the reduction in the magnitude of the feedback current causes the duty cycle to increase.

14. The method according to claim 13, characterized in that Generating the ramp signal includes: When the feedback current increases, the slope of the ramp signal decreases, and When the feedback current decreases, the slope of the ramp signal increases.

15. The method according to claim 13, characterized in that Generating the ramp signal includes: generating a reference current having a predetermined value; generating a charging current, the magnitude of the charging current corresponding to the magnitude of the feedback current subtracted from the reference current; and The ramp signal is generated by charging a ramp capacitor with the charging current and discharging the ramp capacitor at the beginning of each cycle of the clock signal of the SMPS.

16. The method according to claim 15, characterized in that The ramp capacitor is discharged at the beginning of each cycle of the clock signal The method comprises: responding to the edge of the clock signal, turning on a discharge switch coupled to both ends of the ramp capacitor for a preset interval.

17. The method according to claim 15, characterized in that Discharging the ramp capacitor at the beginning of each cycle of the clock signal includes: In response to the edge of the clock signal, a discharge switch coupled to both ends of the ramp capacitor is turned on, and In response to the ramp signal being less than or equal to a preset ramp low voltage, the discharge switch is closed.

18. The method according to claim 13, characterized in that Generating the ramp signal includes controlling a cycle time of the ramp signal according to the feedback current.

19. The method of claim 13, wherein: Generating the ramp signal includes: generating a feedback voltage corresponding to the feedback current; generating a reference current having a predetermined value; generating the ramp signal by charging a capacitor using the reference current; and In response to the ramp signal being greater than the feedback voltage, the capacitor is discharged.

20. The method of claim 13, wherein: Using the ramp signal to control the duty cycle of the power switch includes: determining an error signal having a voltage corresponding to a difference between an output voltage provided by the SMPS to the load and a reference voltage; comparing the error signal with the ramp signal to generate a phase control signal; The duty cycle of the power switch is controlled by the phase control signal.

Images