Level shifter circuit
By introducing delay circuit, pulse generator and latch circuit into the level shifter circuit, and using logic AND circuit and switch to generate extremely short pulse signals, the problems of high quiescent current and slow transition speed in the prior art are solved, and the problem of high quiescent current and slow transition speed is realized. The balance of low quiescent current and rapid transition reduces static power loss.
Patent Information
- Application Number
- CN202410921014.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-11
- Filing Date
- 2024-07-10
- Publication Date
- 2025-01-14
AI Technical Summary
Existing level shifters require high quiescent current during rapid signal transition, resulting in quiescent power loss and it is difficult to achieve a balance between low quiescent current and fast output signal transition.
A level shifter circuit is designed, including an input port, an output port, a delay circuit, a pulse generator and a latch circuit. Through the combination of logic AND circuits and switches, a very short pulse signal is generated to reduce quiescent current consumption, and Increase the speed of the output signal during the input signal transition.
Reducing quiescent current consumption in the microampere range while maintaining faster level shift signal transitions, significantly reducing static power loss and minimizing quiescent current during non-transition.
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Figure CN119315977A_ABST
Abstract
Description
Technical Field
[0001] The present description relates to systems, methods, devices, apparatus, articles of manufacture, and instructions for level shifting a voltage. Background Art
[0002] Level shifters are frequently used circuits in many modern electronic circuits. Applications include translating signals between various communication domains and driver circuits. Typically, level shifters are required to drive high voltage devices (e.g., 15-20V) using much lower voltage input signals (e.g., 2.5-5.5V). But such circuits are also increasingly required to have extremely low quiescent (e.g., standby, static, etc.) currents during periods when there are no signal transitions.
[0003] Many level shifters use a constant bias current for pulling down and pulling up their high voltage output signals. However, there is often a tension between low quiescent current and fast output signal transition times (eg, shorter propagation delays), with faster transitions requiring higher quiescent current.
[0004] Gate driver level shifters in particular may consume large quiescent currents (eg, in the milliamp range), which results in significant quiescent power losses. However, modern electrical devices are increasingly required to have lower quiescent currents, greater light load efficiency, and smaller propagation delays. Summary of the invention
[0005] According to an example embodiment, a level shifter circuit includes: an input port configured to receive an input signal (IN); an output port configured to transmit an output signal (OUT); a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal; and a latch circuit coupled to the pulse generator and configured to generate and maintain a state of the output signal in response to the pulse signal.
[0006] In another example embodiment, a pulse generator is coupled to the input port and is configured to generate a pulse signal in response to a rising edge or a falling edge of the input signal.
[0007] In another example embodiment, the state of the output signal is the first state in response to a rising edge of the input signal; and the state of the output signal is the second state in response to a falling edge of the input signal.
[0008] In another example embodiment, the pulse generator includes a switch (MN_IN) coupled to a logic AND circuit.
[0009] In another example embodiment, the switch is configured to send a pulse signal to the latch circuit in response to a control signal from a logic AND circuit.
[0010] In another example embodiment, the logical AND circuit is configured to generate the control signal if both the input signal and the delayed input signal have the same signal state.
[0011] In another example embodiment, the logic AND circuit and the switch are configured to generate a pulse signal in response to a rising edge of the input signal and a rising edge of the delayed input signal.
[0012] In another example embodiment, the logic AND circuit and the switch are configured to generate a pulse signal in response to a falling edge of the input signal and a falling edge of the delayed input signal.
[0013] In another example embodiment, a first instance of the pulse signal sets the state of the output signal from the latch circuit to a first state; and a second instance of the pulse signal sets the state of the output signal from the latch circuit to a second state.
[0014] In another example embodiment, the output signal (OUT) has a higher voltage than the input signal (IN).
[0015] In another example embodiment, a driver circuit includes: the level shifter circuit according to claim 1 embedded in the driver circuit; and an output port is coupled to a load, and an output voltage is configured to activate the load.
[0016] In another example embodiment, a converter circuit is additionally included, the converter circuit being configured to generate a first differential input signal (IN_A) and a second differential input signal (IN_B) from an input signal (IN).
[0017] In another example embodiment, the delay circuit includes a first delay chain configured to generate a first delayed input signal (IN_A_DLY) from a first differential input signal (IN_A); and the delay circuit includes a second delay chain configured to generate a second delayed input signal (IN_B_DLY) from a second differential input signal (IN_B).
[0018] In another example embodiment, the first delay chain and the second delay chain are cross-coupled using NAND gates.
[0019] In another example embodiment, the pulse generator is a first pulse generator coupled to the first delay circuit and configured to generate a first differential latch signal (Xn) from a combination of the first delayed input signal (IN_A_DLY) and the first differential input signal (IN_A).
[0020] In another example embodiment, a second pulse generator is additionally included, which is coupled to the second delay circuit and is configured to generate a second differential latch signal (Xp) from a combination of the second delayed input signal (IN_B_DLY) and the second differential input signal (IN_B).
[0021] In another example embodiment, the latch circuit is a first differential latch circuit coupled to the first and second pulse generators; and the first differential latch circuit is configured to generate and maintain a state of an output signal in response to a first differential latch signal (Xn) and a second differential latch signal (Xp).
[0022] In another example embodiment, the second differential latch circuit is configured to generate and maintain a state of an output signal in response to a differential signal output from the first differential latch circuit; and the third differential latch circuit is configured to generate and maintain a state of an output signal in response to a differential signal output from the second differential latch circuit.
[0023] In another example embodiment, a first clamp circuit coupled to the first pulse generator and a second clamp circuit coupled to the second pulse generator are further included; wherein the first and second clamp circuits are configured to keep the first differential latch signal (Xn) and the second differential latch signal (Xp) above a minimum signal voltage.
[0024] The above discussion is not intended to represent every example embodiment or every implementation within the scope of current or future claim sets.The figures and the following detailed description also illustrate various example embodiments.
[0025] Various example embodiments may be more fully understood by considering the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A first example of a level shifter circuit is shown.
[0027] Figure 2A , 2B and 2C A second example of the level shifter circuit is shown.
[0028] Although the present disclosure allows various modifications and alternative forms, the details have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments beyond the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed. DETAILED DESCRIPTION
[0029] Example embodiments of a level shifter having substantially reduced quiescent (eg, standby, static, etc.) current consumption (eg, in the micro-ampere range) while still achieving relatively fast level-shifted signal transitions are now discussed.
[0030] Figure 1 A first example of a level shifter circuit is shown 100. The first example level shifter circuit 100 includes an input port 102 for receiving an input signal (IN), an output port 104 for transmitting an output signal (OUT), a delay circuit 106, a pulse generator 108, and a latch circuit 112.
[0031] The delay circuit 106 is configured to generate a delayed input signal bar (IN_DLY_BAR) from an input signal (IN).
[0032] The combination of the pulse generator 108 and the delay circuit 106 is configured to generate an extremely short-lived latch signal (X) from the input signal (IN), which has the effect of substantially reducing static power consumption and current from the pulse generator 108 and therefore also from the first example level shifter circuit 100.
[0033] This example embodiment of the pulse generator 108 includes a logic AND circuit 110 and a switch MN_IN. The logic AND circuit 110 enables the rising and falling edges of the combination of the input signal (IN) and the delayed input signal (IN_DLY) to generate a very short pulse (IN_PULSE). The IN_PULSE signal will turn on the switch MN_IN, which then becomes a very short-term latch signal (X).
[0034] The pulse generator 108 is coupled to the input port 102 and is configured to generate a very short pulse signal in response to a rising edge or a falling edge of the input signal (IN). The switch MN_IN is configured to generate a very short latch signal (X) sent to the latch circuit 112 in response to an IN_PULSE signal (e.g., a control signal) from a logic AND circuit.
[0035] The logic AND circuit 110 is configured to generate an IN_PULSE signal when both the input signal (IN) and the delayed input signal (IN_DLY) have the same signal state. For example, the logic AND circuit and the switch are configured to generate a very short pulse (IN_PULSE) in response to the rising edge of the input signal and the rising edge of the delayed input signal. The logic AND circuit 110 and the switch are also configured to generate a very short pulse (IN_PULSE) in response to the falling edge of the input signal and the falling edge of the delayed input signal.
[0036] The latch circuit 112 is coupled to the pulse generator 108 and is configured to generate and hold the state of the output signal (OUT) in response to a very short pulse of a latch signal (X). A first instance of the very short pulse of the latch signal (X) sets the state of the output signal from the latch circuit 112 to a first state, and a second instance of the very short pulse of the latch signal (X) sets the state of the output signal from the latch circuit 112 to a second state.
[0037] The example embodiment of the level shifter 100 consumes a larger current only during the input signal (IN) transition and thus reduces the static pull-down current at rest, regardless of the input voltage, output voltage, and operating speed of the level shifter 100 .
[0038] Figure 2A , 2B and 2C A second example of a level shifter circuit 200 is shown. The second example level shifter circuit 200 includes an input port 202 for receiving an input signal (IN), an output port 204 for transmitting an output signal (OUT), an inverter circuit 206, a delay circuit 208, a first pulse generator 218, a second pulse generator 222, a first latch circuit 226, a second latch circuit 230, a third latch circuit 234, a first clamp low circuit 236, and a second clamp low circuit 238.
[0039] The inverter circuit 206 is configured to generate a first differential input signal (IN_A) and a second differential input signal (IN_B) from an input signal (IN). This example embodiment of the inverter circuit 206 generates IN_B as the input signal (IN) through an inverter, and IN_A as the input signal (IN) through a buffer including two inverters. Those skilled in the art will appreciate other example embodiments of the inverter circuit 206 that can also generate IN_A and IN_B from the input signal (IN).
[0040] Delay circuit 208 includes a first delay chain configured to generate a first inverted delayed input bar signal (IN_A_DLY_BAR) from a first differential input signal (IN_A), and a second delay chain configured to generate a second inverted delayed input signal (IN_B_DLY) from a second differential input signal (IN_B).
[0041] In this example embodiment, the first delay chain 210 (IN_A_DLY) includes a set of buffers and a first NAND gate 212. The second delay chain 214 (IN_B_DLY) also includes a set of buffers and a second NAND gate 216.
[0042] The first and second delay chains 210, 214 are cross-coupled via NAND gates 212 and 216. By this method, the number of delay cells can be saved because IN_A_DLY must wait for IN_B_DLY to go high, then go through the delay chain, and then go low. 8 delay cells can be used for the first and second sides.
[0043] Those skilled in the art will appreciate other example embodiments of delay circuit 208 that may also generate IN_A_DLY and IN_B_DLY from IN_B and IN_A.
[0044] The combination of the first and second pulse generators 218, 222 with the inverter circuit 206 and the delay circuit 208 is configured to generate extremely short-lived first and second differential latch signals (Xn / Xp) from the input signal (IN), which has the effect of substantially reducing static power consumption and current from the first and second pulse generators 218, 222 and therefore also from the second example level shifter circuit 200.
[0045] This example embodiment of the first pulse generator 218 includes a first logic AND circuit 220 , a switch MN_INA, a switch MNIB_INA, and a switch MHV_INA.
[0046] The first logic AND circuit 220 enables the rising and falling edges of the combination of the IN_A signal and the IN_A_DLY signal to generate a first very short pulse (IN_A_PULSE). Similarly, the second logic AND circuit 224 enables the rising and falling edges of the combination of the IN_B signal and the IN_B_DLY signal to generate a second very short pulse (IN_B_PULSE).
[0047] The IN_A_PULSE and IN_B_PULSE signals will turn on switch MN_INA and switch MN_INB, respectively, which then become very short-lived first and second differential latch signals (Xn / Xp).
[0048] Switches MHV_INA and MHV_INB gate the first and second differential latch signals (Xn / Xp) controlled by an enable signal (VDD_LV).
[0049] The switch MNIB_INA limits the input bias (IB) current flowing in the first differential latch signal (Xn). The switch MNIB_INB limits the input bias (IB) current flowing in the second differential latch signal (Xp).
[0050] When MN_INA is turned on, the first differential latch signal (Xn) will be pulled to a logic low, and when MN_INA is turned off, the first differential latch signal (Xn) will follow the first latch 226 state. Similarly, when MN_INB is turned on, the second differential latch signal (Xp) will be pulled to a logic low, and when MN_INB is turned off, the second differential latch signal (Xp) will follow the first latch 226 state.
[0051] Those skilled in the art will appreciate other example embodiments of the first and second pulse generators 218, 222 that may also generate the first and second differential latch signals (Xn / Xp) from the first and second very short pulses (IN_A_PULSE) and (IN_B_PULSE).
[0052] The first differential latch signal (Xn) and the second differential latch signal (Xp) are held in stable logic states by the first latch circuit 226 receiving the VDD_HV and VSS_HV voltage domains.
[0053] Once the first differential latch signal (Xn) is pulled down, the second differential latch signal (Xp) will be pulled up by the architecture of the first latch circuit 226 .
[0054] The second differential latch signal (Xp) going high will drive the NMOS switch 228 to pull down the node Yp, which in turn will pull up the node Yn at the second latch circuit 230 .
[0055] Yn will drive the NMOS switch 232 to pull down the node Zn, which in turn will then pull up the node Zp at the third latch circuit 234 .
[0056] The signal Zp then passes through two inverter circuits to become an output signal (OUT) on the output port 204 .
[0057] The second example level shifter 200 includes these three latch circuits 226 , 230 , 234 to increase signal noise immunity, however, in other example embodiments, fewer or greater numbers of latch circuits may be used.
[0058] The first clamp circuit 236 and the second clamp circuit 238 prevent the first differential latch signal (Xn) and the second differential latch signal (Xp) from going below VSS_HV minus a diode voltage drop (0.7V) in response to IN_A_PULSE and IN_B_PULSE signal switching transitions that may cause the respective NMOS parasitic body diodes to turn on.
[0059] Using the above circuits, the quiescent current of the first and second example level shifter circuits 100, 200 is minimized during the steady state period when the input signal (IN) is not transitioning. Many example embodiments of the level shifter 100 have a quiescent current of less than 5uA, which is substantially lower than conventional level shifter / driver circuits. The driver current can be measured via the driver VDD pin or the enable pin.
[0060] Unless a particular order is explicitly stated, the various instructions and / or operational steps discussed in the above figures may be performed in any order. Moreover, those skilled in the art will recognize that although some example instruction sets / steps have been discussed, the material in this specification may be combined in a variety of ways to produce other examples, and should be understood within the context provided in this detailed description.
[0061] In some example embodiments, these instructions / steps are implemented as functions and software instructions. In other embodiments, the instructions can be implemented using logic gates, dedicated chips, firmware, and other hardware forms.
[0062] When instructions are embodied as an executable instruction set in a non-transitory computer-readable or computer-usable medium, these instructions are implemented on a computer or machine programmed with the executable instructions and controlled by the executable instructions. The instructions are loaded to be executed on a processor (e.g., one or more CPUs). The processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components. The (one or more) computer-readable or computer-usable storage medium is considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. The (one or more) non-transitory machine or computer-usable medium as defined herein does not include signals, but such (one or more) media may be able to receive and process information from signals and / or other temporary media.
[0063] It will be readily appreciated that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the detailed description of the various embodiments as represented in the figures is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
[0064] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. The described embodiments should be considered in all respects to be illustrative only and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than by the specific implementation. All changes falling within the equivalent meaning and scope of the claims should be included within their scope.
[0065] Reference throughout this specification to features, advantages, or similar language does not imply that all features and advantages that may be realized using the present invention should be included in any single embodiment of the present invention or in any single embodiment of the present invention. Rather, language referring to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussion of features and advantages and similar language throughout this specification may (but need not necessarily) refer to the same embodiment.
[0066] In addition, the described features, advantages and characteristics of the present invention may be combined in any suitable manner in one or more embodiments. Those skilled in the relevant art will recognize that, in view of the description herein, the present invention may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present invention.
[0067] Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may (but do not necessarily) all refer to the same embodiment.
Claims
1. A level shifter circuit, characterized in that: include: an input port configured to receive an input signal (IN); an output port configured to transmit an output signal (OUT); a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal; as well as A latch circuit is coupled to the pulse generator and is configured to generate and hold a state of the output signal in response to the pulse signal.
2. The level shifter circuit according to claim 1: It is characterized in that The pulse generator is coupled to the input port and is configured to generate a pulse signal in response to a rising edge or a falling edge of the input signal.
3. The level shifter circuit according to claim 1: It is characterized in that The state of the output signal is a first state in response to a rising edge of the input signal; and The state of the output signal is a second state in response to a falling edge of the input signal.
4. The level shifter circuit according to claim 1: It is characterized in that The pulse generator includes a switch (MN_IN) coupled to a logic AND circuit.
5. The level shifter circuit according to claim 4: It is characterized in that The switch is configured to transmit the pulse signal to the latch circuit in response to a control signal from the logical AND circuit.
6. The level shifter circuit according to claim 5: It is characterized in that The logical AND circuit is configured to generate the control signal if both the input signal and the delayed input signal have the same signal state.
7. The level shifter circuit according to claim 4: It is characterized in that The logical AND circuit and the switch are configured to generate the pulse signal in response to a rising edge of the input signal and a rising edge of the delayed input signal.
8. The level shifter circuit according to claim 4: It is characterized in that The logical AND circuit and the switch are configured to generate the pulse signal in response to a falling edge of the input signal and a falling edge of the delayed input signal.
9. The level shifter circuit according to claim 1: It is characterized in that A first instance of the pulse signal sets the state of the output signal from the latch circuit to a first state; and Wherein a second instance of the pulse signal sets the state of the output signal from the latch circuit to a second state.
10. A driver circuit, characterized in that: include: wherein the level shifter circuit according to claim 1 is embedded in the driver circuit; and The output port is coupled to a load, and the output voltage is configured to activate the load.