Method and device for realizing bit synchronization and carrier synchronization of multi-rate multiplexing

Abstract

The invention discloses a method and a device for realizing bit synchronization and carrier synchronization of multi-rate multiplexing, and belongs to the field of short frame burst frequency hopping communication. The device comprises a control module, a sliding correlation module, a phase and frequency discrimination module and a data block storage module. A short pulse structure of'preamble-data block-postamble 'is used as a minimum processing unit, sliding correlation is completed at the positions of the preamble and the postamble through a time division multiplexing single complex multiplier and an adder, corresponding sites of correlation results are differentiated, bit synchronization is completed by selecting large according to a module, and phase discrimination and frequency discrimination are completed by using an optimal difference result. And finally reading the stored data and correcting the phase and the frequency offset. According to the invention, the control module analyzes frame information according to a rate gear, determines the working start and stop moments of each module, and carries out time division multiplexing, addressing and other time sequence and read-write logic control. The method has the advantages of adapting to communication requirements of various communication rates and frame format parameters, and being high in compatibility and low in resource complexity.

Description

Technical Field

[0001] The present invention relates to a method and device for realizing bit synchronization and carrier synchronization of multi-rate multiplexing, which is particularly suitable for multi-rate communication scenarios with multiple business requirements and multiple physical layer frame structure requirements, and belongs to the field of short frame burst frequency hopping communication. Background Art

[0002] In the short-frame burst frequency-hopping communication system, synchronization is a crucial link, which determines whether the valid data can be correctly received and is the guarantee for the normal operation of the entire system.

[0003] The synchronization of the short-frame burst frequency-hopping communication system has two meanings: one is to estimate and correct the starting time of each code element in the continuous code element sequence, so that the clock pulse sequence and the start and end time of the received code element symbol are aligned as much as possible, that is, bit synchronization; the other is to estimate the frequency and phase of each hopping carrier, and generate a local oscillation inside the receiver that is strictly the same frequency and phase as each hopping carrier of the received signal, that is, carrier synchronization.

[0004] In more complex short-frame burst communication scenarios, nodes usually have multiple communication services and different quality of service (QoS) requirements. At the same time, the channel conditions, communication distances and service coverage of different scenarios may also vary greatly. In order to distinguish them, the physical layer of the sender and receiver often agrees on different rate gears and corresponding frame structures to complete the communication. In addition, due to considerations such as volume, weight, power consumption, and cost-effectiveness, the hardware resource complexity of the transceiver carried by the communication node should be as low as possible. Therefore, how to achieve bit synchronization and carrier synchronization with low complexity while being compatible with multiple communication rate gears and corresponding frame structures is of great research significance.

[0005] Existing methods for solving bit synchronization and carrier synchronization can be divided into two categories: Non-Data-Aided (NDA) and Data-Aided (DA), depending on whether additional auxiliary synchronization information is inserted.

[0006] When using the NDA method without inserting additional auxiliary synchronization information, both the carrier information and the bit timing information need to be extracted from the transmitted data itself. Common NDA methods for carrier synchronization include the square ring method and the Costas ring method. Common NDA methods for bit synchronization include the nonlinear transformation synchronization method and the lead / lag gate synchronization method.

[0007] The common feature of the method without additional auxiliary information (NDA) is that it needs to use a loop with a loop filter and a voltage-controlled oscillator to complete synchronization, and the synchronization establishment time is relatively long. However, since the short-frame burst transmission system using frequency hopping spread spectrum is developing in the direction of high hopping speed and large bandwidth, the rapid time variation of the carrier frequency and the group delay fluctuation at different frequency points may cause the loop used for synchronization to fail to converge and stabilize quickly within the specified time, thus failing to meet the performance requirements.

[0008] The data-assisted synchronization method (DA) can insert additional synchronization codes in each hop, provide reliable synchronization sites after the frequency hop, enhance the system's adaptability to frequency changes, and avoid the problem of loop instability that may be caused by the above-mentioned frequency hop. It has become a commonly used synchronization method in short-frame burst frequency hopping communications. Summary of the invention

[0009] In order to overcome the problem that the bit synchronization and carrier synchronization implementation methods in common short frame burst frequency hopping receivers are only applicable to a single communication rate and a fixed frame structure, the purpose of the present invention is to provide a multi-rate multiplexing bit synchronization and carrier synchronization implementation method and device, which takes the short pulse structure of "pre-synchronization code-data block-post-synchronization code" as the minimum processing unit, and adopts a data-assisted synchronization method of inserting synchronization codes to complete the estimation and correction of timing errors, carrier phase and residual frequency deviation, etc., to provide conditions for coherent demodulation and decoding of data.

[0010] The method of the present invention is achieved through the following technical solutions.

[0011] The present invention discloses a method for realizing bit synchronization and carrier synchronization of multi-rate multiplexing, comprising the following steps:

[0012] Step 1: Determine the communication rate; determine the communication rate gear number to be used according to the communication scenario and business requirements, and parse out the corresponding symbol rate R s With bit rate R b ;

[0013] Step 2: Rate matching: According to the symbol rate R in step 1 s With bit rate R b , parse out the corresponding frame information; the frame information includes: the total number of hops N of the data segment h , the number of short pulses per jump N p , the number of symbols per hop L Hop , synchronization code length L P , data block length L D The baseband receive sequence sampling rate f corresponding to the symbol rate s ;

[0014] Then the number of sampling points in one symbol duration is M s =fs / R s , the number of sampling points per hop M Hop =L Hop *f s / R s , the number of sampling points of each data block field M D =L D *f s / R s , the number of sampling points for each synchronization code field M P =L P *f s / R s ; Local synchronization code waveform template M P ×1 vector, represented as:

[0015]

[0016] The superscript T indicates the transpose of the matrix;

[0017] Step 3: Pre-processing: According to the sampling rate f determined in step 2 s Complete low-pass downsampling; according to R s After completing the pre-stage coarse synchronization step of capture and frame synchronization, the I / Q baseband sequence r(n) with coarse frequency offset compensation is obtained, and the starting sampling point number of the jth short pulse of the i-th jump is recorded as The initial values ​​of the subscripts i and j are set to i = 0, j = 0; With initial value The relationship is:

[0018]

[0019] The corresponding timing error is within the duration of one symbol;

[0020] Step 4: Calculate the search range related to the sliding of the preamble field; according to the M determined in step 2 s =f s / R s , the sampling point number obtained in step 3 Determine the start and end range of the sliding correlation: The starting sampling point number of the search is recorded as The end sampling point number is recorded as in represents the floor function;

[0021] Step 5: Conjugate multiply the received baseband sequence r(n) with the local template and arrange the calculation results into a matrix R;

[0022] Will Total Ms The sample values ​​are written into the queue in sequence and added to the first data of the local template. l (0) Conjugate multiplication, the complex multiplication results are arranged in sequence as the first row of the matrix R, denoted as When the queue enters the next state, Sequentially with the second data r in the local template l (1) Conjugate multiplication gives the second row of the matrix R, which is denoted as

[0023] By analogy, in the last state of the queue, Sequentially with r l (M P -1) Conjugate multiplication to obtain the Mth matrix R P , denoted as Get M P Line M s The matrix R of columns;

[0024] Step 6: Corresponding accumulation: accumulate the matrix R obtained in step 5 by column to obtain M s Results for group preamble:

[0025]

[0026] Step 7: Data caching; combined with the M obtained in step 2 P 、M D and the search range associated with the sliding of the preamble field obtained in step 4, caching the received baseband sequence r(n);

[0027] make Indicates the index number of the receiving sequence from which the buffer starts; let Q = M D +M s -1 indicates the total amount of cached data; the cached data is represented as a vector

[0028] Step 8: Calculate the search range related to the sliding of the post-synchronization code field; according to the M determined in step 2 P 、M D And the sliding-related search range of the preamble field obtained in step 4 is used to calculate the sliding-related search range of the postamble field:

[0029] Post-amble field start relative position End related position:

[0030] Step 9: Complete sliding correlation search in the post-synchronization code field; within the post-synchronization code sliding correlation range obtained in step 8, repeat steps 5 and 6, complete conjugate multiplication and accumulation in sequence, and then obtain the sliding correlation result R of the post-synchronization code field. post (k), k=1,2,…,M s ;

[0031] Step 10: Phase difference and select the largest one; take the complex difference of the corresponding positions of the correlation results of the front and back synchronization codes obtained in steps 6 and 9, and then s Take the square modulus of the complex difference results; select the index value corresponding to the maximum value of the square modulus

[0032]

[0033] in(·) * Indicates taking the conjugate of the result; and records the index Corresponding preamble correlation results And the complex difference result

[0034] Step 11: frequency offset estimation and carrier generation;

[0035] Frequency offset estimation results:

[0036]

[0037] Δθ is the phase difference caused by the residual frequency offset; Δt is the time difference between the pre- and post-synchronization codes;

[0038] When using direct frequency synthesis DDS to generate a carrier, The relationship with the corresponding frequency control word FW is as follows:

[0039]

[0040] Therefore, the frequency control word is expressed as:

[0041]

[0042] in is the calculated normalized phase difference, 2 Depth is the storage depth of DDS, M P With M D Calculated in step 2 according to the speed gear;

[0043] According to the frequency control word FW, DDS is used to generate the carrier and take the conjugate to obtain the conjugate carrier.

[0044] Step 12: According to step 10 And the result from step 11 Correct the timing error, initial phase and frequency deviation of the data cached in step seven respectively;

[0045] Timing Error Correction: In the buffered data vector Take out the size of M D ×1 fragment

[0046]

[0047] Initial phase and frequency deviation correction: The data in Perform initial phase and frequency deviation compensation;

[0048] Step 13: Determine the shutdown condition; according to the total number of data segment hops N provided in step 2 h , the number of short pulses per jump N p Determine whether to continue processing:

[0049] The short pulse number j is first incremented by 1, and then the incremented short pulse number j is checked to see if it is equal to N. p ; If not equal to N p , then jump to step 4 to continue processing;

[0050] If it is equal to N p , then check whether the data jump number i is equal to N h -1; if not equal to N h -1, the data jump number i increases by 1, the short pulse number j is reset to zero, and the process jumps to step 4 to continue; if it is equal to N h -1, reset the data hop number i and the short pulse number j to zero, and end the processing; that is, realize the bit synchronization and carrier synchronization of multi-rate multiplexing.

[0051] The present invention discloses a low-complexity multi-rate multiplexing bit synchronization and carrier synchronization device, which is implemented based on the multi-rate bit synchronization and carrier synchronization method. It can avoid resource redundancy caused by simply integrating multiple sets of receiver modules suitable for different communication rates into one set of devices, and greatly reduce resource expenditure while being compatible with multiple rate gears.

[0052] The multi-rate multiplexing bit synchronization and carrier synchronization device manufactured according to the above method comprises a control module, a sliding correlation module, a phase and frequency detection module, and a data block storage module.

[0053] The control module will parse the rate gear sequence number determined according to the communication scenario and business requirements, and parse the symbol rate R of the current communication frame. s , bit rate R bAnd the corresponding frame information; combined with the built-in sampling point counter to control the signal processing flow and timing logic of the entire device;

[0054] The sliding correlation module is responsible for completing the sliding correlation processing of the front and back synchronization code fields, and is mainly composed of a cache queue unit, a local template storage unit, a complex multiplication unit and an accumulation unit;

[0055] The cache queue unit is used to cache received sequence data, and the length of the queue is M. s The control module determines the speed according to the speed gear. When a new sample data is obtained in each sampling period, the queue updates its status and inserts the new data into the end of the queue. The old data that first enters the queue is dequeued, i.e., first in, first out.

[0056] The local template storage unit is used to store the locally generated synchronization code field modulation waveform, and the control module selects the corresponding template according to the rate gear. When the sampling point counter counts to the sliding correlation range of the front and rear synchronization codes, the control module gives a read enable signal according to the rate gear, and reads out a local template waveform data every other sampling cycle; in other cases, the read enable is reset and the read address is reset;

[0057] The complex multiplication unit is used to convert the M s The data is conjugate-multiplied with a certain data read out from the local template storage unit in turn; the complex multiplication unit adopts time division multiplexing mode to reduce resource consumption, and the control module performs timing control according to the rate gear: the interval of queue update data is one sampling cycle, and a total of K = f clk / f s processing clocks, f clk To process the clock frequency; select M s clock cycles, each clock cycle is used as a time slot, and a complex multiplication result is calculated. The single complex multiplier is used in time division multiplexing to complete the M in the queue in turn. s The complex multiplication of the data and the local template is output in the form of a serial data stream;

[0058] The accumulation unit also uses time division multiplexing mode to reduce resource consumption. The control module performs time division multiplexing timing control and accumulation length M according to the rate gear. P Control: Select the sampling period M s clock cycles, each clock cycle is a time slot and marked with the time slot number k = 1, 2, ..., M s , each time slot independently completes the accumulation of a set of complex multiplication results, and finally obtains M s Group accumulation result, corresponding to M s When implementing the accumulator, set Ms A register is used to temporarily store the accumulated intermediate results of each time slot, and its initial value is 0; after each update of the queue, each time slot reads the corresponding register and provides the accumulated intermediate results of different related sites to a port of the complex adder. The M obtained by the complex multiplication unit s The serial data stream of the complex multiplication result is distributed to another port of the complex adder according to the time slot, thereby realizing the time division multiplexing of the complex adder;

[0059] The phase and frequency detection module is responsible for completing the estimation of phase deviation and residual frequency deviation and performing corresponding compensation on the received sequence, and mainly includes a phase difference unit, a mode selection unit and a carrier generation unit;

[0060] The phase difference unit takes out the final results of the accumulation registers at the front and back synchronization codes respectively, and performs corresponding conjugate multiplication to obtain M s The differential result is modulo the large modulus unit and obtains the maximum value; the time slot number corresponding to the maximum value is The correlation results with the preamble segment are recorded, which are used for the correction of timing error and phase deviation respectively; the carrier generation unit uses the Cordic algorithm to obtain the normalized phase difference for the differential result corresponding to the maximum value, and uses a divider to divide it by the number of sampling points M between the correlation sites given by the control module according to the rate gear. P +M D The frequency control word FW is obtained by shift operation, that is, the phase offset caused by the residual frequency deviation of one sampling period, and is given to the DDS to generate the carrier for correction;

[0061] The data block storage module is used to cache valid data that has not been corrected for bit timing error, phase offset and residual frequency offset; the depth design of the data block storage module needs to meet all rate gears (M D +M s -1) the maximum value; when the sampling point number counts to the data block range, the control module gives the data block storage module a write enable signal, each sampling cycle writes a data; after the phase and frequency detection module completes the frequency deviation estimation, according to The read start address is determined, one data is read out per processing clock, and after phase and frequency offset compensation, it is used for subsequent demodulation processing.

[0062] Beneficial effects:

[0063] 1. The present invention discloses a method and device for realizing bit synchronization and carrier synchronization of multi-rate multiplexing, which adopts a data-assisted synchronization method of inserting front and back synchronization codes, and completes bit synchronization and carrier synchronization compatible with different symbol rates, bit rates and corresponding frame structures by setting variable frame information, and can overcome the problem that traditional methods only allow the use of a single communication rate and a fixed frame format.

[0064] 2. The present invention discloses a multi-rate multiplexing bit synchronization and carrier synchronization device, which adopts a physical layer frame structure and synchronization method compatible with multiple rate gears, and uses a control module and a built-in sampling point counter to control the signal processing process, thereby avoiding resource redundancy caused by simply integrating multiple sets of receiver modules suitable for different communication rates into one device. Using a device compatible with multiple rate gears can greatly reduce resource expenditure, thereby reducing system power consumption and saving costs.

[0065] 3. The present invention discloses a multi-rate multiplexing bit synchronization and carrier synchronization device, which uses a first-in-first-out cache queue to cache received data and adopts a time-division multiplexing complex multiplication unit and accumulation unit method. The control module controls the length of the cache queue and the timing of time-division multiplexing according to the rate gear. Only one complex multiplier and complex adder are used to complete the sliding correlation operation of the front and rear synchronization codes of each rate gear, which greatly reduces the hardware resource consumption of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 Schematic diagram of the universal frame structure of each rate gear in the present invention;

[0067] Figure 2 It is a schematic diagram of the processing flow of each module and unit in the device of the present invention;

[0068] Figure 3 It is a schematic diagram of the working of the sliding related modules in the present invention;

[0069] Figure 4 It is a schematic diagram of the operation of the accumulation unit in the sliding-related module of the present invention;

[0070] Figure 5 The timing error of the speed gear 1 in the embodiment of the present invention is -2.25*1 / f s1 The estimated results when

[0071] Figure 6 It is a bar graph of the estimated error under different residual frequency offsets for speed gear 1 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The present invention is described in detail below in conjunction with the embodiments and drawings.

[0073] The module processing clock frequency in this embodiment is f clk For example, if the communication node has three different service types, three different rate gears are required to complete the communication. The general frame structure of the three rate gears is shown in the attached Figure 1 .

[0074] When the communication rate gear number is 1 and 2: the symbol rate of the two is the same, that is, R s1 =R s2 =R s1,2 ; The bit rate is different, that is, R b1 ≠R b2 The sampling rate of the received sequence given to the module is f s1 =f s2 =f s1,2 .

[0075] In communication frame No. 1, the data segment duration is T1 and the number of data segment hops is N. h1 , the total number of symbols per hop L Hop1 =R s1 *T1 / N h1 Each hop includes N p1 short pulses and 1 frequency hopping protection interval: the total number of each short pulse symbol is (2L P1 +L D1 ), including the front and rear synchronization codes P1 Symbols and data blocks L D1 symbols; the length of each frequency hopping protection interval is L G1 The communication frame transmits a total of N valid data. h1 *N p1 *L D1 symbols, assuming the coding rate is γ1, then the bit rate R b1 =γ1*N h1 N p1 L D1 / T1.

[0076] In communication frame No. 2, the data segment duration is T2 and the number of data segment hops is N. h2 , the total number of symbols per hop L Hop2 =R s2 *T2 / N h2 Each hop includes N p2 short pulses and 1 frequency hopping protection interval: the total number of each short pulse symbol is (2L P2 +L D2 ), including the front and rear synchronization codes P2 Symbols and data blocks L D2 symbols; the length of each frequency hopping protection interval is L G2 The communication frame transmits a total of N valid data. h2 *N p2 *L D2 symbols, assuming the coding rate is γ2, then the bit rate R b2 =γ2*N h2 N p2 L D2 / T2.

[0077] When the communication rate gear number is 3: the symbol rate is R s3 , the sampling rate is f s3 .

[0078] In communication frame No. 3, the duration of the data segment is T3, and the number of data segment hops is N. h3 , the total number of symbols per hop L Hop3 =R s3 *T3 / N h3 Each hop includes N p3 short pulses and 1 frequency hopping protection interval: the total number of each short pulse symbol is (2L P3 +L D3 ), including the front and rear synchronization codes P3 Symbols and data blocks L D3 symbols; the length of each frequency hopping protection interval is L G3 The communication frame transmits a total of N valid data. h3 *N p3 *L D3 symbols, and the coding rate is γ3. At this time, the bit rate R b3 =γ3*N h3 N p3 L D3 / T3.

[0079] This embodiment takes the above parameters as an example. Figure 2 As shown, the present embodiment discloses a method for implementing bit synchronization and carrier synchronization of multi-rate multiplexing, and the specific implementation steps are as follows:

[0080] Step 1: Determine the communication rate. Determine the communication rate gear number to be used according to the communication scenario and business requirements, and parse the corresponding symbol rate R according to the gear numbers 1 to 3. s With bit rate R b .

[0081] Step 2: Rate matching: According to R in step 1 s With R b , parse out the corresponding frame information. The frame information includes: the total number of hops N of the data segment h , the number of short pulses per jump N p , the number of symbols per hop L Hop , synchronization code length L P , data block length L D The baseband receive sequence sampling rate f corresponding to the symbol rate s .

[0082] And determine the following parameters based on the above frame information:

[0083] (1) The number of sampling points M within a symbol duration s For speed range 1 to 2, M s =f s1,2 / R s1,2 ; For speed gear 3, M s =f s3 / R s3 .

[0084] (2) Number of sampling points per hop M Hop For speed range 1, M Hop =L Hop1 *f s1,2 / R s1,2 ; For speed gear 2, M Hop =L Hop2 *f s1,2 / R s1,2 ; For speed gear 3, M Hop =L Hop3 *f s3 / R s3 .

[0085] (3) The number of sampling points M for each data block field D For speed range 1, M D =L D1 *f s1,2 / R s1,2 ; For speed gear 2, M D =L D2 *f s1,2 / R s1,2 ; For speed gear 3, M D =L D3 *f s3 / R s3 .

[0086] (4) The number of sampling points M for each synchronization code field P And local synchronization code waveform template Local Templates M P ×1 vector. For rate gear 1, the local template is expressed as

[0087]

[0088] For rate gear 2, the local template is expressed as

[0089]

[0090] For rate gear 3, the local template is expressed as

[0091]

[0092] The superscript T indicates the transpose of the matrix.

[0093] Step 3: Pre-processing: According to the sampling rate f determined in step 2 s Complete low-pass downsampling; according to R s After completing the pre-stage coarse synchronization step of capture and frame synchronization, the I / Q baseband sequence r(n) with coarse frequency offset compensation is obtained, and the starting sampling point number of the jth short pulse of the i-th jump is recorded as The initial values ​​of the subscripts i and j are set to i = 0, j = 0; With initial value The relationship is:

[0094]

[0095] The corresponding timing error is within the duration of one symbol;

[0096] Step 4: Calculate the search range related to the sliding of the preamble field; according to the M determined in step 2 s =f s / R s , the sampling point number obtained in step 3 Determine the start and end range of the sliding correlation: The starting sampling point number of the search is recorded as The end sampling point number is recorded as in represents the floor function;

[0097] Step 5: Conjugate multiply the received baseband sequence r(n) with the local template and arrange the calculation results into a matrix R;

[0098] Will Total M s The sample values ​​are written into the queue in sequence and added to the first data of the local template. l (0) Conjugate multiplication, the complex multiplication results are arranged in sequence as the first row of the matrix R, denoted as When the queue enters the next state, Sequentially with the second data r in the local template l (1) Conjugate multiplication gives the second row of the matrix R, which is denoted as

[0099] By analogy, in the last state of the queue, Sequentially with r l (M P -1) Conjugate multiplication to obtain the Mth matrix R P , denoted as Get M P Line Ms The matrix R of columns;

[0100] Step 6: Corresponding accumulation: accumulate the matrix R obtained in step 5 by column to obtain M s The relevant results of the group preamble correspond to the M s Sampling points:

[0101]

[0102] Step 7: Data caching; combined with the M obtained in step 2 P 、M D and the search range associated with the sliding of the preamble field obtained in step 4, caching the received baseband sequence r(n);

[0103] make Indicates the index number of the receiving sequence from which the buffer starts; let Q = M D +M s -1 indicates the total amount of cached data; the cached data is represented as a vector

[0104] Step 8: Calculate the search range related to the sliding of the post-synchronization code field; according to the M determined in step 2 P 、M D And the sliding-related search range of the preamble field obtained in step 4 is used to calculate the sliding-related search range of the postamble field:

[0105] Post-amble field start relative position End related position:

[0106] Step 9: Complete sliding correlation search in the post-synchronization code field; within the post-synchronization code sliding correlation range obtained in step 8, repeat steps 5 and 6, complete conjugate multiplication and accumulation in sequence, and then obtain the sliding correlation result R of the post-synchronization code field. post (k), k=1,2,…,M s ;

[0107] Step 10: Phase difference and select the largest one; take the complex difference of the corresponding positions of the correlation results of the front and back synchronization codes obtained in steps 6 and 9, and then s Take the square modulus of the complex difference results; select the index value corresponding to the maximum value of the square modulus

[0108]

[0109] in(·) * Indicates taking the conjugate of the result; and records the index Corresponding preamble correlation results And the complex difference result

[0110] Step 11: frequency offset estimation and carrier generation;

[0111] Frequency offset estimation results:

[0112]

[0113] Δθ is the phase difference caused by the residual frequency offset; Δt is the time difference between the pre- and post-synchronization codes;

[0114] When using direct frequency synthesis DDS to generate a carrier, The relationship with the corresponding frequency control word FW is as follows:

[0115]

[0116] Therefore, the frequency control word is expressed as:

[0117]

[0118] in is the calculated normalized phase difference, 2 Depth is the storage depth of DDS, M P With M D Calculated in step 2 according to the speed gear;

[0119] According to the frequency control word FW, DDS is used to generate the carrier and take the conjugate to obtain the conjugate carrier.

[0120] Step 12: According to step 10 And the result from step 11 Correct the timing error, initial phase and frequency deviation of the data cached in step seven respectively;

[0121] Timing Error Correction: In the buffered data vector Take out the size of M D ×1 fragment

[0122]

[0123] Initial phase and frequency deviation correction: The data in Perform initial phase and frequency deviation compensation;

[0124] Step 13: Determine the shutdown condition; according to the total number of data segment hops N provided in step 2 h , the number of short pulses per jump N pDetermine whether to continue processing:

[0125] The short pulse number j is first incremented by 1, and then the incremented short pulse number j is checked to see if it is equal to N. p ; If not equal to N p , then jump to step 4 to continue processing;

[0126] If it is equal to N p , then check whether the data jump number i is equal to N h -1; if not equal to N h -1, the data jump number i increases by 1, the short pulse number j is reset to zero, and the process jumps to step 4 to continue; if it is equal to N h -1, reset the data hop number i and the short pulse number j to zero, and end the processing; that is, realize the bit synchronization and carrier synchronization of multi-rate multiplexing.

[0127] like Figure 5 As shown, the timing error is -2.25*1 / f s1 The actual data segment start time is 2.25*1 / f ahead of the result of the previous rough synchronization estimation. s1 When the bit timing error estimated by this method is -2*1 / f s1 , the error is 0.25*1 / f s1 , reducing the error to within a sampling period and meeting the accuracy requirements of bit synchronization. Figure 6 The frequency results of carrier synchronization estimation under different residual frequency offsets are given, and the estimation error meets the requirements of subsequent demodulation and decoding in the short-frame burst communication system.

[0128] The present embodiment discloses a low-complexity multi-rate multiplexing bit synchronization and carrier synchronization device, which is implemented based on the low-complexity multi-rate bit synchronization and carrier synchronization implementation method. It can avoid resource redundancy caused by simply integrating multiple sets of receiver modules suitable for different communication rates into one device, and can greatly reduce resource expenditure while being compatible with multiple rate gears.

[0129] The multi-rate multiplexing bit synchronization and carrier synchronization device manufactured according to the above method includes a control module, a sliding correlation module, a phase and frequency detection module, and a data block storage module; the device signal processing flow refers to the attached Figure 2 .

[0130] The control module will parse the rate gear sequence number determined according to the communication scenario and business requirements, and parse the symbol rate R of the current communication frame. s , bit rate R b And the corresponding frame information; combined with the built-in sampling point counter to control the signal processing flow and timing logic of the entire device;

[0131] The sliding correlation module is responsible for completing the sliding correlation processing of the front and back synchronization code fields, and is mainly composed of a cache queue unit, a local template storage unit, a complex multiplication unit and an accumulation unit; the working diagram of the sliding correlation module is shown in the attached Figure 3 .

[0132] The cache queue unit is used to cache received sequence data, and the length of the queue is M. s The control module determines the speed according to the speed gear. When a new sample data is obtained in each sampling period, the queue updates its status and inserts the new data into the end of the queue. The old data that first enters the queue is dequeued, i.e., first in, first out.

[0133] The local template storage unit is used to store the locally generated synchronization code field modulation waveform, and the control module selects the corresponding template according to the rate gear. When the sampling point counter counts to the sliding correlation range of the front and rear synchronization codes, the control module gives a read enable signal according to the rate gear, and reads out a local template waveform data every other sampling cycle; in other cases, the read enable is reset and the read address is reset;

[0134] The complex multiplication unit is used to convert the M s The data is conjugate-multiplied with a certain data read out from the local template storage unit in turn; the complex multiplication unit adopts time division multiplexing mode to reduce resource consumption, and the control module performs timing control according to the rate gear: the interval of queue update data is one sampling cycle, and a total of K = f clk / f s processing clocks; select M of them s clock cycles, each clock cycle is used as a time slot, and a complex multiplication result is calculated. The single complex multiplier is used in time division multiplexing to complete the M in the queue in turn. s The complex multiplication of the data and the local template is output in the form of a serial data stream;

[0135] The accumulation unit also uses time division multiplexing mode to reduce resource consumption. The control module performs time division multiplexing timing control and accumulation length M according to the rate gear. P Control: Select the sampling period M s clock cycles, each clock cycle is a time slot and marked with the time slot number k = 1, 2, ..., M s , each time slot independently completes the accumulation of a set of complex multiplication results, and finally obtains M s Group accumulation result, corresponding to M s When implementing the accumulator, set M sA register is used to temporarily store the accumulated intermediate results of each time slot, and its initial value is 0; after each update of the queue, each time slot reads the corresponding register and provides the accumulated intermediate results of different related sites to a port of the complex adder. The M obtained by the complex multiplication unit s The serial data stream of the complex multiplication result is distributed to another port of the complex adder according to the time slot, thereby realizing the time division multiplexing of the complex adder; the working principle of the accumulation unit is referred to in the attached Figure 4 .

[0136] The phase and frequency detection module is responsible for completing the estimation of phase deviation and residual frequency deviation and performing corresponding compensation on the received sequence, and mainly includes a phase difference unit, a mode selection unit and a carrier generation unit;

[0137] The phase difference unit takes out the final results of the accumulation registers at the front and back synchronization codes respectively, and performs corresponding conjugate multiplication to obtain M s The differential result is modulo the large modulus unit and obtains the maximum value; the time slot number corresponding to the maximum value is The correlation results with the preamble segment are recorded, which are used for the correction of timing error and phase deviation respectively; the carrier generation unit uses the Cordic algorithm to obtain the normalized phase difference for the differential result corresponding to the maximum value, and uses a divider to divide it by the number of sampling points M between the correlation sites given by the control module according to the rate gear. P +M D The frequency control word FW is obtained by shift operation, that is, the phase offset caused by the residual frequency deviation of one sampling period, and is given to the DDS to generate the carrier for correction;

[0138] The data block storage module is used to cache valid data that has not been corrected for bit timing error, phase offset and residual frequency offset; the depth design of the data block storage module needs to meet all rate gears (M D +M s -1) the maximum value; when the sampling point number counts to the data block range, the control module gives the data block storage module a write enable signal, each sampling cycle writes a data; after the phase and frequency detection module completes the frequency deviation estimation, according to The read start address is determined, one data is read out per processing clock, and after phase and frequency offset compensation, it is used for subsequent demodulation processing.

[0139] The specific description above further illustrates the purpose, technical solutions and beneficial effects of the invention in detail. It should be understood that the above is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for implementing bit synchronization and carrier synchronization of multi-rate multiplexing, characterized in that: The following steps are included: Step 1: Determine the communication rate; determine the communication rate gear number to be used according to the communication scenario and business requirements, and parse out the corresponding symbol rate R s With bit rate R b ; Step 2: Rate matching: According to the symbol rate R in step 1 s With bit rate R b , parse out the corresponding frame information; the frame information includes the total number of hops N of the data segment h , the number of short pulses per jump N p , the number of symbols per hop L Hop , synchronization code length L P , data block length L D The baseband receive sequence sampling rate f corresponding to the symbol rate s ; Then the number of sampling points in a symbol duration is M s =f s / R s , the number of sampling points per hop M Hop =L Hop *f s / R s , the number of sampling points of each data block field M D =L D *f s / R s , the number of sampling points for each synchronization code field M P =L P *f s / R s ; Local synchronization code waveform template M P ×1 vector, expressed as: The superscript T indicates the transpose of the matrix; Step 3: Pre-processing: According to the sampling rate f determined in step 2 s Complete low-pass downsampling; according to R s After completing the pre-stage coarse synchronization step of capture and frame synchronization, the I / Q baseband sequence r(n) with coarse frequency offset compensation is obtained, and the starting sampling point number of the jth short pulse of the i-th jump is recorded as The initial values ​​of the subscripts i and j are set to i = 0, j = 0; With initial value The relationship is: The corresponding timing error is within the duration of one symbol; Step 4: Calculate the search range related to the sliding of the preamble field; according to the M determined in step 2 s =f s / R s , the sampling point number obtained in step 3 Determine the start and end range of the sliding correlation: The starting sampling point number of the search is recorded as The end sampling point number is recorded as in represents the floor function; Step 5: Conjugate multiply the received baseband sequence r(n) with the local template and arrange the calculation results into a matrix R; Will Total M s The sample values ​​are written into the queue in sequence and added to the first data of the local template. l (0) Conjugate multiplication, the complex multiplication results are arranged in sequence as the first row of the matrix R, denoted as When the queue enters the next state, Sequentially with the second data r in the local template l (1) Conjugate multiplication gives the second row of the matrix R, which is denoted as By analogy, in the last state of the queue, Sequentially with r l (M P -1) Conjugate multiplication to obtain the Mth matrix R P , denoted as Get M P Line M s The matrix R of columns; Step 6: Corresponding accumulation: accumulate the matrix R obtained in step 5 by column to obtain M s Results for group preamble: Step 7: Data caching; combined with the M obtained in step 2 P 、M D and the search range associated with the sliding of the preamble field obtained in step 4, caching the received baseband sequence r(n); make Indicates the index number of the receiving sequence from which the buffer starts; let Q = M D +M s -1 indicates the total amount of cached data; the cached data is represented as a vector Step 8: Calculate the search range related to the sliding of the post-synchronization code field; according to the M determined in step 2 P 、M D And the sliding-related search range of the preamble field obtained in step 4 is used to deduce the sliding-related search range of the postamble field: Post-amble field start relative position End related position: Step 9: Complete sliding correlation search in the post-synchronization code field; within the post-synchronization code sliding correlation range obtained in step 8, repeat steps 5 and 6, complete conjugate multiplication and accumulation in sequence, and then obtain the sliding correlation result R of the post-synchronization code field. post (k), k=1,2,…,M s ; Step 10: Phase difference and select the largest one; take the complex difference of the corresponding positions of the correlation results of the front and back synchronization codes obtained in steps 6 and 9, and then s Take the square modulus of the complex difference results; select the index value corresponding to the maximum value of the square modulus in(·) * Indicates taking the conjugate of the result; and records the index Corresponding preamble correlation results And the complex difference result Step 11: frequency offset estimation and carrier generation; Frequency offset estimation results: Δθ is the phase difference caused by the residual frequency offset; Δt is the time difference between the pre- and post-synchronization codes; When using direct frequency synthesis DDS to generate a carrier, The relationship with the corresponding frequency control word FW is as follows: Therefore, the frequency control word is expressed as: in is the calculated normalized phase difference, 2 Depth is the storage depth of DDS, M P With M D Calculated in step 2 according to the speed gear; According to the frequency control word FW, DDS is used to generate the carrier and take the conjugate to obtain the conjugate carrier. Step 12: According to step 10 And the result from step 11 Correct the timing error, initial phase and frequency deviation of the data cached in step seven respectively; Timing Error Correction: In the buffered data vector Take out the size of M D ×1 fragment Initial phase and frequency offset correction: The data in are multiplied by Perform initial phase and frequency deviation compensation; Step 13: Determine the shutdown conditions; According to the total number of data segment hops N provided in step 2 h , the number of short pulses per jump N p Determine whether to continue processing: The short pulse number j is first incremented by 1, and then the incremented short pulse number j is checked to see if it is equal to N. p ; If not equal to N p , then jump to step 4 to continue processing; If it is equal to N p , then check whether the data jump number i is equal to N h -1; if not equal to N h -1, the data jump number i increases by 1, the short pulse number j is reset to zero, and the process jumps to step 4 to continue; if it is equal to N h -1, reset the data hop number i and the short pulse number j to zero, and end the processing, that is, realize the bit synchronization and carrier synchronization of multi-rate multiplexing.

2. A device for implementing the method as claimed in claim 1, characterized in that: It includes a control module, a sliding correlation module, a phase and frequency discrimination module and a data block storage module; The control module will parse the rate gear sequence number determined according to the communication scenario and business requirements, and parse the symbol rate R of the current communication frame. s , bit rate R b And the corresponding frame information; combined with the built-in sampling point counter to control the signal processing flow and timing logic of the entire device; The sliding correlation module is used to complete the sliding correlation processing of the front and back synchronization code fields, and is mainly composed of a cache queue unit, a local template storage unit, a complex multiplication unit and an accumulation unit; The cache queue unit is used to cache received sequence data, and the length of the queue is M. s The control module determines the speed according to the speed gear. When a new sample data is obtained in each sampling period, the queue updates its status and inserts the new data into the end of the queue. The old data that first enters the queue is dequeued, i.e., first in, first out. The local template storage unit is used to store the locally generated synchronization code field modulation waveform, and the control module selects the corresponding template according to the rate gear. When the sampling point counter counts to the sliding correlation range of the front and rear synchronization codes, the control module gives a read enable signal according to the rate gear, and reads out a local template waveform data every other sampling cycle; in other cases, the read enable is reset and the read address is reset; The complex multiplication unit is used to convert the M s The data is conjugate-multiplied with a certain data read out from the local template storage unit in turn; the complex multiplication unit adopts time division multiplexing mode to reduce resource consumption, and the control module performs timing control according to the rate gear: the interval of queue update data is one sampling cycle, and a total of K = f clk / f s processing clocks, f clk To process the clock frequency; select M s clock cycles, each clock cycle is used as a time slot, and a complex multiplication result is calculated. The single complex multiplier is used in time division multiplexing to complete the M in the queue in turn. s The complex multiplication of the data and the local template is output in the form of a serial data stream; The accumulation unit also uses time division multiplexing mode to reduce resource consumption. The control module performs time division multiplexing timing control and accumulation length M according to the rate gear. P Control: Select the sampling period M s clock cycles, each clock cycle is a time slot and marked with the time slot number k = 1, 2, ..., M s Each time slot independently completes the accumulation of a set of complex multiplication results, and finally obtains M s Group accumulation result, corresponding to M s When implementing the accumulator, set M s A register is used to temporarily store the accumulated intermediate results of each time slot, and its initial value is 0; after each update of the queue, each time slot reads the corresponding register and provides the accumulated intermediate results of different related sites to a port of the complex adder. The M obtained by the complex multiplication unit s The serial data stream of the complex multiplication result is distributed to another port of the complex adder according to the time slot, thereby realizing the time division multiplexing of the complex adder; The phase and frequency detection module is responsible for completing the estimation of phase deviation and residual frequency deviation and performing corresponding compensation on the received sequence, and mainly includes a phase difference unit, a mode selection unit and a carrier generation unit; The phase difference unit takes out the final results of the accumulation registers at the front and back synchronization codes respectively, and performs corresponding conjugate multiplication to obtain M s The differential result is modulo the large modulus unit and obtains the maximum value; the time slot number corresponding to the maximum value is The correlation results with the preamble segment are recorded, which are used for the correction of timing error and phase deviation respectively; the carrier generation unit uses the Cordic algorithm to obtain the normalized phase difference for the differential result corresponding to the maximum value, and uses a divider to divide it by the number of sampling points M between the correlation sites given by the control module according to the rate gear. P +M D The frequency control word FW is obtained by shift operation, that is, the phase offset caused by the residual frequency deviation of one sampling period, and is given to the DDS to generate the carrier for correction; The data block storage module is used to cache valid data that has not been corrected for bit timing error, phase offset and residual frequency offset; the depth design of the data block storage module needs to meet all rate gears (M D +M s -1) The case where the value is the largest; When the sampling point sequence number counts to the data block range, the control module gives the write enable signal of the data block storage module, and writes one data in each sampling cycle; after the phase and frequency detection module completes the frequency deviation estimation, according to The read start address is determined, one data is read out per processing clock, and after phase and frequency offset compensation, it is used for subsequent demodulation processing.

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