Homomorphic encryption heterogeneous processing method, system, device, medium and program product

Abstract

The present invention provides a homomorphic encryption heterogeneous processing method system, electronic device, storage medium and program product, comprising the following steps: homomorphically encrypting target data to form homomorphic encrypted data including a plurality of polynomials, wherein the polynomials include a plurality of zero coefficient terms and non-zero coefficient terms; when executing processing steps for the homomorphic encrypted data, calling a GPU to process a plurality of the non-zero coefficient terms in parallel, and calling a CPU to process the processing steps except for the non-zero coefficient terms. The present invention utilizes the polynomial characteristics generated by homomorphic encryption processing to more effectively allocate tasks to a CPU-GPU heterogeneous architecture.

Description

Technical Field

[0001] The present invention relates to the field of homomorphic encryption technology, and specifically to a homomorphic encryption heterogeneous processing method, system, electronic device, storage medium and program product. Background Art

[0002] Fully Homomorphic Encryption (FHE) technology is an encryption method that can perform arithmetic operations directly on encrypted data. Its biggest advantage is that it can complete calculation operations without decrypting the data, thus providing a powerful tool for data privacy protection. However, existing fully homomorphic encryption processing methods have many limitations in computational complexity and performance, especially when calculating polynomial operators, the computational overhead is huge, which seriously affects its practicality. The existing FPGA, ASIC and GPU acceleration solutions have their own advantages and disadvantages, but none of them can effectively solve the following problems:

[0003] Computational overhead of polynomial calculations: Fully homomorphic encryption involves a large number of polynomial operations, such as polynomial addition, multiplication, and modular operations. Traditional FPGA, ASIC, and GPU solutions cannot efficiently handle these operations.

[0004] Development complexity and flexibility: FPGA and ASIC have complex designs and long development cycles, and their flexibility and scalability are limited, making them unable to adapt to data encryption tasks of different scales.

[0005] GPU acceleration adaptability and energy efficiency issues: GPUs are good at parallel computing, but they are not fully adapted to fully homomorphic encryption algorithms, resulting in low resource utilization. At the same time, during high-intensity computing, power consumption and heat dissipation requirements are high.

[0006] High development cost: The development of ASIC requires high design and manufacturing costs, and has a long development cycle, and is only suitable for application scenarios with large-scale, long-term fixed tasks.

[0007] Poor flexibility: Since ASIC is designed for specific tasks, it is difficult to adapt to changing application requirements and cannot be flexibly adjusted for different fully homomorphic encryption algorithms or different data sizes.

[0008] Difficult to update: Once the ASIC design is completed, it is difficult to upgrade or modify, which means that once the encryption algorithm changes, the ASIC may need to be redesigned and manufactured.

[0009] Therefore, a new efficient fully homomorphic encryption processing technology solution based on CPU-GPU heterogeneous architecture is needed to solve the above technical problems. Summary of the invention

[0010] The purpose of the present invention is to provide a homomorphic encryption heterogeneous processing method, system, electronic device, storage medium and program product. The polynomial characteristics generated by homomorphic encryption processing are used to more effectively allocate tasks to the CPU-GPU heterogeneous architecture.

[0011] To achieve the above-mentioned purpose, the present invention provides a homomorphic encryption heterogeneous processing method, comprising the following steps: homomorphically encrypting the target data to form homomorphically encrypted data including a plurality of polynomials, wherein the polynomials include a plurality of zero coefficient terms and non-zero coefficient terms; when executing processing steps on the homomorphic encrypted data, calling the GPU to process a plurality of the non-zero coefficient terms in parallel, and calling the CPU to process the processing steps except for the non-zero coefficient terms.

[0012] Optionally, before executing the processing step on the homomorphically encrypted data, the non-zero coefficient items are extracted and stored in an independent storage space for retrieval by the GPU.

[0013] Optionally, the GPU has multiple threads, each thread is used to process the non-zero coefficient items with the same exponent.

[0014] Optionally, the polynomial is divided into a plurality of term groups, and coefficients of each term of each term group are extracted; and based on the coefficients of each term of each term group, an index is established for access by the GPU.

[0015] Optionally, the index is established based on the coefficients of each item in each item group for access by the GPU, specifically including: for each item group, a coefficient matrix is ​​established based on the coefficients of each item in the item group, the coefficient matrix has a mapping relationship with the corresponding ciphertext block, and an index is established for access by the GPU according to the mapping relationship.

[0016] Optionally, if the load of one of the CPU and the GPU exceeds a preset threshold, part of the processing steps is transferred to the other of the CPU and the GPU for processing.

[0017] The present invention also provides a homomorphic encryption heterogeneous processing system, comprising: an encryption module, used to homomorphically encrypt target data to form homomorphic encrypted data including a plurality of polynomials, wherein the polynomials include a plurality of zero coefficient terms and non-zero coefficient terms; a calling module, used to call a GPU to process a plurality of the non-zero coefficient terms in parallel, and call a CPU to process the processing steps except for the non-zero coefficient terms when executing processing steps for the homomorphic encrypted data.

[0018] The present invention also provides an electronic device, comprising: a memory storing a computer program; a processor communicatively connected to the memory, for executing any one of the above-mentioned homomorphic encryption heterogeneous processing methods when the computer program is called; and a display communicatively connected to the processor and the memory, for displaying a GUI interactive interface related to the homomorphic encryption heterogeneous processing method.

[0019] To achieve the above objectives, the present invention also provides a readable storage medium storing a computer program, which, when executed by a processor, implements any of the above-mentioned homomorphic encryption heterogeneous processing methods.

[0020] To achieve the above objectives, the present invention also provides a computer program product, which, when executed by a processor, implements the homomorphic encryption heterogeneous processing method described in any one of the above items.

[0021] The homomorphic encryption heterogeneous processing method, system, electronic device, storage medium and program product provided by the present invention have the following beneficial effects:

[0022] The present invention provides a homomorphic encryption heterogeneous processing method, comprising the following steps: homomorphically encrypting target data to form homomorphic encrypted data including several polynomials, wherein the polynomials include several zero coefficient terms and non-zero coefficient terms; when executing processing steps for the homomorphic encrypted data, calling a GPU to process multiple non-zero coefficient terms in parallel, and calling a CPU to process the processing steps except for the non-zero coefficient terms. Under the framework of homomorphic encryption technology, encrypted data will be converted into several polynomials, and non-zero coefficient terms and zero coefficient terms will appear in these polynomials. The difference from conventional polynomial operations is that in the logic of homomorphic encryption, zero coefficient terms must be represented and cannot be directly regarded as zero to eliminate, but this part of zero coefficient terms is indeed essentially zero from a mathematical point of view, and this detail is often overlooked in the prior art. If all these terms are directly handed over to the GPU for parallel processing, it will inevitably lead to redundant calculations, resulting in computational waste and increasing the burden on the GPU. Therefore, this application starts from the characteristics of the polynomial itself generated by homomorphic encryption, and uses the polynomial characteristics generated by homomorphic encryption processing to more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0023] The present invention also provides a homomorphic encryption heterogeneous processing system, which is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods. Therefore, the homomorphic encryption heterogeneous processing system can start from the characteristics of the polynomials generated by homomorphic encryption, and use the polynomial characteristics generated by homomorphic encryption processing to more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0024] The present invention also provides an electronic device, which is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods. Therefore, the electronic device can start from the characteristics of the polynomial itself generated by homomorphic encryption, and use the polynomial characteristics generated by homomorphic encryption processing to more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0025] The present invention also provides a readable storage medium, and since the readable storage medium is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods, the readable storage medium can start from the characteristics of the polynomial itself generated by homomorphic encryption, and use the polynomial characteristics generated by homomorphic encryption processing to more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0026] The present invention also provides a computer program product, which is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods. Therefore, the computer program product can start from the characteristics of the polynomial itself generated by homomorphic encryption, use the polynomial characteristics generated by homomorphic encryption processing, and more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby realizing efficient and low-power homomorphic encryption processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A flowchart of a homomorphic encryption heterogeneous processing method provided in one embodiment of the present invention.

[0028] Figure 2 A schematic diagram of the block structure of an electronic device provided by an embodiment of the present invention.

[0029] The accompanying drawings are denoted as follows:

[0030] 101 - processor; 102 - communication interface; 103 - memory; 104 - communication bus; 105 - display. DETAILED DESCRIPTION

[0031] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0032] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in addition (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "include" is used to determine the presence of features, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] The purpose of the present invention is to provide a homomorphic encryption heterogeneous processing method, system, electronic device, storage medium and program product. The polynomial characteristics generated by homomorphic encryption processing are used to more effectively allocate tasks to the CPU-GPU heterogeneous architecture.

[0034] To achieve the above purpose, the present invention provides a homomorphic encryption heterogeneous processing method, please refer to Figure 1 , Figure 1 The following is a flow chart of a homomorphic encryption heterogeneous processing method provided by an embodiment of the present invention. Figure 1As shown, the present invention includes the following steps: homomorphically encrypting the target data to form homomorphically encrypted data including several polynomials, wherein the polynomials include several zero coefficient terms and non-zero coefficient terms; when executing processing steps for the homomorphically encrypted data, calling the GPU to process multiple non-zero coefficient terms in parallel, and calling the CPU to process the processing steps except for the non-zero coefficient terms. It should be noted that the target data includes but is not limited to graphic data, and the present invention can be applied to data in any form or format.

[0035] Under the framework of homomorphic encryption technology, encrypted data will be converted into several polynomials, and non-zero coefficient terms and zero coefficient terms will appear in these polynomials. The difference from conventional polynomial operations is that in the logic of homomorphic encryption, zero coefficient terms must be represented and cannot be directly regarded as zero to eliminate, but this part of zero coefficient terms is indeed essentially zero from a mathematical point of view, and this detail is often overlooked in the prior art. If all these items are directly handed over to the GPU for parallel processing, it will inevitably lead to redundant calculations, resulting in computational waste and increasing the burden on the GPU. Therefore, this application starts with the characteristics of the polynomials generated by homomorphic encryption itself, and uses the characteristics of the polynomials generated by homomorphic encryption processing to more effectively assign tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0036] GPU (Graphics Processing Unit) is a dedicated highly parallel processor originally designed for fast and efficient rendering of graphics, images and video content. Unlike traditional general-purpose CPUs, GPUs use a massively parallel hardware architecture that can execute thousands of threads simultaneously, greatly improving the capabilities of graphics rendering and data parallel computing. Initially, the functions of GPUs were relatively simple, focusing mainly on the rendering of graphics images. However, over time, the GPU hardware and software ecosystem has continued to develop, its programmability and flexibility have become stronger, and its application areas have continued to expand. Just as the application of GPUs in neural networks, blockchain computing, and artificial intelligence large model training, although these applications are based on the parallel processing capabilities of GPUs, they have achieved unexpected technical effects based on different scenarios and algorithms. This application also starts with the characteristics of the polynomials generated by homomorphic encryption, utilizes the polynomial characteristics generated by homomorphic encryption processing, and effectively combines the application of CPUs to achieve more efficient allocation of tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0037] At the system architecture level, a task scheduling module can be set up to intelligently allocate computing tasks between the CPU and GPU. Task allocation is adjusted in real time according to the complexity of the current task and the system load. Using a dynamic scheduling algorithm, high-concurrency tasks are allocated to the GPU, and complex control tasks are handed over to the CPU for execution. Different from the static task allocation in the prior art, this module effectively improves the utilization of system resources and avoids task blocking and resource idleness.

[0038] Furthermore, a polynomial operation acceleration module can be set up, which is responsible for performing optimized polynomial addition, multiplication and modular operations on the GPU. By designing a parallel algorithm adapted to the GPU architecture, the parallel computing advantages of polynomial addition and multiplication are maximized. In particular, in polynomial multiplication, the fast Fourier transform (FFT) optimization algorithm is used to significantly reduce the time complexity and greatly improve the operation speed. In order to further improve the operation efficiency and reduce the waste of computing resources, especially in the case of a large number of zero coefficients in the sparse polynomials commonly used in homomorphic encryption operations, this module uses a sparse storage scheme (the detailed design is described in the data management module) to accelerate the calculation process. Under this scheme, the GPU only calculates non-zero coefficients, avoiding redundant zero coefficient calculations, thereby improving the operation speed.

[0039] Furthermore, a data management module can be set up. In this system, the ciphertext polynomial data structure adopts a hierarchical storage strategy to store the encryption coefficients and non-encrypted metadata separately. The specific design is as follows:

[0040] Encrypted coefficient storage layer: This layer is dedicated to storing encrypted coefficient data, using GPU-efficient parallel access for storage and optimizing the memory layout suitable for the GPU architecture (such as using shared memory and texture memory) for fast access and processing.

[0041] Unencrypted metadata storage layer: This layer contains the unencrypted metadata of the polynomial, such as index information, block information, coefficient position, etc. This part is stored in the CPU-side memory, using an optimized memory access strategy to reduce memory usage and ensure that the GPU can access these metadata through an efficient interface.

[0042] Loading and Transferring: The data management module is responsible for loading the encrypted coefficients from the main storage medium to the GPU memory and ensuring the parallel execution between the loading and calculation operations of the encrypted coefficients through double buffer technology.

[0043] Scheduling of metadata and encryption coefficients: On the CPU side, based on a dynamic scheduling algorithm, the loading and allocation of metadata and encryption coefficients are managed to ensure seamless connection between the CPU and the GPU's parallel computing tasks when processing metadata.

[0044] In order to maximize the system throughput, the data management module adopts the following optimization measures to reduce data transmission delay:

[0045] Double buffer technology: Using double buffer technology, one buffer is allocated for data calculation and processing during data transmission, and the other buffer is used for data loading and storage. In this way, the GPU can process the data in one buffer while the CPU can continue to load the next data block, thus reducing waiting time.

[0046] Asynchronous data transmission: Using the asynchronous data transmission mechanism, ensure that the data exchange between the CPU and GPU does not become a computing bottleneck. Through background transmission, the system can perform calculations and data transmission at the same time, ensuring efficient cooperation between the two.

[0047] In terms of the specific calculation process, first, non-zero coefficients are extracted. Before the polynomial addition, multiplication and modular operations begin, the non-zero coefficients of each polynomial are first extracted from the sparse storage. Due to the adoption of a block storage scheme, the GPU can directly load the memory blocks storing non-zero coefficients, avoiding the loading and processing of invalid data containing zero coefficients. This process ensures that calculations are performed only on valid data, minimizing memory bandwidth consumption. Based on this, the present invention further provides the following technical solution: before executing the processing step for the homomorphic encrypted data, the non-zero coefficient items are extracted and stored in an independent storage space for the GPU to retrieve.

[0048] Furthermore, the GPU has multiple threads, each of which is used to process the non-zero coefficient terms with the same exponent. When performing addition on the GPU, each thread is only responsible for calculating the sum of the non-zero coefficients at the same exponent position in the two polynomials. Since the zero coefficients have been ignored, only calculations involving non-zero coefficients will be performed, further improving the parallelism and efficiency of the calculations. All addition operations are performed directly in the GPU memory, greatly reducing the data exchange delay between the CPU and the GPU.

[0049] When performing polynomial multiplication, the GPU uses fast Fourier transform (FFT) to efficiently calculate non-zero coefficients. FFT converts the polynomial multiplication problem into point value operations and processes them efficiently in the frequency domain. Since most coefficients in the polynomial are zero, the GPU only processes the point values ​​corresponding to those non-zero coefficients. The FFT optimization algorithm significantly reduces the computational complexity and avoids invalid calculations of zero coefficients, thereby increasing the computational speed.

[0050] For polynomial modular operations, the use of sparse storage solutions also plays an important role. The GPU only performs modular operations on polynomials containing non-zero coefficients, ignoring the zero coefficients, reducing unnecessary calculations. When performing modular operations, the GPU only needs to process the non-zero part related to the modulus, avoiding the repeated calculation of invalid data in traditional methods and improving the calculation efficiency.

[0051] For sparse polynomials, many of the coefficients are zero. Especially in homomorphic encryption operations, there are usually a large number of zero coefficients. To address this situation, this solution designs a special sparse polynomial block storage solution:

[0052] Block storage structure: The ciphertext polynomial is divided into multiple blocks, each containing multiple coefficients. When storing, only the non-zero coefficients are stored in the memory, and an index is created for each non-zero coefficient. This allows the GPU to only load and calculate the non-zero coefficients during processing, greatly reducing redundant calculations.

[0053] Non-zero coefficient processing: The storage location of non-zero coefficients and their corresponding exponents are managed through a compressed storage structure (CSR format of sparse matrices). This design allows the GPU to quickly find non-zero coefficients during calculations and perform calculations through GPU-optimized parallel algorithms, significantly improving calculation efficiency.

[0054] Sparse matrix and ciphertext block mapping: Each non-zero coefficient block has a corresponding sparse matrix that records its position, value, and mapping information of the ciphertext block. The GPU uses this mapping to directly access the coefficients that need to be calculated, avoiding the processing of zero coefficients.

[0055] Based on this, the present invention further provides the following technical solution: the polynomial is divided into multiple item groups, and the coefficients of each item of each item group are extracted; based on the coefficients of each item of each item group, an index is established for the GPU to access. Specifically, the index is established for the GPU to access based on the coefficients of each item of each item group, which specifically includes: for each item group, based on the coefficients of each item of the item group, a coefficient matrix is ​​established, the coefficient matrix has a mapping relationship with the corresponding ciphertext block, and the index is established for the GPU to access according to the mapping relationship.

[0056] Furthermore, a computing coordination module may be provided, and the execution of the computing coordination module follows the following logic: if the load of one of the CPU and the GPU exceeds a preset threshold, part of the processing steps is transferred to the other of the CPU and the GPU for processing. The computing coordination module is responsible for coordinating the computing tasks between the CPU and the GPU to ensure smooth connection between the two.

[0057] When the system starts, the computing coordination module first identifies the tasks to be processed and makes preliminary allocations based on the nature of the tasks. Complex control tasks (such as key generation and data scheduling) will be assigned to the CPU for execution, while computationally intensive tasks (such as polynomial addition and multiplication) will be assigned to the GPU.

[0058] The computation coordination module monitors the progress of task execution in real time. The working status of the CPU and GPU is continuously tracked, including computation progress, task queue, computation load, memory usage, etc. When the task is in progress, the module regularly collects hardware load information, evaluates the resource usage of each device, and makes adjustments as needed.

[0059] If monitoring finds that a device (CPU or GPU) is overloaded or the computing progress is significantly delayed, the computing coordination module will dynamically adjust the task allocation. If the GPU load is too high, some tasks will be rescheduled to the CPU for execution; conversely, if the CPU load is too high, the remaining tasks will be reassigned to the GPU.

[0060] When tasks are backlogged or delayed during execution, the computational coordination module adjusts the execution order of the task queue. Tasks with higher priorities are executed first, while lower priority tasks may be delayed to avoid excessive use of system resources.

[0061] The computation coordination module ensures that the CPU and GPU can seamlessly connect during task execution. When the GPU computation is completed, the CPU immediately begins post-processing or further scheduling of the computation results. Through precise resource scheduling and task synchronization, idle waiting and resource idleness between tasks can be avoided.

[0062] The module adjusts task allocation based on real-time feedback information. After the task is completed, the computation coordination module will evaluate the subsequent computation load based on the computation progress of the results, and adjust the resource allocation ratio based on the expected computation time to ensure the balance of CPU and GPU computation tasks and maximize system performance.

[0063] Furthermore, a result integration module may be provided, which is responsible for merging the calculation results of the CPU and GPU and outputting the final encrypted calculation results. After the CPU and GPU complete their respective calculation tasks, the result integration module extracts the calculation results from the two devices. The results of the GPU calculation are stored in the GPU memory, and the results of the CPU calculation are stored in the CPU memory. The module extracts the results from their respective memories to ensure the integrity and consistency of the data. Since the calculations of the GPU and the CPU are performed in parallel, the result integration module needs to align the calculation results from the CPU and the GPU in the correct order. First, the module sorts the results of each task according to the information of task division. If there is a sequence dependency between the calculation results, the module ensures that the order is consistent to avoid errors during merging. For each calculation result, the calculation coordination module checks the integrity of the ciphertext and merges the ciphertext parts from the CPU and the GPU according to the encryption protocol. If the results calculated by the two devices are different parts of the ciphertext polynomial, the module combines them into a complete ciphertext to ensure that all relevant data are correctly integrated. The merged ciphertext will be verified through the encryption protocol to ensure that the merged result is not damaged. The module verifies the correctness of the ciphertext by performing an integrity check on the encryption result. This can be verified by calculating the hash value or checksum of the ciphertext to ensure that the calculation results returned from the CPU and GPU are consistent and correct. If the final output is a plaintext result, the module will perform a decryption operation. According to the decryption protocol of fully homomorphic encryption, the result integration module decrypts the combined ciphertext to obtain the plaintext result. The decrypted result will be formatted to ensure that the output meets the predetermined format requirements. For example, the ciphertext result will be returned directly to the user or system, and the decrypted plaintext result will be provided for further processing or storage according to the application scenario. Before the final output, the module will verify the decrypted plaintext result to ensure that there are no errors in the decryption process and that the result meets the expected calculation goal. If the decryption result does not meet the expectation, the module will trigger the error handling mechanism and return a calculation error prompt to prevent the erroneous result from entering the application layer.

[0064] In the present invention, different types of polynomial operations are reasonably allocated to the CPU and GPU to achieve optimal computing efficiency:

[0065] Polynomial addition: High degree of parallelism, suitable for execution on GPU. GPU uses its large number of parallel computing cores to process multiple addition operations simultaneously, speeding up the calculation.

[0066] Polynomial multiplication: The computational complexity is high and it is suitable for execution on GPU. The FFT-optimized polynomial multiplication algorithm significantly reduces the computational time.

[0067] Polynomial modular operations: With a high degree of parallelization, GPU can process modular operations of multiple data blocks through parallel computing, thus accelerating the entire encryption process.

[0068] Large number and complex control operations: Involving conditional judgment and serial processing, they are suitable for processing on the CPU, making full use of the CPU's efficient control logic and complex operation processing capabilities to give full play to its advantages.

[0069] The present invention is significantly different from the prior art in the following aspects and brings many beneficial effects:

[0070] Intelligent task scheduling: Different from the existing static task allocation method, the intelligent scheduling algorithm dynamically adjusts task allocation according to the real-time task load, improving the resource utilization of the system.

[0071] Algorithm optimization: We designed parallel algorithms that are adapted to the GPU architecture for polynomial operations, such as FFT-optimized polynomial multiplication operations, which greatly improved the computing speed and broke through the efficiency bottleneck under large amounts of data.

[0072] Energy efficiency optimization: Through heterogeneous computing architecture and reasonable task allocation, the system energy consumption is reduced by about 20% compared with the traditional full CPU or full GPU architecture, which is suitable for high-performance applications of large-scale data encryption.

[0073] The present invention significantly improves the computing efficiency of fully homomorphic encryption. Compared with traditional single CPU processing, the computing speed of the present invention in processing homomorphic addition and multiplication is increased by 3 to 10 times, especially in large-scale ciphertext operations, the parallel processing capability of the GPU is fully utilized. Compared with traditional single GPU processing, the system can achieve a considerable acceleration ratio. The intelligent task scheduling module can dynamically allocate tasks so that CPU and GPU resources are optimally utilized, avoiding resource idleness and computing bottlenecks. Compared with the traditional solution of fixed task allocation, the dynamic scheduling solution increases the throughput of the overall system by about 30%, further accelerating the processing process of fully homomorphic encryption. By allocating tasks suitable for parallel computing to the GPU and handing over complex control logic tasks to the CPU for processing, the system maximizes the advantages of heterogeneous computing. Under the same computing load, the overall energy consumption of the system is reduced by about 20% compared with the traditional full CPU or full GPU architecture. This significantly reduces power consumption requirements in high-performance computing and large-scale data encryption scenarios.

[0074] The present invention also provides a homomorphic encryption heterogeneous processing system, comprising: an encryption module, used to homomorphically encrypt target data to form homomorphic encrypted data including a plurality of polynomials, wherein the polynomials include a plurality of zero coefficient terms and non-zero coefficient terms; a calling module, used to call a GPU to process a plurality of the non-zero coefficient terms in parallel, and call a CPU to process the processing steps except for the non-zero coefficient terms when executing processing steps for the homomorphic encrypted data.

[0075] Since the homomorphic encryption heterogeneous processing system is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods, the homomorphic encryption heterogeneous processing system can start from the characteristics of the polynomials generated by homomorphic encryption, use the characteristics of the polynomials generated by homomorphic encryption processing, and more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0076] Since the homomorphic encryption heterogeneous processing system provided by the present invention and the homomorphic encryption heterogeneous processing method described above belong to the same inventive concept, the electronic device provided by the present invention has all the advantages of the homomorphic encryption heterogeneous processing method described above, and the beneficial effects of the electronic device provided by the present invention will not be described one by one here.

[0077] To achieve the above object, the present invention also provides an electronic device, please refer to Figure 2 , Figure 2 FIG. 1 is a block diagram of an electronic device provided by an embodiment of the present invention. Figure 2 As shown, the electronic device includes:

[0078] A memory 103 storing a computer program;

[0079] A processor 101 is communicatively connected to the memory, and executes any one of the above-mentioned homomorphic encryption heterogeneous processing methods when calling the computer program;

[0080] The display 105 is communicatively connected to the processor and the memory, and is used to display a GUI interaction interface related to the homomorphic encryption heterogeneous processing method.

[0081] like Figure 2 As shown, the electronic device also includes a communication interface 102 and a communication bus 104, wherein the processor 101, the communication interface 102, and the memory 103 communicate with each other through the communication bus 104. The communication bus 104 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 104 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface 102 is used for communication between the above-mentioned electronic device and other devices.

[0082] The processor 101 referred to in the present invention may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor 101 is the control center of the electronic device, and various interfaces and lines are used to connect various parts of the entire electronic device.

[0083] The memory 103 may be used to store the computer program. The processor 101 implements various functions of the electronic device by running or executing the computer program stored in the memory 103 and calling the data stored in the memory 103 .

[0084] The memory 103 may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0085] Since the electronic device is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods, the electronic device can start from the characteristics of the polynomial itself generated by homomorphic encryption, use the characteristics of the polynomial generated by homomorphic encryption processing, and more effectively assign tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0086] Since the electronic device provided by the present invention and the homomorphic encryption heterogeneous processing method described above belong to the same inventive concept, the electronic device provided by the present invention has all the advantages of the homomorphic encryption heterogeneous processing method described above, and the beneficial effects of the electronic device provided by the present invention will not be described one by one here.

[0087] To achieve the above-mentioned object, the present invention provides a readable storage medium storing a computer program, which, when executed by a processor, implements the homomorphic encryption heterogeneous processing method as described in any one of the above. Since the readable storage medium is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods. Therefore, the readable storage medium can start from the characteristics of the polynomial itself generated by homomorphic encryption, and use the characteristics of the polynomial generated by homomorphic encryption processing to more effectively assign tasks to the CPU-GPU heterogeneous architecture, thereby achieving efficient and low-power homomorphic encryption processing.

[0088] Since the readable storage medium provided by the present invention and the homomorphic encryption heterogeneous processing method described above belong to the same inventive concept, the readable storage medium provided by the present invention has all the advantages of the homomorphic encryption heterogeneous processing method described above, and the beneficial effects of the readable storage medium provided by the present invention will not be described one by one here.

[0089] The readable storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer hard disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this article, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, a device or a device or used in combination with it.

[0090] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program codes. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0091] The present invention also provides a computer program product, which, when executed by a processor, implements any of the above-mentioned homomorphic encryption heterogeneous processing methods.

[0092] The present invention also provides a computer program product, which is used to execute any of the above-mentioned homomorphic encryption heterogeneous processing methods. Therefore, the computer program product can start from the characteristics of the polynomial itself generated by homomorphic encryption, use the polynomial characteristics generated by homomorphic encryption processing, and more effectively allocate tasks to the CPU-GPU heterogeneous architecture, thereby realizing efficient and low-power homomorphic encryption processing.

[0093] Since the computer program product provided by the present invention and the homomorphic encryption heterogeneous processing method described above belong to the same inventive concept, the computer program product provided by the present invention has all the advantages of the homomorphic encryption heterogeneous processing method described above, and the beneficial effects of the computer program product provided by the present invention will not be described one by one here.

[0094] It should be noted that the various embodiments in this specification are described in a progressive manner, and any embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0095] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0096] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0097] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A homomorphic encryption heterogeneous processing method, characterized in that: The following steps are involved: Homomorphically encrypting the target data to form homomorphically encrypted data including a plurality of polynomials, wherein the polynomials include a plurality of zero coefficient terms and non-zero coefficient terms; When executing the processing steps for the homomorphically encrypted data, calling the GPU to process the plurality of non-zero coefficient items in parallel, and calling the CPU to process the processing steps except for the non-zero coefficient items; Divide the polynomial into a plurality of term groups, and extract coefficients of each term of each term group; Based on the coefficients of each item of each item group, an index is established for access by the GPU, wherein, when storing, only non-zero coefficients are stored in the memory, and an index is established for each non-zero coefficient to form a non-zero coefficient block, so that the GPU only loads and calculates the non-zero coefficients when processing; Each of the non-zero coefficient blocks has a corresponding sparse matrix, which records the position, value and mapping information of the sparse matrix and the ciphertext block, so that the GPU can directly access the non-zero coefficient block using the mapping information.

2. The homomorphic encryption heterogeneous processing method according to claim 1, characterized in that: The GPU has multiple threads, and each thread is used to process the non-zero coefficient items with the same exponent.

3. The homomorphic encryption heterogeneous processing method according to claim 1, characterized in that: If the load of one of the CPU and the GPU exceeds a preset threshold, part of the processing steps is transferred to the other of the CPU and the GPU for processing.

4. A homomorphic encryption heterogeneous processing system, applied to the homomorphic encryption heterogeneous processing method as claimed in any one of claims 1 to 3, characterized in that: include: An encryption module, used to homomorphically encrypt the target data to form homomorphically encrypted data including a plurality of polynomials, wherein the polynomials include a plurality of zero coefficient terms and non-zero coefficient terms; A calling module is used to call the GPU to process multiple non-zero coefficient items in parallel and call the CPU to process the processing steps except for the non-zero coefficient items when executing processing steps for the homomorphically encrypted data.

5. An electronic device, characterized in that: The electronic device comprises: a memory storing a computer program; A processor, communicatively connected to the memory, and executing the homomorphic encryption heterogeneous processing method according to any one of claims 1 to 3 when calling the computer program; A display is communicatively connected to the processor and the memory, and is used to display a GUI interaction interface related to the homomorphic encryption heterogeneous processing method.

6. A readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it implements the homomorphic encryption heterogeneous processing method as described in any one of claims 1 to 3.

7. A computer program product, characterized in that When the computer program product is executed by a processor, it implements the homomorphic encryption heterogeneous processing method as described in any one of claims 1 to 3.

Images