Memristive neural network circuit for generating multi-direction multi-double-scroll chaotic attractors

Abstract

The invention discloses a memristor neural network circuit for generating a multi-direction multi-double-scroll chaotic attractor, which comprises a first integral channel circuit, a second integral channel circuit, a third integral channel circuit, a first memristor, a second memristor, a third memristor, a first switch, a second switch and a third switch, and is characterized in that the first integral channel circuit comprises three input ends and one output end; the second integral channel circuit comprises three input ends and one output end; the third integral channel circuit comprises two input ends and one output end. The memristive neural network circuit can generate a multi-direction multi-scroll chaotic attractor by controlling the on-off state of the memristive channels connected with the input ends of the integral channel circuits, and the circuit has a discharge characteristic closer to an interactive neuron in a real nervous system; the method can provide new possibility for physically constructing an intelligent neuromorphic system, and has important value in the fields of chaotic secret communication, image encryption, complex signal processing and the like.

Description

Technical Field

[0001] The invention relates to a memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors, and belongs to the technical field of memristor neural network circuit design. Background Art

[0002] A memristor is a nonlinear element with memory function, whose resistance value changes with the amount of charge passing through it. The concept of memristor was first proposed by Leon Chua in 1971, but it was not until 2008 that HP Labs successfully produced the first physical model. The emergence of memristors has brought new possibilities for electronic circuit design and application, especially in the fields of chaotic systems and neural networks. The official launch of the "China Brain Project" has created a new situation for brain science research in my country. Memristor neural networks combine the advantages of memristors and neural networks and can simulate the learning and memory functions of biological neural networks. By introducing memristors into neural networks, dynamic adjustment of neuron connection weights can be achieved, thereby enhancing the learning ability and adaptability of the network, and accurately and meticulously describing the dynamic evolution of neural networks.

[0003] Multi-scroll chaotic system is a kind of nonlinear system with complex dynamic behavior. By changing the system parameters, different numbers and types of scrolls can be generated, thereby increasing the complexity and pseudo-randomness of the system. Multi-directional multi-double scroll chaotic attractor further expands this concept. By introducing double scroll structures in multiple directions, the system exhibits more complex chaotic behavior in higher dimensions.

[0004] At present, a series of results have been achieved in the research on chaotic circuits that can generate controllable number of chaotic attractors. For example, the Chinese invention patent application with publication number CN107135063A discloses a chaotic circuit implementation method for generating grid multi-wing hyperchaotic hidden attractors, and the Chinese invention patent application with publication number CN116388951A discloses a multi-structure chaotic circuit based on a memristor Hopfield neural network. However, these circuits can only regulate the number or type of attractors in one or two directions, while the double-scroll attractors with controllable number in multiple directions have more complex dynamic behaviors. Therefore, it is necessary to design a memristor circuit that can generate different types of multiple double-scroll chaotic attractors in different directions. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors, which can generate different types of multi-double scroll chaotic attractors in different directions, and the generated chaotic attractors have complex dynamic characteristics.

[0006] The present invention adopts the following technical solutions to solve the above technical problems: A memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors, comprising: first to third integral channel circuits, first to third memristors and first to third switches; the first integral channel circuit comprises three input terminals, one output terminal, first to third resistors, a first membrane resistor, a first capacitor and a first operational amplifier; the second integral channel circuit comprises three input terminals, one output terminal, fourth to sixth resistors, a second membrane resistor, a second capacitor and a second operational amplifier; the third integral channel circuit comprises two input terminals, one output terminal, seventh to eighth resistors, a third membrane resistor, a third capacitor and a third operational amplifier; The output of the second integral channel circuit is sequentially transmitted through the first negative hyperbolic tangent circuit and the first inverter. The output of the first inverter The first input end of the first integral channel circuit is connected to the inverting input end of the first operational amplifier via the first resistor or the first memristor, and the first resistor and the first memristor are connected via the first switch Switching; the output of the first integral channel circuit passes through the second negative hyperbolic tangent circuit, the output A of the second negative hyperbolic tangent circuit is connected to the second input end of the first integral channel circuit, the second input end of the first integral channel circuit is connected to the inverting input end of the first operational amplifier through the second resistor or the second memristor, the second resistor and the second memristor are connected through the second switch Switching; the output of the third integral channel circuit passes through the third negative hyperbolic tangent circuit, the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the first integral channel circuit, the third input terminal of the first integral channel circuit is connected to the inverting input terminal of the first operational amplifier through the third resistor; the non-inverting input terminal of the first operational amplifier is grounded, the first capacitor is connected across the inverting input terminal and the output terminal of the first operational amplifier, the first membrane resistor is connected in parallel with the first capacitor, and the output of the first operational amplifier is used as the output of the first integral channel circuit; The output A of the second negative hyperbolic tangent circuit is connected to the first input terminal of the second integrating channel circuit, and the first input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a fourth resistor; the output B of the first negative hyperbolic tangent circuit is connected to the second input terminal of the second integrating channel circuit, and the second input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a fifth resistor; the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the second integrating channel circuit, and the third input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a sixth resistor; the in-phase input terminal of the second operational amplifier is grounded, the second capacitor is connected across the inverting input terminal and the output terminal of the second operational amplifier, the second membrane resistor is connected in parallel with the second capacitor, and the output of the second operational amplifier is used as the output of the second integrating channel circuit; The output of the second negative hyperbolic tangent circuit is passed through the second inverter, and the output of the second inverter The output of the third negative hyperbolic tangent circuit is connected to the third inverter, and the output of the third inverter is connected to the inverting input terminal of the third operational amplifier through the seventh resistor. The second input end of the third integral channel circuit is connected to the inverting input end of the third operational amplifier via the eighth resistor or the third memristor, and the eighth resistor and the third memristor are connected via the third switch Switching; the non-inverting input terminal of the third operational amplifier is grounded, the third capacitor is connected between the inverting input terminal and the output terminal of the third operational amplifier, the third membrane resistor is connected in parallel with the third capacitor, and the output of the third operational amplifier is used as the output of the third integration channel circuit; and When none of them are closed, the circuit equations of the first, second and third integration channel circuits are as follows: , In the formula, and Respectively represent the outputs of the first, second and third integration channel circuits, and denote the first, second, third, fourth, fifth, sixth, seventh and eighth resistors respectively, represents the hyperbolic tangent, Represents the first, second and third membrane resistors, the resistance values ​​of the first, second and third membrane resistors are equal, represents the first, second and third capacitors, and the capacitance values ​​of the first, second and third capacitors are equal.

[0007] As a preferred solution of the circuit of the present invention, the first memristor includes fourth to seventh operational amplifiers, ninth to fourteenth resistors, fourth to fifth membrane resistors, a fourth capacitor, fourth to fifth inverters, a fourth negative hyperbolic tangent circuit, a first multiplier and a first coupling resistor; The output of the first inverter as the input of the first memristor; the input of the first memristor is connected to the inverting input terminal of the sixth operational amplifier via the thirteenth resistor, the output terminal of the sixth operational amplifier is connected to the inverting input terminal of the fourth operational amplifier, the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the fifth operational amplifier via the ninth resistor, the tenth resistor is connected across the inverting input terminal and the output terminal of the fifth operational amplifier, the output terminal of the fifth operational amplifier is connected to the inverting input terminal of the sixth operational amplifier after passing through the fourth inverter and the eleventh resistor in sequence; The fourth capacitor is connected between the inverting input terminal and the output terminal of the sixth operational amplifier, the twelfth resistor is connected in parallel with the fourth capacitor, the output terminal of the sixth operational amplifier is connected to the first input terminal of the first multiplier via the fourth negative hyperbolic tangent circuit, the input of the first memristor is connected to the second input terminal of the first multiplier, and the output terminal of the first multiplier is connected to the inverting input terminal of the seventh operational amplifier via the fourteenth resistor; the input of the first memristor is connected to the inverting input terminal of the seventh operational amplifier after passing through the fifth inverter and the fourth membrane resistor in sequence, the fifth membrane resistor is connected between the inverting input terminal and the output terminal of the seventh operational amplifier, and the output terminal of the seventh operational amplifier obtains the output of the first memristor via the first coupling resistor; the in-phase input terminals of the fourth, fifth, sixth and seventh operational amplifiers are all grounded; The circuit equation for the first memristor is as follows: , In the formula, in the formula, and Respectively represent the twelfth, thirteenth and fourteenth resistors, represents the fourth capacitor, and the capacitance value of the fourth capacitor is equal to that of the first capacitor. represents the output of the sixth operational amplifier, represents the voltage variable obtained by inverting the output of the second integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

[0008] As a preferred solution of the circuit of the present invention, the second memristor includes eighth to eleventh operational amplifiers, fifteenth to twenty-first resistors, a sixth membrane resistor, a fifth capacitor, sixth to seventh inverters, a fifth negative hyperbolic tangent circuit, a second multiplier and a second coupling resistor; The output A of the second negative hyperbolic tangent circuit is used as the input of the second memristor; the input of the second memristor is connected to the inverting input terminal of the tenth operational amplifier after passing through the sixth inverter and the eighteenth resistor in sequence, the output terminal of the tenth operational amplifier is connected to the inverting input terminal of the eighth operational amplifier, the output terminal of the eighth operational amplifier is connected to the inverting input terminal of the ninth operational amplifier through the fifteenth resistor, the sixteenth resistor is connected across the inverting input terminal and the output terminal of the ninth operational amplifier, and the output terminal of the ninth operational amplifier is connected to the inverting input terminal of the tenth operational amplifier after passing through the seventh inverter and the nineteenth resistor in sequence; The fifth capacitor is connected between the inverting input terminal and the output terminal of the tenth operational amplifier, the twentieth resistor is connected in parallel with the fifth capacitor, the output terminal of the tenth operational amplifier is connected to the first input terminal of the second multiplier via the fifth negative hyperbolic tangent circuit, the input of the second memristor is connected to the second input terminal of the second multiplier, and the output terminal of the second multiplier is connected to the inverting input terminal of the eleventh operational amplifier via the twenty-first resistor; the input of the second memristor is connected to the inverting input terminal of the eleventh operational amplifier after passing through the sixth inverter and the seventeenth resistor in sequence, the sixth memristor is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier, and the output terminal of the eleventh operational amplifier obtains the output of the second memristor via the second coupling resistor; the in-phase input terminals of the eighth, ninth, tenth and eleventh operational amplifiers are all grounded; The circuit equation for the second memristor is as follows: , In the formula, in the formula, and represent the nineteenth, twentieth and twenty-first resistors respectively, represents the fifth capacitor, and the capacitance value of the fifth capacitor is equal to that of the first capacitor. represents the output of the tenth operational amplifier, represents the voltage variable obtained by inverting the output of the first integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

[0009] As a preferred solution of the circuit of the present invention, the third memristor includes twelfth to fifteenth operational amplifiers, twenty-second to twenty-eighth resistors, a seventh membrane resistor, a sixth capacitor, eighth to ninth inverters, a sixth negative hyperbolic tangent circuit, a third multiplier and a third coupling resistor; The output of the third inverter as the input of the third memristor; the input of the third memristor is connected to the inverting input terminal of the fourteenth operational amplifier via the twenty-third resistor, the output terminal of the fourteenth operational amplifier is connected to the inverting input terminal of the twelfth operational amplifier, the output terminal of the twelfth operational amplifier is connected to the inverting input terminal of the thirteenth operational amplifier via the twenty-second resistor, the twenty-sixth resistor is connected across the inverting input terminal and the output terminal of the thirteenth operational amplifier, the output terminal of the thirteenth operational amplifier is connected to the inverting input terminal of the fourteenth operational amplifier after passing through the ninth inverter and the twenty-fourth resistor in sequence; The sixth capacitor is connected between the inverting input terminal and the output terminal of the fourteenth operational amplifier, the twenty-fifth resistor is connected in parallel with the sixth capacitor, the output terminal of the fourteenth operational amplifier is connected to the first input terminal of the third multiplier via the sixth negative hyperbolic tangent circuit, the input of the third memristor is connected to the second input terminal of the third multiplier, and the output terminal of the third multiplier is connected to the inverting input terminal of the fifteenth operational amplifier via the twenty-eighth resistor; the input of the third memristor is connected to the inverting input terminal of the fifteenth operational amplifier after passing through the eighth inverter and the twenty-seventh resistor in sequence, the seventh membrane resistor is connected between the inverting input terminal and the output terminal of the fifteenth operational amplifier, and the output terminal of the fifteenth operational amplifier obtains the output of the third memristor via the third coupling resistor; the in-phase input terminals of the twelfth, thirteenth, fourteenth and fifteenth operational amplifiers are all grounded; The circuit equation for the third memristor is as follows: , In the formula, and denote the twenty-fourth, twenty-fifth and twenty-sixth resistors respectively, represents the sixth capacitor, and the capacitance value of the sixth capacitor is equal to that of the first capacitor. represents the output of the fourteenth operational amplifier, represents the voltage variable obtained by inverting the output of the third integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

[0010] The method for realizing the memristor neural network circuit based on the above-mentioned generation of multi-directional multi-double scroll chaotic attractors includes: When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch , and When all are closed, the memristor neural network circuit is a three-memristor neural network circuit. and Multiple double vortex chaotic attractors distributed in three directions are generated on the plane.

[0011] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. The present invention uses a first switch , Second switch and the third switch The on and off states of the memristors are controlled to output different chaotic signals, so that the memristor neural network circuit generates different types of multiple double vortex chaotic attractors in different directions. The generated chaotic attractors have complex dynamic characteristics. This circuit has the discharge characteristics that are closer to the interactive neurons in the real nervous system, and can provide new possibilities for the physical construction of intelligent neuromorphic systems.

[0012] 2. The present invention can change the topological structure and number of scrolls by changing system parameters. At the same time, the memristor neural network circuit has the advantages of simple structure and easy implementation. It has important reference value and application prospects in the fields of chaotic secure communication, image encryption and complex signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is an overall structural block diagram of a memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to the present invention; Figure 2 It is a circuit diagram of the main circuit of the present invention; Figure 3 is a circuit diagram of a first memristor of the present invention; Figure 4is a circuit diagram of a second memristor of the present invention; Figure 5 is a circuit diagram of a third memristor of the present invention; Figure 6 yes When closed Circuit simulation diagram of phase plane chaotic attractor; Figure 7 yes When closed Circuit simulation diagram of phase plane chaotic attractor; Figure 8 yes When closed Circuit simulation diagram of phase plane chaotic attractor; Fig. 9 yes , When closed Circuit simulation diagram of phase plane chaotic attractor; Fig.10 yes , When closed Circuit simulation diagram of phase plane chaotic attractor; Fig.11 yes , When closed Circuit simulation diagram of phase plane chaotic attractor; Fig.12 yes , and When closed Circuit simulation diagram of phase plane chaotic attractor; Fig.13 yes , and When closed Circuit simulation diagram of phase plane chaotic attractor; Fig.14 yes , and When closed Circuit simulation diagram of phase plane chaotic attractor. DETAILED DESCRIPTION

[0014] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0015] like Figure 1 As shown, the present invention proposes a memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors, including: a main circuit including three integral channel circuits, three memristors and three switches. The three memristors are respectively connected through switches. and The output end of each integral channel circuit is connected to the input end of the three memristors. and The on and off states of the memristor neural network circuit cause it to generate different types of chaotic attractors of multiple double scrolls on different phase planes.

[0016] like Figure 2 As shown, the first to third integrating channel circuits, the first integrating channel circuit has first to third input terminals and an output terminal, the second integrating channel circuit has first to third input terminals and an output terminal, and the third integrating channel circuit has first to second input terminals and an output terminal.

[0017] The first input end of the first integral channel circuit is connected to the first memristor or the first resistor, and the two are connected through the first switch Switching, the output of the second integration channel circuit After the first negative hyperbolic tangent circuit and the first inverter, the output of the first inverter The first input end of the first integral channel circuit is connected to the first input end of the first integral channel circuit; the second input end of the first integral channel circuit is connected to the second memristor or the second resistor, and the two are connected through the second switch Switching, the output of the first integration channel circuit The output A of the second negative hyperbolic tangent circuit is connected to the second input terminal of the first integral channel circuit through the second negative hyperbolic tangent circuit. The third input terminal of the first integral channel circuit is connected to the third resistor. The first integral channel circuit includes a first resistor, a second resistor, a third resistor, a first film resistor, a first capacitor and a first operational amplifier. The first resistor, the second resistor and the third resistor are connected to the inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier is grounded, the output terminal of the first operational amplifier serves as the output terminal of the first integral channel circuit, the first capacitor is connected across the inverting input terminal and the output terminal of the first operational amplifier, and the first film resistor is connected in parallel with the first capacitor.

[0018] The first input terminal of the second integral channel circuit is connected to the output terminal of the second negative hyperbolic tangent circuit, the second input terminal is connected to the output terminal of the first negative hyperbolic tangent circuit, and the third input terminal is connected to the output terminal of the third negative hyperbolic tangent circuit. The second integral channel circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a second film resistor, a second capacitor, and a second operational amplifier. The first input terminal of the second integral channel circuit is connected to the inverting input terminal of the second operational amplifier via the fourth resistor, the second input terminal is connected to the inverting input terminal of the second operational amplifier via the fifth resistor, the third input terminal is connected to the inverting input terminal of the second operational amplifier via the sixth resistor, the non-inverting input terminal of the second operational amplifier is grounded, the second capacitor is connected across the output terminal and the inverting input terminal of the second operational amplifier, the output terminal of the second operational amplifier serves as the output terminal of the second integral channel, and the second film resistor is connected in parallel with the second capacitor.

[0019] The first input terminal of the third integral channel circuit is connected to the output terminal of the second inverter; the second input terminal of the third integral channel circuit is connected to the third memristor or the eighth resistor, and the two are connected through the third switch Switching, the output of the third integration channel circuit The first input end of the third integral channel circuit is connected to the third negative hyperbolic tangent circuit and the third inverter. The third integral channel circuit includes a seventh resistor, an eighth resistor, a third membrane resistor, a third capacitor and a third operational amplifier. The first input end of the third integral channel circuit is connected to the inverting input end of the third operational amplifier via the seventh resistor, the second input end is connected to the inverting input end of the third operational amplifier via the eighth resistor or the third memristor, the non-inverting input end of the third operational amplifier is grounded, the output end of the third operational amplifier serves as the output end of the third integral channel circuit, the third capacitor is connected between the output end and the inverting input end of the third operational amplifier, and the third membrane resistor is connected in parallel with the third capacitor.

[0020] like Figure 3 As shown, the first memristor includes a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a seventh operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fourth capacitor, a fourth film resistor, a fifth film resistor, a fourth inverter, a fifth inverter, a fourth negative hyperbolic tangent circuit, a first multiplier and a first coupling resistor The non-inverting input terminals of the fourth operational amplifier, the fifth operational amplifier, the sixth operational amplifier and the seventh operational amplifier are grounded, the inverting input terminal of the fourth operational amplifier is connected to the output terminal of the sixth operational amplifier, the output terminal of the fourth operational amplifier is connected to the ninth resistor, the output terminal of the ninth resistor is connected to the inverting input terminal of the fifth operational amplifier, the tenth resistor is connected between the output terminal and the inverting input terminal of the fifth operational amplifier, the output of the fifth operational amplifier is connected to the fourth inverter, and the output terminal of the fourth inverter is connected to the eleventh resistor; the input terminal of the first memristor is connected to the inverting input terminal of the sixth operational amplifier through the thirteenth resistor, and the output terminal of the eleventh resistor is connected to the inverting input terminal of the sixth operational amplifier. , the fourth capacitor is connected across the output terminal and the inverting input terminal of the sixth operational amplifier, the twelfth resistor is connected across the output terminal and the inverting input terminal of the sixth operational amplifier, the output of the sixth operational amplifier is connected to the fourth negative hyperbolic tangent circuit, the output of the fourth negative hyperbolic tangent circuit and the input of the first memristor are connected to the first multiplier, the output of the first multiplier is connected to the fourteenth resistor, the output of the fourteenth resistor is connected to the inverting input terminal of the seventh operational amplifier, the input terminal of the first memristor is connected to the inverting input terminal of the seventh operational amplifier via the fifth inverter and the fourth membrane resistor, the fifth membrane resistor is connected across the output terminal and the inverting input terminal of the seventh operational amplifier, and the output terminal of the seventh operational amplifier is connected to the first coupling resistor , The output end of is used as the output end of the first memristor.

[0021] like Figure 4 As shown, the second memristor includes a sixth inverter, a seventh inverter, a fifth negative hyperbolic tangent circuit, an eighth operational amplifier, a ninth operational amplifier, a tenth operational amplifier, an eleventh operational amplifier, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a fifth capacitor, a second multiplier, and a second coupling resistor The non-inverting input terminals of the eighth operational amplifier, the ninth operational amplifier, the tenth operational amplifier and the eleventh operational amplifier are grounded, the inverting terminal of the eighth operational amplifier is connected to the output terminal of the tenth operational amplifier, the output terminal of the eighth operational amplifier is connected to the fifteenth resistor, the output terminal of the fifteenth resistor is connected to the inverting input terminal of the ninth operational amplifier, the sixteenth resistor is connected between the output terminal and the inverting input terminal of the ninth operational amplifier, the output terminal of the ninth operational amplifier is connected to the input terminal of the seventh inverter, the output terminal of the seventh inverter is connected to the input terminal of the nineteenth resistor, the output terminal of the nineteenth resistor is connected to the inverting input terminal of the tenth operational amplifier, the fifth capacitor is connected between the output terminal and the inverting input terminal of the tenth operational amplifier, the twentieth resistor is connected between the output terminal and the inverting input terminal of the tenth operational amplifier The input end of the second memristor is connected to the sixth inverter and then to the input end of the seventeenth resistor and the input end of the eighteenth resistor. The output end of the eighteenth resistor is connected to the inverting input end of the tenth operational amplifier. The output end of the tenth operational amplifier is connected to the fifth negative hyperbolic tangent circuit. The output end of the fifth negative hyperbolic tangent circuit is connected to the second multiplier. The input end of the second memristor is connected to the second multiplier. The output end of the second multiplier is connected to the input end of the twenty-first resistor. The output end of the twenty-first resistor is connected to the inverting input end of the eleventh operational amplifier. The output end of the seventeenth resistor is connected to the inverting input end of the eleventh operational amplifier. The sixth membrane resistor is connected across the output end and the inverting input end of the eleventh operational amplifier. The output end of the eleventh operational amplifier is connected to the second coupling resistor. , The output of is used as the output of the second memristor.

[0022] like Figure 5 As shown, the third memristor includes an eighth inverter, a ninth inverter, a sixth negative hyperbolic tangent circuit, a twelfth operational amplifier, a thirteenth operational amplifier, a fourteenth operational amplifier, a fifteenth operational amplifier, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a third multiplier, a sixth capacitor, a seventh membrane resistor, and a third coupling resistor The non-inverting input terminals of the twelfth operational amplifier, the thirteenth operational amplifier, the fourteenth operational amplifier and the fifteenth operational amplifier are all grounded, the inverting input terminal of the twelfth operational amplifier is connected to the output of the fourteenth operational amplifier, the output terminal of the twelfth operational amplifier is connected to the input terminal of the twenty-second resistor, the output terminal of the twenty-second resistor is connected to the inverting input terminal of the thirteenth operational amplifier, the twenty-sixth resistor is connected between the output terminal and the inverting input terminal of the thirteenth operational amplifier, the output terminal of the thirteenth operational amplifier is connected to the input terminal of the ninth inverter, the output terminal of the ninth inverter is connected to the input terminal of the twenty-fourth resistor, the output terminal of the twenty-fourth resistor is connected to the inverting input terminal of the fourteenth operational amplifier, the input terminal of the third memristor is connected to the input terminal of the twenty-third resistor, and the output terminal of the twenty-third resistor is connected to the inverting input terminal of the fourteenth operational amplifier. The sixth capacitor is connected between the inverting input terminal and the output terminal of the fourteenth operational amplifier, the twenty-fifth resistor is connected between the inverting input terminal and the output terminal of the fourteenth operational amplifier, the output terminal of the fourteenth operational amplifier is connected to the input terminal of the sixth negative hyperbolic tangent, the output terminal of the sixth negative hyperbolic tangent is connected to the third multiplier, the input terminal of the third memristor is connected to the third multiplier, the output terminal of the third multiplier is connected to the input terminal of the twenty-eighth resistor, the input terminal of the third memristor is connected to the eighth inverter, the output terminal of the eighth inverter is connected to the input terminal of the twenty-seventh resistor, the output terminal of the twenty-seventh resistor is connected to the inverting input terminal of the fifteenth operational amplifier, the output terminal of the twenty-eighth resistor is connected to the inverting input terminal of the fifteenth operational amplifier, the seventh membrane resistor is connected between the output terminal and the inverting input terminal of the fifteenth operational amplifier, and the output terminal of the fifteenth operational amplifier is connected to the third coupling resistor The input terminal, The output end of is used as the output end of the third memristor.

[0023] Figure 2 , Figure 3 , Figure 4 and Figure 5 The circuit equations involved are as follows: , The above circuit equations are all prototype equations when the first, second, and third integration channel circuits are not closed. The capacitance values ​​of the first to sixth capacitors are equal. The resistance values ​​of the first to seventh membrane resistors are equal, and are indicated by express.

[0024] Take the single memristor coupled neural network model as an example, that is, when the switch closure, and All are in the on state. The circuit equation after connecting to the first memristor is as follows: , and The remaining two closed and open states are the same as above The closed circuit equation can be obtained in the same way.

[0025] Take the dual memristor coupled neural network model as an example, that is, when the switch Close, switch is in the on state. The circuit equation after connecting the first memristor and the second memristor is as follows: , Take the three-memristor coupled neural network model as an example, that is, when the switch and In the closed state, the circuit equation after connecting the first memristor, the second memristor, and the third memristor is as follows: , in, are six voltage variables. Any other switch states are the same as the above equations.

[0026] The implementation method of the memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors is as follows: when closure, When turned on, the single memristor coupled neural network model Multiple double vortex chaotic attractors distributed in a single direction generated on the plane; when closure, When turned on, the single memristor coupled neural network model Multiple double vortex chaotic attractors distributed in a single direction generated on the plane; when closure, When turned on, the single memristor coupled neural network model Multiple double vortex chaotic attractors distributed in a single direction generated on the plane; when closure, When turned on, the dual memristor coupled neural network model Multiple double vortex chaotic attractors are generated in two directions on the plane; when closure, When turned on, the dual memristor coupled neural network model Multiple double vortex chaotic attractors are generated in two directions on the plane; when closure, When turned on, the dual memristor coupled neural network model Multiple double vortex chaotic attractors are generated in two directions on the plane; when When all are turned off, the three-memristor coupled neural network model , and Multiple double vortex chaotic attractors are distributed in three directions on the plane.

[0027] Selection of circuit components and power supply voltage of the present invention: Figures 1 to 5 All operational amplifiers in the system are TL082CP and all power supply voltages are The output saturation value of each operational amplifier is All analog multipliers in the figure are AD633 and the voltage is .

[0028] The parameters of each component are: Set the integration time constant is 0.1 ms, and the resistance values ​​of the first to seventh membrane resistors are , the capacitance values ​​of the first to sixth capacitors are , the multiplier ratio is 0.1. Based on the synaptic weight matrix model of the neural network, the modular design method of the improved chaotic circuit can be derived Figures 2 to 5 All theoretical resistances are shown in Table 1: Table 1

[0029] The present invention was tested according to Table 1 and the above time parameters, and the switch was controlled. and The switching state of the phase plane corresponding relationship table of multiple double scroll chaotic attractors is obtained, as shown in Table 2: Table 2

[0030] The present invention was tested according to the corresponding relationship in Table 2. Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 , respectively give the generation of a multi-directional multi-double scroll chaotic attractor memristor neural network circuit of the present invention Attractor phase diagram, Attractor phase diagram, Attractor phase diagram, Attractor phase diagram, Attractor phase diagram, Attractor phase diagram and , , Attractor phase diagram.

[0031] As can be seen from Table 2, the present invention can generate chaotic attractors of multiple double vortices in multiple different directions, has complex dynamic characteristics and excellent pseudo-randomness, and can ensure the security of encrypted information.

[0032] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors, characterized in that: include: first to third integrating channel circuits, first to third memristors, and first to third switches; The first integrating channel circuit includes three input terminals, one output terminal, first to third resistors, a first membrane resistor, a first capacitor, and a first operational amplifier; The second integral channel circuit includes three input terminals, one output terminal, fourth to sixth resistors, a second film resistor, a second capacitor and a second operational amplifier; the third integral channel circuit includes two input terminals, one output terminal, seventh to eighth resistors, a third film resistor, a third capacitor and a third operational amplifier; The output of the second integral channel circuit is sequentially transmitted through the first negative hyperbolic tangent circuit and the first inverter. The output of the first inverter The first input end of the first integral channel circuit is connected to the inverting input end of the first operational amplifier via the first resistor or the first memristor, and the first resistor and the first memristor are connected via the first switch Switching; the output of the first integral channel circuit passes through the second negative hyperbolic tangent circuit, the output A of the second negative hyperbolic tangent circuit is connected to the second input end of the first integral channel circuit, the second input end of the first integral channel circuit is connected to the inverting input end of the first operational amplifier through the second resistor or the second memristor, the second resistor and the second memristor are connected through the second switch Switching; the output of the third integral channel circuit passes through the third negative hyperbolic tangent circuit, the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the first integral channel circuit, the third input terminal of the first integral channel circuit is connected to the inverting input terminal of the first operational amplifier through the third resistor; the non-inverting input terminal of the first operational amplifier is grounded, the first capacitor is connected across the inverting input terminal and the output terminal of the first operational amplifier, the first membrane resistor is connected in parallel with the first capacitor, and the output of the first operational amplifier is used as the output of the first integral channel circuit; The output A of the second negative hyperbolic tangent circuit is connected to the first input terminal of the second integrating channel circuit, and the first input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a fourth resistor; the output B of the first negative hyperbolic tangent circuit is connected to the second input terminal of the second integrating channel circuit, and the second input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a fifth resistor; the output C of the third negative hyperbolic tangent circuit is connected to the third input terminal of the second integrating channel circuit, and the third input terminal of the second integrating channel circuit is connected to the inverting input terminal of the second operational amplifier via a sixth resistor; the in-phase input terminal of the second operational amplifier is grounded, the second capacitor is connected across the inverting input terminal and the output terminal of the second operational amplifier, the second membrane resistor is connected in parallel with the second capacitor, and the output of the second operational amplifier is used as the output of the second integrating channel circuit; The output of the second negative hyperbolic tangent circuit is passed through the second inverter, and the output of the second inverter The output of the third negative hyperbolic tangent circuit is connected to the third inverter, and the output of the third inverter is connected to the inverting input terminal of the third operational amplifier through the seventh resistor. The second input end of the third integral channel circuit is connected to the inverting input end of the third operational amplifier via the eighth resistor or the third memristor, and the eighth resistor and the third memristor are connected via the third switch Switching; the non-inverting input terminal of the third operational amplifier is grounded, the third capacitor is connected between the inverting input terminal and the output terminal of the third operational amplifier, the third membrane resistor is connected in parallel with the third capacitor, and the output of the third operational amplifier is used as the output of the third integration channel circuit; and When none of them are closed, the circuit equations of the first, second and third integration channel circuits are as follows: ， In the formula, and Respectively represent the outputs of the first, second and third integration channel circuits, and denote the first, second, third, fourth, fifth, sixth, seventh and eighth resistors respectively, represents the hyperbolic tangent, Represents the first, second and third membrane resistors, the resistance values ​​of the first, second and third membrane resistors are equal, represents the first, second and third capacitors, and the capacitance values ​​of the first, second and third capacitors are equal.

2. The memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to claim 1, characterized in that: The first memristor includes fourth to seventh operational amplifiers, ninth to fourteenth resistors, fourth to fifth membrane resistors, a fourth capacitor, fourth to fifth inverters, a fourth negative hyperbolic tangent circuit, a first multiplier, and a first coupling resistor; The output of the first inverter as the input of the first memristor; the input of the first memristor is connected to the inverting input terminal of the sixth operational amplifier via the thirteenth resistor, the output terminal of the sixth operational amplifier is connected to the inverting input terminal of the fourth operational amplifier, the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the fifth operational amplifier via the ninth resistor, the tenth resistor is connected across the inverting input terminal and the output terminal of the fifth operational amplifier, the output terminal of the fifth operational amplifier is connected to the inverting input terminal of the sixth operational amplifier after passing through the fourth inverter and the eleventh resistor in sequence; The fourth capacitor is connected between the inverting input terminal and the output terminal of the sixth operational amplifier, the twelfth resistor is connected in parallel with the fourth capacitor, the output terminal of the sixth operational amplifier is connected to the first input terminal of the first multiplier via the fourth negative hyperbolic tangent circuit, the input of the first memristor is connected to the second input terminal of the first multiplier, and the output terminal of the first multiplier is connected to the inverting input terminal of the seventh operational amplifier via the fourteenth resistor; the input of the first memristor is connected to the inverting input terminal of the seventh operational amplifier after passing through the fifth inverter and the fourth membrane resistor in sequence, the fifth membrane resistor is connected between the inverting input terminal and the output terminal of the seventh operational amplifier, and the output terminal of the seventh operational amplifier obtains the output of the first memristor via the first coupling resistor; the in-phase input terminals of the fourth, fifth, sixth and seventh operational amplifiers are all grounded; The circuit equation for the first memristor is as follows: ， In the formula, in the formula, and Respectively represent the twelfth, thirteenth and fourteenth resistors, represents the fourth capacitor, and the capacitance value of the fourth capacitor is equal to that of the first capacitor. represents the output of the sixth operational amplifier, represents the voltage variable obtained by inverting the output of the second integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

3. The memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to claim 1, characterized in that: The second memristor includes eighth to eleventh operational amplifiers, fifteenth to twenty-first resistors, a sixth membrane resistor, a fifth capacitor, sixth to seventh inverters, a fifth negative hyperbolic tangent circuit, a second multiplier, and a second coupling resistor; The output A of the second negative hyperbolic tangent circuit is used as the input of the second memristor; the input of the second memristor is connected to the inverting input terminal of the tenth operational amplifier after passing through the sixth inverter and the eighteenth resistor in sequence, the output terminal of the tenth operational amplifier is connected to the inverting input terminal of the eighth operational amplifier, the output terminal of the eighth operational amplifier is connected to the inverting input terminal of the ninth operational amplifier through the fifteenth resistor, the sixteenth resistor is connected across the inverting input terminal and the output terminal of the ninth operational amplifier, and the output terminal of the ninth operational amplifier is connected to the inverting input terminal of the tenth operational amplifier after passing through the seventh inverter and the nineteenth resistor in sequence; The fifth capacitor is connected between the inverting input terminal and the output terminal of the tenth operational amplifier, the twentieth resistor is connected in parallel with the fifth capacitor, the output terminal of the tenth operational amplifier is connected to the first input terminal of the second multiplier via the fifth negative hyperbolic tangent circuit, the input of the second memristor is connected to the second input terminal of the second multiplier, and the output terminal of the second multiplier is connected to the inverting input terminal of the eleventh operational amplifier via the twenty-first resistor; the input of the second memristor is connected to the inverting input terminal of the eleventh operational amplifier after passing through the sixth inverter and the seventeenth resistor in sequence, the sixth memristor is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier, and the output terminal of the eleventh operational amplifier obtains the output of the second memristor via the second coupling resistor; the in-phase input terminals of the eighth, ninth, tenth and eleventh operational amplifiers are all grounded; The circuit equation for the second memristor is as follows: ， In the formula, in the formula, and represent the nineteenth, twentieth and twenty-first resistors respectively, represents the fifth capacitor, and the capacitance value of the fifth capacitor is equal to that of the first capacitor. represents the output of the tenth operational amplifier, represents the voltage variable obtained by inverting the output of the first integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

4. The memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors according to claim 1, characterized in that: The third memristor includes twelfth to fifteenth operational amplifiers, twenty-second to twenty-eighth resistors, a seventh membrane resistor, a sixth capacitor, eighth to ninth inverters, a sixth negative hyperbolic tangent circuit, a third multiplier and a third coupling resistor; The output of the third inverter as the input of the third memristor; the input of the third memristor is connected to the inverting input terminal of the fourteenth operational amplifier via the twenty-third resistor, the output terminal of the fourteenth operational amplifier is connected to the inverting input terminal of the twelfth operational amplifier, the output terminal of the twelfth operational amplifier is connected to the inverting input terminal of the thirteenth operational amplifier via the twenty-second resistor, the twenty-sixth resistor is connected across the inverting input terminal and the output terminal of the thirteenth operational amplifier, the output terminal of the thirteenth operational amplifier is connected to the inverting input terminal of the fourteenth operational amplifier after passing through the ninth inverter and the twenty-fourth resistor in sequence; The sixth capacitor is connected between the inverting input terminal and the output terminal of the fourteenth operational amplifier, the twenty-fifth resistor is connected in parallel with the sixth capacitor, the output terminal of the fourteenth operational amplifier is connected to the first input terminal of the third multiplier via the sixth negative hyperbolic tangent circuit, the input of the third memristor is connected to the second input terminal of the third multiplier, and the output terminal of the third multiplier is connected to the inverting input terminal of the fifteenth operational amplifier via the twenty-eighth resistor; the input of the third memristor is connected to the inverting input terminal of the fifteenth operational amplifier after passing through the eighth inverter and the twenty-seventh resistor in sequence, the seventh membrane resistor is connected between the inverting input terminal and the output terminal of the fifteenth operational amplifier, and the output terminal of the fifteenth operational amplifier obtains the output of the third memristor via the third coupling resistor; the in-phase input terminals of the twelfth, thirteenth, fourteenth and fifteenth operational amplifiers are all grounded; The circuit equation for the third memristor is as follows: ， In the formula, and denote the twenty-fourth, twenty-fifth and twenty-sixth resistors respectively, represents the sixth capacitor, and the capacitance value of the sixth capacitor is equal to that of the first capacitor. represents the output of the fourteenth operational amplifier, represents the voltage variable obtained by inverting the output of the third integral channel circuit, represents the hyperbolic tangent, Represents a symbolic function.

5. A method for implementing a memristor neural network circuit for generating multi-directional multi-double scroll chaotic attractors based on any one of claims 1 to 4, characterized in that: include: When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch closure, and When turned on, the memristor neural network circuit is a single memristor neural network circuit. Multiple double vortex chaotic attractors with unidirectional distribution are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch and closure, When turned on, the memristor neural network circuit is a dual memristor neural network circuit. Multiple double vortex chaotic attractors distributed in two directions are generated on the plane; When the switch , and When all are closed, the memristor neural network circuit is a three-memristor neural network circuit. and Multiple double vortex chaotic attractors distributed in three directions are generated on the plane.

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