Storage unit, manufacturing method thereof, memory and electronic equipment

Abstract

The invention provides a memory cell, a manufacturing method thereof, a memory and an electronic device, a memory layer and a second conductive layer are sequentially formed in a hole of a stack structure, and the stack structure comprises an insulating layer and a first conductive layer which are alternately stacked. Orthographic projections of the storage layer, the second conductive layer and at least part of the first conductive layer on the first plane perpendicular to the stacking direction are overlapped, so that the storage layer and the second conductive layer can be inserted into the stacking structure along the aperture direction, and the opposite area of the first conductive layer and the second conductive layer is increased; therefore, the area of a storage capacitor formed by the first conductive layer, the storage layer and the second conductive layer is increased, read-write charges of the storage unit are increased, and the problem that the read-write charges are few due to the fact that the right opposite area of the storage capacitor is small when the thickness of the first conductive layer is small is avoided. Therefore, read-write errors caused by less read-write charges are reduced, and the read-write accuracy of the storage unit is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a storage unit, a manufacturing method thereof, a memory and an electronic device. Background Art

[0002] In recent years, with the development and popularization of semiconductor technology, many new memories have emerged, such as Ferroelectric Random Access Memory (FeRAM), Phase Change Random Access Memory (PCRAM), Magnetic Random Access Memory (MRAM) and Resistive Random Access Memory (ReRAM). These new memories have smaller storage cell sizes and can achieve faster access speeds with lower power consumption, and are now being used more and more widely.

[0003] Moreover, as the size of storage cells continues to decrease, the density of two-dimensional storage has reached its limit, leading to the emergence of three-dimensional storage, which can stack multiple storage cells in the same area, thereby increasing storage density. However, in three-dimensional storage, as the number of stacked layers increases, the thickness of each conductive layer and each insulating layer gradually decreases, which makes the area facing the two electrodes in the capacitor of the storage cell smaller and smaller, resulting in a decrease in the read and write charge of the storage cell, weaker read and write signals, and larger read and write errors. Summary of the invention

[0004] The present application provides a storage unit, a manufacturing method thereof, a memory and an electronic device, which are used to increase the read and write charges of the storage unit and reduce the read and write errors.

[0005] In a first aspect, an embodiment of the present application provides a storage unit, comprising: a stacking structure, a hole penetrating the stacking structure along a stacking direction, and a storage layer and a second conductive layer filled in the hole, wherein the storage layer is at least arranged between the second conductive layer and the stacking structure; wherein the stacking structure comprises at least one insulating layer and at least one first conductive layer alternately stacked, and when a plane perpendicular to the stacking direction is recorded as a first plane, the orthographic projections of the storage layer, the second conductive layer, and at least part of the first conductive layer on the first plane overlap. For example, when the first conductive layer has one layer, the orthographic projections of the first conductive layer, the storage layer, and the second conductive layer on the first plane overlap; when the first conductive layer has multiple layers, the orthographic projections of part of the first conductive layer, the storage layer, and the second conductive layer on the first plane overlap, or the orthographic projections of each first conductive layer, the storage layer, and the second conductive layer on the first plane overlap. In this way, the storage layer and the second conductive layer can be inserted into the stacked structure along the direction of the aperture, so that at least part of the first conductive layer and the second conductive layer not only have opposite faces in the first direction, but also have opposite faces in the non-first direction, increasing the opposite area of ​​the first conductive layer and the second conductive layer, thereby increasing the area of ​​the storage capacitor formed by the first conductive layer, the storage layer and the second conductive layer, thereby increasing the read and write charge of the storage unit, avoiding the problem of less read and write charge caused by the smaller opposite area of ​​the storage capacitor when the thickness of the first conductive layer is smaller, thereby reducing the read and write errors caused by less read and write charge, and improving the read and write accuracy of the storage unit. It should be understood that the first direction is any direction parallel to the first plane.

[0006] When the stacked structure is disposed on the substrate, the hole may expose part of the surface of the substrate, and the exposed surface of the substrate may be regarded as the bottom of the hole. The surface of the stacked structure facing the hole may be regarded as the side wall of the hole, and the storage layer may be disposed only on the side wall of the hole, or the storage layer may be disposed not only on the side wall of the hole but also on the bottom of the hole, in which case the storage layer disposed on the side wall is located between the second conductive layer and the stacked structure. Therefore, the specific location of the storage layer may be set according to actual conditions and is not limited here.

[0007] Furthermore, the materials used to make the storage layer may include ferroelectric materials, phase change materials, or resistive materials, etc., and the corresponding storage units may be ferroelectric storage units, phase change storage units, or resistive storage units, etc., so that the storage units in the embodiments of the present application have a wider range of applications. Furthermore, since the orthographic projections of the storage layer, the second conductive layer, and at least part of the first conductive layer on the first plane overlap, the overlapping second conductive layer and the first conductive layer can apply stress to the storage layer located between the two, and the second conductive layer and the first conductive layer can also apply stress to the storage layer located between the two in a direction perpendicular to the stacking direction, thus increasing the stress of the first conductive layer and the second conductive layer on the storage layer, which is beneficial to the crystallization of the material in the storage layer, thereby facilitating the realization of the storage function of the storage layer. For example, when the materials used to make the storage layer include ferroelectric materials, it is beneficial to the formation of a ferroelectric phase in the storage layer, thereby facilitating the formation of a ferroelectric storage unit. In addition, since the orthographic projections of the storage layer, the second conductive layer and at least part of the first conductive layer on the first plane overlap, an electric field is formed not only in the direction perpendicular to the stacking direction, but also in other directions such as the stacking direction, so that the distribution of the electric field is no longer in a single direction but in multiple directions. In this way, when the material making the storage layer includes ferroelectric material, even if the polarization axis direction in the storage layer is parallel to the stacking direction, it can also be polarized. Reversal, thereby increasing the probability of polarization reversal of the ferroelectric material and improving the performance of the ferroelectric memory unit.

[0008] Exemplarily, in order to achieve the overlap of the orthographic projections of the storage layer, the second conductive layer, and at least a portion of the first conductive layer on the first plane, the following methods may be used:

[0009] The first way: at least part of the first conductive layer is recessed relative to the adjacent insulating layer in the direction along the aperture of the hole, that is, if the first conductive layer recessed relative to the adjacent insulating layer is called a recessed first conductive layer, the recessed first conductive layer is not aligned with the end of the adjacent insulating layer facing the hole, the end of the insulating layer facing the hole protrudes outward and extends into the hole, and the end of the recessed first conductive layer facing the hole is recessed to form a recess, so that the side wall of the hole is concave and convex. Among them, the end face of the recessed first conductive layer facing the hole can be a non-planar surface, and the cross-sectional shape of the end face on the second plane parallel to the stacking direction can be: semicircular, semi-elliptical, triangular or polygonal, as long as the end face of the recessed first conductive layer facing the hole presents a non-planar surface. In this way, the orthographic projections of the storage layer, the second conductive layer and the recessed first conductive layer on the first plane can overlap. In addition, the maximum distance between the non-planar surface and the end face of the adjacent insulating layer facing the hole can be set to any value between 1nm and 1μm. There is no strict requirement for the specific distance setting, and it can be adjusted according to actual needs. In addition, when the insulating layer adjacent to the recessed first conductive layer protrudes outward toward one end of the hole, the cross-sectional shape of the protruding portion parallel to the second plane can be: rectangular, circular, elliptical, triangular, trapezoidal or other shapes. There are no strict requirements for the specific cross-sectional shape and it can be adjusted according to actual needs.

[0010] The second way: at least part of the first conductive layer has a protrusion relative to the adjacent insulating layer in the direction along the aperture of the hole, that is, if the first conductive layer with the protrusion is called a protruding first conductive layer, the protruding first conductive layer is not aligned with the end of the adjacent insulating layer facing the hole. The protruding first conductive layer protrudes outwards and extends into the hole at one end facing the hole, while the insulating layer is recessed at one end facing the hole to form a depression, so that the side wall of the hole is concave and convex, so that the storage layer, the second conductive layer and the protruding first conductive layer on the first plane can overlap. Among them, the length of the protrusion along the aperture of the hole is any value between 1nm and 1μm, and there is no strict requirement for the specific length setting, which can be adjusted according to actual needs. In addition, the protruding first conductive layer may include: a connected body and a protruding portion, and the body and the protruding portion can be made of the same conductive material or different conductive materials, which can be set according to actual conditions. In addition, the cross-sectional shape of the protrusion parallel to the second plane can be: rectangular, circular, elliptical, triangular, trapezoidal or other shapes. There are no strict requirements for the specific cross-sectional shape and it can be adjusted according to actual needs.

[0011] Exemplarily, the storage layer can be divided into a plurality of storage parts, the number of storage parts is the same as the number of the first conductive layer and is arranged one-to-one, and each storage part at least partially wraps the end of the corresponding first conductive layer facing the hole; similarly, the second conductive layer can be divided into a plurality of conductive parts, the number of conductive parts is the same as the number of storage parts and is arranged one-to-one. In this way, the corresponding conductive part, the storage part and the first conductive layer can form a conductive-medium-conductive structure, thereby forming a storage capacitor, wherein the conductive part can be regarded as the first end of the storage capacitor, and the first conductive layer can be regarded as the second end of the storage capacitor. Based on this, when the stacking structure includes n (n is a positive integer) layers of the first conductive layer, n storage capacitors are correspondingly arranged, and the conductive parts of the n storage capacitors are connected to each other, so that the first ends of the n storage capacitors are connected to each other and can be connected to the same potential, and the second ends of the n storage capacitors are insulated from each other and can be connected to different potentials. When the first end of each storage capacitor is connected to the same potential, by connecting different potentials to different second ends, data can be written to and read from each storage capacitor.

[0012] In addition to n storage capacitors, the storage unit may also include a transistor. For each storage unit: when there is one transistor, the gate of the transistor is connected to the word line, the source of the transistor is connected to the bit line, and the drain of the transistor is respectively connected to the first end of the n storage capacitors, or the source of the transistor is respectively connected to the first end of the n storage capacitors, and the drain of the transistor is connected to the bit line. When there are multiple transistors, each transistor can be connected to the first end of at least one storage capacitor among the n storage capacitors, and different transistors are connected to the first ends of different storage capacitors. The gates of at least some transistors are connected to different bit lines, so that the gates of at least some transistors are controlled by different bit lines. The connection relationship between the transistor and the word line can be determined according to the number of word lines, the control method of each transistor, and the read and write method of the storage unit. In other words, no matter how many transistors are set, the connection relationship between the transistor and the word line, the bit line, and the first end of the storage capacitor can be adjusted according to the actual situation, and no strict requirements are made here. Take the example that the gate of the transistor is connected to the word line, the source of the transistor is connected to the bit line, and the drain of the transistor is respectively connected to the first end of n storage capacitors. When the value of n is 1, the storage unit is a single-stage storage unit, which can store 1 bit of data. When the value of n is greater than 1, the storage unit is a multi-stage storage unit, which can store multiple bits of data. Specifically, when writing data, the word line provides a certain voltage to the gate to control the transistor to turn on, and the bit line provides a certain voltage to the first end of the n storage capacitors through the transistor. The second end of one storage capacitor is connected to a certain voltage. Under the action of the appropriate voltage, data "0" or "1" can be written into the storage capacitor. The method of writing data to other storage capacitors is similar and will not be described in detail here. In this way, data can be written into each storage capacitor, so that the storage unit can store n bits of data. The larger the value of n, the more data the storage unit stores, and the larger the storage capacity of the storage unit, and vice versa. When reading data, the transistor is also turned on under the control of the word line. By inputting a suitable voltage to the second end of each storage capacitor in turn, the current generated by the storage capacitor can flow into the bit line through the transistor. By detecting the current in the bit line, the data written in each storage capacitor can be read in turn, thereby realizing data reading.

[0013] Furthermore, the transistor can be arranged on the side of the stacking structure away from the substrate, or the transistor can be arranged between the stacking structure and the substrate, so that the occupied area of ​​the storage unit can be reduced. Alternatively, the transistor can be arranged in an area outside the area where the stacking structure is located, so that the positive projections of the transistor and the stacking structure on the substrate do not overlap. In this case, the stacking structure including the second conductive layer, the storage layer and the first conductive layer can be referred to as a first stacking structure, and the first stacking structure is used to form a plurality of storage capacitors. Further, when a plurality of storage units are provided, the transistors in different storage units can be stacked along the stacking direction, so that the transistors of each storage unit can be arranged and stacked separately. In this case, the stacking structure including the transistor can be referred to as a second stacking structure, and the second stacking structure is used to form a plurality of transistors belonging to different storage units. The first stacking structure and the second stacking structure can be arranged side by side on the substrate, and then the electrical connection between the transistor and the corresponding storage capacitor is realized through wiring, so as to realize the function of each storage unit, and it is also beneficial to reduce the occupied area. Among them, the transistor can be a top-gate transistor or a bottom-gate transistor, which can be specifically arranged according to actual needs and is not limited here.

[0014] For example, the first conductive layer and the second conductive layer described above can be made of conductive materials, such as but not limited to: conductive metals, conductive metal oxides or conductive alloys, and the materials used to make the first conductive layer and the second conductive layer can be the same or different. The insulating layer can be made of insulating materials, such as but not limited to: inorganic insulating materials or organic insulating materials.

[0015] In the second aspect, an embodiment of the present application also provides a method for manufacturing a storage unit, comprising: alternately stacking at least one insulating layer and at least one first conductive layer to form a stacked structure; etching the stacked structure to form a hole that penetrates the stacked structure along the stacking direction, and the sidewall of the hole is concave-convex; depositing a storage layer at least on the sidewall of the hole; depositing a second conductive layer on the storage layer, so that the storage layer is at least arranged between the second conductive layer and the stacked structure, and the orthographic projections of the storage layer, the second conductive layer and at least part of the first conductive layer on a first plane perpendicular to the stacking direction overlap. In this way, the storage layer and the second conductive layer can be inserted into the stacked structure along the direction of the aperture, so that at least part of the first conductive layer and the second conductive layer not only have opposite faces in the first direction, but also have opposite faces in the non-first direction, thereby increasing the opposite area between the first conductive layer and the second conductive layer, and thereby increasing the area of ​​the storage capacitor formed by the first conductive layer, the storage layer and the second conductive layer, thereby increasing the read and write charges of the storage unit, avoiding the problem of less read and write charges caused by a smaller opposite area of ​​the storage capacitor when the thickness of the first conductive layer is smaller, thereby reducing the read and write errors caused by less read and write charges and improving the read and write accuracy of the storage unit.

[0016] Exemplarily, when forming a hole that penetrates the stacked structure along the stacking direction, the following process may be included: etching the stacked structure to form a vertical hole that penetrates the stacked structure along the stacking direction and has a smooth sidewall; processing the vertical hole to form a hole with a concave-convex sidewall. That is, firstly, a vertical hole is formed in the stacked structure, and the sidewall of the vertical hole is a smooth surface, not concave-convex, and then the vertical hole is processed accordingly to form a hole with a concave-convex sidewall, so that a hole with a concave-convex sidewall can be obtained through step-by-step operations, and the difficulty of making the hole can also be reduced.

[0017] Among them, the following methods may be used to process the vertical hole to form a hole with a concave-convex side wall:

[0018] Method 1: using etching technology (such as but not limited to wet etching technology or dry etching technology) to form a hole with a concave-convex sidewall. The specific method may include: etching the sidewall of the vertical hole by etching technology and using a suitable etchant to etch away at least a portion of the first conductive layer or at least a portion of the insulating layer, so that the sidewall is concave-convex, thereby forming a hole with a concave-convex sidewall. Wherein, when etching at least a portion of the first conductive layer, an isotropic etching method may be used for etching, so that at least a portion of the first conductive layer is recessed relative to the adjacent insulating layer in the direction along the aperture of the hole, and the end surface of at least a portion of the first conductive layer facing the hole is non-planar, thereby achieving the overlap of the orthographic projections of the storage layer, the second conductive layer and at least a portion of the first conductive layer on the first plane. When etching at least part of the insulating layer, anisotropic etching or isotropic etching can be used for etching, so that at least part of the first conductive layer has a protrusion relative to the adjacent insulating layer in the aperture direction. Since the first conductive layer has a protrusion, the orthographic projections of the storage layer, the second conductive layer and at least part of the first conductive layer on the first plane can overlap, and after etching, the end face of the insulating layer facing the hole can be either a plane or a non-plane. It should be understood that isotropic etching refers to an etching method in which different crystallographic planes exhibit the same corrosion rate, so through isotropic etching, the surface after etching is non-planar. Anisotropic etching refers to an etching method in which different crystallographic planes exhibit different corrosion rates, so through anisotropic etching, the surface after etching is planar.

[0019] Method 2: Depositing a conductive end on the side wall of the vertical hole to form a hole with a concave-convex side wall. The specific method may include: using a selective atomic layer deposition method to deposit a conductive end on the end of the first conductive layer exposed in the vertical hole, so that at least part of the first conductive layer has a protrusion relative to the adjacent insulating layer along the aperture of the hole, thereby forming a hole with a concave-convex side wall. The deposited conductive end and the first conductive layer can be made of the same material or different materials, which can be selected according to actual needs and are not limited here.

[0020] Method 3: First, selective atomic layer deposition is used to deposit an insulating end on the end of the insulating layer exposed in the vertical hole, and then an isotropic etching method is used to etch at least part of the first conductive layer using the vertical hole, that is, deposition is performed first and then etching is performed, so that on the basis of forming a hole with a concave-convex sidewall, the end surface of at least part of the first conductive layer facing the hole is non-planar, thereby achieving the overlap of the orthographic projections of the storage layer, the second conductive layer and at least part of the first conductive layer on the first plane. Of course, the isotropic etching method can also be first used to etch at least part of the first conductive layer using the vertical hole, and then the selective atomic layer deposition method is used to deposit the insulating end on the end of the insulating layer exposed in the vertical hole, that is, etching is performed first and then deposition is performed, so the execution order of etching and deposition can be interchanged, and can be specifically designed according to actual needs, which is not limited here.

[0021] Based on this, when forming a hole with a concave-convex side wall, any one of the above-mentioned methods 1 to 3 can be selected according to actual needs, and is not limited here.

[0022] Exemplarily, the first conductive layer, the first insulating layer, the storage layer, and the second conductive layer can be manufactured by physical vapor deposition or chemical vapor deposition. Furthermore, when the memory cell also includes a transistor, no matter where the transistor is disposed, it can be manufactured by a method for manufacturing a transistor well known to those skilled in the art, which will not be described in detail herein.

[0023] In the third aspect, the embodiment of the present application also provides a memory, including: a memory array and a controller coupled to the memory array, the memory array including a plurality of memory cells as described in the first aspect above, the plurality of memory cells being deployed in an array manner; a memory array for storing data; a controller for writing data to the memory array, or reading data from the memory array. In this way, when the memory cell increases the read-write charge and the read-write accuracy, the memory can also increase the read-write charge and the read-write accuracy, thereby improving the performance of the memory. Among them, since the principle of the memory to solve the problem is similar to the principle of the aforementioned memory cell to solve the problem, the implementation and technical effects of the memory can refer to the implementation and technical effects of the aforementioned memory cell, and the repeated parts will not be repeated.

[0024] Exemplarily, the memory also includes: word lines, bit lines, and at least one control line. When each memory cell in the memory array is deployed in an array manner, the memory cells in the same row can be connected to the same word line, and the memory cells in different rows are connected to different word lines, so that different word lines can control the conduction and disconnection of transistors in memory cells in different rows. The memory cells in the same column can be connected to the same bit line, and the memory cells in different columns are connected to different bit lines, so that different bit lines can provide voltage to memory cells in different rows. Each control line is respectively connected to the second end of each storage capacitor of each memory cell, that is, each memory cell is connected to each control line, and the number of control lines set is the same as the number of storage capacitors set in the memory cell, and they are set one by one. Thus, each memory cell can be accurately controlled through word lines and bit lines, and accurate writing and reading of data can be achieved under the action of the voltage provided by each control line.

[0025] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a circuit board and a memory as described in the second aspect above, wherein the memory is arranged on the surface of the circuit board. In this way, when the memory increases the read / write charge and the read / write accuracy, the electronic device including the memory can also increase the read / write charge and the read / write accuracy, thereby improving the performance of the electronic device. Among them, since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned memory, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the aforementioned memory, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a top view structure of a storage unit provided in an embodiment of the present application;

[0029] Figure 4 For along Figure 3 A cross-sectional view shown in the x1-x2 direction;

[0030] Figure 5 For along Figure 3 Another cross-sectional view shown in the x1-x2 direction;

[0031] Figure 6 For along Figure 3 Another cross-sectional view shown in the x1-x2 direction;

[0032] Figure 7 For along Figure 3 Another cross-sectional view shown in the x1-x2 direction;

[0033] Figure 8 For along Figure 3 Another cross-sectional view shown in the x1-x2 direction;

[0034] Fig. 9 A circuit diagram of a storage unit provided in an embodiment of the present application;

[0035] Fig.10 A schematic cross-sectional structure diagram of a storage unit provided in an embodiment of the present application;

[0036] Fig.11 A schematic cross-sectional view of another storage unit provided in an embodiment of the present application;

[0037] Fig.12 A flowchart of a method for manufacturing a storage unit provided in an embodiment of the present application.

[0038] Reference numerals:

[0039] 100-memory, 110-storage array, 120-controller, 200-circuit board, 300-housing, 400-external device, 10-stacked structure, 11-insulating layer, 12-first conductive layer, 20-hole, 20a-vertical hole, 30-storage layer, 31-storage part, 40-second conductive layer, 41-conductive part, 50-substrate, 60-filling layer, a1-body, a2-protruding part, m1-first stacked structure, m2-second stacked structure, T0-transistor, C0-storage capacitor, WL-word line, BL-bit line, V1, V2, V3, Vn-control lines. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0041] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0042] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, the application scenario provided by the embodiments of the present application is first explained below.

[0043] The storage solution provided in the embodiments of the present application can be widely used in devices with storage functions, for example, it can be applied to storage devices with only storage functions, such as memory, and it can also be applied to electronic devices with storage functions and other functions (such as read and write functions). Electronic devices can include various terminal devices and electronic devices, and terminal devices can include but are not limited to: smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (personal computers, PCs), tablet computers, wearable devices, smart broadband, vehicle-mounted devices and other devices. Electronic devices can include but are not limited to: wireless networks, fixed networks, servers and other telecommunications equipment, as well as chip modules and other devices.

[0044] Figure 1 The schematic diagram of the structure of the memory when it is used in an electronic device is shown as an example. Figure 1 The electronic device includes a housing 300 and a circuit board 200 disposed in the housing 300, and a memory 100 is disposed on the circuit board 200. The memory 100 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), flash eprom (FE), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM), as well as new types of memory such as ferroelectric RAM, phase change RAM, magnetic RAM, or resistive RAM. Non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), or flash memory. It should be noted that the memory described herein is intended to include, without being limited to, these and any other suitable types of memory.

[0045] Figure 2 The internal structure diagram of a memory 100 applicable to the embodiments of the present application is exemplarily shown. It should be understood that the illustrated memory 100 is only an example, and the memory 100 may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application-specific integrated circuits.

[0046] like Figure 2 As shown, the memory 100 may include a storage array 110 and a controller 120. The storage array 110 is used to store data, and is a matrix array composed of multiple storage units arranged in rows and columns. Each storage unit can be used to store 1 or more bits of binary data, such as "0" and / or "1". Among them, multiple storage units can be located in different tracks of the same disk, or in different disks, without specific limitation. The controller 120 is used to read or write data in the storage array 110, and is a device with control capabilities. The controller 120 can be connected to the storage array 110, and the connection method can be, for example, a bus connection. The controller 120 may include multiple functional components, such as including but not limited to a driving circuit, a decoding circuit, and an amplifier circuit. These functional components can be set as separate devices, or they can be implemented in one device, or they can be set in at least two devices in any combination, without specific limitation.

[0047] Continue to refer to Figure 2 As shown, the controller 120 can also be connected to an external device 400, which can be, for example, a read / write device or a processor. When reading / writing data, the external device 400 can send a read / write request to the controller 120, and the read / write request carries the row address information and column address information of the target storage unit to be read / written. The controller 120 decodes the row address information in the read / write request to determine the row where the target storage unit is located, and turns on all storage units corresponding to the row where the target storage unit is located by decoding the selection signal, and then decodes the column address information in the read / write request to obtain the column where the target storage unit is located, and then reads the data stored in the target storage unit at the column and sends it to the external device 400, or writes the data to be written sent by the external device 400 into the target storage unit at the column.

[0048] although Figure 2Not shown in the figure, the memory 100 may also include other components, such as a main memory data register (memory data register, MDR) and a main memory address register (memory address register, MAR), etc., which are not described in detail here.

[0049] Figures 3 to 6 The schematic diagram of the structure of the storage unit in the first embodiment provided in the embodiment of the present application is exemplarily shown, referring to Figures 3 to 5 As shown, the storage unit may include: a stacking structure 10, a hole 20 penetrating the stacking structure 10 along the stacking direction (i.e., the z direction), and a storage layer 30 and a second conductive layer 40 filled in the hole 20, wherein the storage layer 30 is at least arranged between the second conductive layer 40 and the stacking structure 10. After the storage layer 30 is formed in the hole 20, the deposited second conductive layer 40 can completely occupy the remaining space in the hole 20, so that the second conductive layer 40 and the storage layer 30 fill the hole 20. Moreover, the plane perpendicular to the z direction is a plane formed by the x direction and the y direction, and the plane can be defined as a first plane. When the stacking structure 10 includes at least one insulating layer 11 and at least one first conductive layer 12 alternately stacked, the orthographic projections of the storage layer 30, the second conductive layer 40 and at least part of the first conductive layer 12 on the first plane overlap. In this way, the storage layer 30 and the second conductive layer 40 can be arranged along the direction of the aperture (i.e., the z direction). Figure 4 and Figure 5 The first conductive layer 12 and the second conductive layer 40 are inserted into the stacked structure 10 so that at least part of the first conductive layer 12 and the second conductive layer 40 are not only directly opposite to each other in the first direction (as shown in the x direction) but also directly opposite to each other in the second direction. Figure 4 In the dashed box n1 in FIG. 1 ), there is also a directly opposite side in the non-first direction (such as Figure 4 As shown in the dotted box n2 in the figure, the facing area of ​​the first conductive layer 12 and the second conductive layer 40 is increased, and then the area of ​​the storage capacitor formed by the first conductive layer 12, the storage layer 30 and the second conductive layer 40 is increased, thereby increasing the read and write charges of the storage unit, avoiding the problem of less read and write charges caused by the smaller facing area of ​​the storage capacitor when the thickness of the first conductive layer 12 is smaller, thereby reducing the read and write errors caused by less read and write charges and improving the read and write accuracy of the storage unit.

[0050] It should be understood that Figure 3 In the embodiment, the first plane is a plane formed by the x-direction and the y-direction. The first direction may be any direction parallel to the first plane, such as the x-direction. Of course, since the hole 20 is provided in the stacked structure 10 and the stacked structure 10 is provided around the hole 20, the first direction may also be the y-direction, and any direction in the first plane except the x-direction and the y-direction. The cross-sectional shape of the stacked structure 10 parallel to the first plane is not limited to Figure 3The circle shown in the figure may also be other shapes, and the circle is used as an example for explanation here. In addition, the orthographic projections of the storage layer 30, the second conductive layer 40, and at least part of the first conductive layer 12 on the first plane overlap, which can be understood as: when the first conductive layer 12 has one layer, the orthographic projections of the first conductive layer 12, the storage layer 30, and the second conductive layer 40 on the first plane overlap; when the first conductive layer 12 has multiple layers, the orthographic projections of part of the first conductive layer 12, the storage layer 30, and the second conductive layer 40 on the first plane overlap, or the orthographic projections of each layer of the first conductive layer 12, the storage layer 30, and the second conductive layer 40 on the first plane overlap. Figure 4 and Figure 5 In the figure, the orthographic projection overlap of each of the first conductive layer 12, the storage layer 30 and the second conductive layer 40 on the first plane is used as an example.

[0051] When the stacked structure 10 is disposed on the substrate 50, the hole 20 may expose a portion of the surface of the substrate 50, and the exposed surface of the substrate 50 may be regarded as the bottom of the hole. The surface of the stacked structure 10 facing the hole 20 may be regarded as the side wall of the hole 20, and the storage layer 30 may be disposed only on the side wall of the hole 20, such as Figure 4 As shown; or the storage layer 30 is not only provided on the sidewall of the hole 20, but also provided at the bottom of the hole (such as Figure 5 The storage layer 30 may be disposed at a position that is specifically set according to actual conditions and is not limited here.

[0052] Furthermore, at least part of the first conductive layer 12 has a protrusion relative to the adjacent insulating layer 11 in the direction along the aperture of the hole 20. That is, if the first conductive layer 12 with the protrusion is called a protruding first conductive layer, the protruding first conductive layer and the end of the adjacent insulating layer 11 facing the hole 20 are also not aligned. The end of the protruding first conductive layer facing the hole 20 protrudes outward and extends into the hole 20, while the end of the insulating layer 11 facing the hole 20 is recessed to form a depression, so that the side wall of the hole 20 is concave and convex, so that the storage layer 30, the second conductive layer 40 and the orthographic projection of the protruding first conductive layer on the first plane overlap. The length L1 of the protrusion along the aperture of the hole 20 is any value between 1nm and 1μm, and there is no strict requirement for the specific length setting, which can be adjusted according to actual needs. Furthermore, the raised first conductive layer may include: a main body a1 and a protruding portion a2 connected to each other. The main body a1 and the protruding portion a2 may be made of the same conductive material or different conductive materials, which may be set according to actual conditions. In addition, the cross-sectional shape of the protruding portion a2 parallel to the second plane may be: a rectangle (such as Figure 4 As shown), round (as Figure 5As shown), ellipse, triangle, trapezoid or other shapes. There is no strict requirement for the specific cross-sectional shape and it can be adjusted according to actual needs.

[0053] In addition, the material of the storage layer 30 may include ferroelectric materials, phase change materials or resistive materials, etc., and the corresponding storage unit may be a ferroelectric storage unit, a phase change storage unit or a resistive storage unit, etc., so that the storage unit in the embodiment of the present application has a wide range of applications. In addition, since the orthographic projections of the storage layer 30, the second conductive layer 40 and at least part of the first conductive layer 12 on the first plane overlap, the overlapping second conductive layer 40 and the first conductive layer 12 can apply stress to the storage layer 30 located between the two in the z direction, and the second conductive layer 40 and the first conductive layer 12 can also apply stress to the storage layer 30 located between the two in the direction perpendicular to the z direction (for example, but not limited to the x direction), so that the stress of the first conductive layer 12 and the second conductive layer 40 on the storage layer 30 is increased, which is conducive to the crystallization of the material in the storage layer 30, thereby facilitating the realization of the storage function of the storage layer 30. For example, when the material of the storage layer 30 includes a ferroelectric material, it is conducive to the formation of a ferroelectric phase in the storage layer 30, thereby facilitating the formation of a ferroelectric storage unit. In addition, since the orthographic projections of the storage layer 30, the second conductive layer 40 and at least part of the first conductive layer 12 on the first plane overlap, an electric field is formed not only in a direction perpendicular to the z direction, but also in other directions such as the z direction, so that the distribution of the electric field is no longer in a single direction but in multiple directions, such as Figure 4 The direction of the electric field is shown by the dotted arrow. In this way, when the material used to make the storage layer 30 includes ferroelectric materials, even if the polarization axis direction in the storage layer 30 is parallel to the stacking direction, the polarization can be reversed, thereby increasing the polarization reversal probability of the ferroelectric material and improving the performance of the ferroelectric memory unit.

[0054] The first conductive layer 12 and the second conductive layer 40 described above can be made of conductive materials, such as but not limited to: conductive metals, conductive metal oxides or conductive alloys, and the materials used to make the first conductive layer 12 and the second conductive layer 40 can be the same or different. The insulating layer 11 can be made of insulating materials, such as but not limited to: inorganic insulating materials or organic insulating materials.

[0055] For example, refer to Figure 6As shown, the storage layer 30 can be divided into a plurality of storage parts 31, the number of storage parts 31 is the same as the number of first conductive layers 12 and they are arranged one by one, and each storage part 31 at least partially wraps the end of the corresponding first conductive layer 12 facing the hole 20; similarly, the second conductive layer 40 can be divided into a plurality of conductive parts 41, the number of conductive parts 41 is the same as the number of storage parts 31 and they are arranged one by one. In this way, the corresponding conductive parts 41, storage parts 31 and first conductive layer 12 can form a conductive-medium-conductive structure (such as Figure 6 As shown in the dotted box n4 in the figure), a storage capacitor is formed, wherein the conductive portion 41 can be regarded as the first end of the storage capacitor, and the first conductive layer 12 can be regarded as the second end of the storage capacitor. Therefore, when the stacked structure 10 includes n (n is a positive integer) layers of the first conductive layer 12, there are correspondingly n storage capacitors, and the conductive portions 41 of the n storage capacitors are connected to each other, so that the first ends of the n storage capacitors are connected to each other and can be connected to the same potential, and the second ends of the n storage capacitors are insulated from each other and can be connected to different potentials. When the first ends of the storage capacitors are connected to the same potential, data can be written to and read from the storage capacitors by connecting different potentials to different second ends. It should be understood that in order to facilitate the clear illustration of the conductive portion 41 and the storage portion 31, in Figure 6 The structures are shown separately in the figure, but this does not mean that these structures are separated in reality. Figure 6 Only a portion in each first conductive layer, a portion in each insulating layer, a portion in the storage layer, and a portion in the second conductive layer are shown.

[0056] Figure 7 The schematic diagram of the structure of the storage unit in the second embodiment provided in the embodiment of the present application is exemplarily shown, referring to Figure 7As shown, the structure of the storage unit in the second embodiment is basically similar to that in the first embodiment, except that: the hole 20 is provided with not only the storage layer 30 and the second conductive layer 40, but also the filling layer 60, wherein the storage layer 30 is at least provided on the side wall of the hole 20, the second conductive layer 40 is provided on the storage layer 30, and the filling layer 60 is provided on the second conductive layer 40, so that the filling layer 60 fills the space in the hole 20 not occupied by the storage layer 30 and the second conductive layer 40, so that the hole 20 can be filled by the storage layer 30, the second conductive layer 40 and the filling layer 60. The filling layer 60 can be made of insulating material or semiconductor material with low conductivity. In this way, the amount of conductive material used when forming the second conductive layer 40 in the hole 20 can be reduced, and when the manufacturing cost of the conductive material is higher than that of the insulating material or the semiconductor material with low conductivity, the manufacturing cost of the storage unit can be reduced. In addition, the similarities between the second embodiment and the storage unit in the first embodiment can be referred to the introduction of the first embodiment, and the repeated parts will not be repeated.

[0057] Figure 8 The schematic diagram of the structure of the storage unit in the third embodiment provided in the embodiment of the present application is exemplarily shown, referring to Figure 8 As shown, the structure of the storage unit in the third embodiment is basically similar to that in the first embodiment, except that at least a portion of the first conductive layer 12 is recessed relative to the adjacent insulating layer 11 along the aperture of the hole 20. Alternatively, the structure of the storage unit in the third embodiment is basically similar to that in the second embodiment, except that at least a portion of the first conductive layer 12 is recessed relative to the adjacent insulating layer 11 along the aperture of the hole 20.

[0058] Reference Figure 8As shown, if the first conductive layer 12 that is recessed relative to the adjacent insulating layer 11 is called a recessed first conductive layer, the recessed first conductive layer is not aligned with the end of the adjacent insulating layer 11 that faces the hole 20, the end of the insulating layer 11 that faces the hole 20 protrudes outward and extends into the hole 20, while the end of the recessed first conductive layer that faces the hole 20 is recessed to form a recess, so that the side wall of the hole 20 is concave-convex. Among them, the end face of the recessed first conductive layer facing the hole 20 can be a non-planar surface, and the cross-sectional shape of the end face on the second plane parallel to the stacking direction (such as the plane formed by the x-direction and the z-direction) can be: semicircular, semi-elliptical, triangular or polygonal, etc., as long as the end face of the recessed first conductive layer facing the hole 20 presents a non-planar surface. In this way, the orthographic projections of the storage layer 30, the second conductive layer 40 and the recessed first conductive layer on the first plane can overlap. Furthermore, the maximum distance L2 between the non-plane and the end face of the adjacent insulating layer 11 facing the hole 20 can be set to any value between 1nm and 1μm. There is no strict requirement for the specific distance setting, and it can be adjusted according to actual needs. In addition, when the insulating layer 11 adjacent to the recessed first conductive layer protrudes outward toward one end of the hole 20, the cross-sectional shape of the protruding portion parallel to the second plane can be: rectangular, circular, elliptical, triangular, trapezoidal or other shapes. There is no strict requirement for the specific cross-sectional shape, and it can be adjusted according to actual needs. It should be understood that Figure 8 It is illustrated by taking the example that each first conductive layer 12 is a recessed first conductive layer.

[0059] For similarities between the storage unit in the third embodiment and the aforementioned first embodiment, please refer to the introduction in the aforementioned first embodiment. For similarities between the storage unit in the third embodiment and the aforementioned second embodiment, please refer to the introduction in the aforementioned second embodiment. The repeated parts will not be repeated here.

[0060] Figures 9 to 11 The schematic diagram of the structure of the storage unit in the fourth embodiment provided in the embodiment of the present application is exemplarily shown, referring to Figures 9 to 11 As shown, Fig. 9 is the circuit diagram of the storage unit, Fig.10 and Fig.11 The fourth embodiment is a cross-sectional view of a memory cell including four storage capacitors. The structure of the memory cell in the fourth embodiment is basically similar to that in the first embodiment. The difference is that the memory cell includes n storage capacitors (such as Fig. 9 In addition to the transistor T0, the transistor T0 may also include a gate connected to the word line WL, a source connected to the bit line BL, a drain connected to the first end of each of the n storage capacitors C0, and a second end of each of the storage capacitors C0 connected to a different control line (such as Fig. 9The transistor T0 may be disposed on a side of the stacked structure 10 away from the substrate 50, as shown in FIG. Fig.10 As shown; or the transistor T0 can be disposed between the stacked structure 10 and the substrate 50; or the transistor T0 can be disposed in a region outside the region where the stacked structure 10 is located, such as Fig.11 As shown, the positive projections of the transistor T0 and the stacking structure 10 on the substrate 50 do not overlap. At this time, the stacking structure 10 including the second conductive layer, the storage layer and the first conductive layer can be referred to as a first stacking structure m1. The first stacking structure m1 is used to form a plurality of storage capacitors. Further, when a plurality of storage cells are provided, the transistors T0 in different storage cells can be stacked along a stacking direction (such as a z direction), so that the transistors T0 of each storage cell can be separately provided and stacked. At this time, the stacking structure including the transistor T0 can be referred to as a second stacking structure m2. The second stacking structure m2 is used to form a plurality of transistors T0 belonging to different storage cells. The first stacking structure m1 and the second stacking structure m2 can be arranged side by side on the substrate 50, as shown. Fig.11 In the second stacking structure m2, the top transistor T0 can form a storage unit with the stacking structure 10 on the right, and the bottom transistor T0 in the second stacking structure m2 can form another storage unit with the stacking structure 10 on the left. Then, the transistor T0 is electrically connected to the corresponding storage capacitor through wiring, so as to realize the function of each storage unit, and it is also beneficial to reduce the occupied area. In addition, the transistor T0 can be a top-gate transistor or a bottom-gate transistor, which can be set according to actual needs and is not limited here. Therefore, based on the transistor T0 and the n storage capacitors C0, the functions of writing and reading data of the storage unit are realized. It should be understood that in order to avoid Fig.11 Too complicated, not in Fig.11 The similarities between the storage unit in the fourth embodiment and the storage unit in the first embodiment can be found in the description of the first embodiment, and the repeated parts will not be described again.

[0061] Fig.12 A schematic diagram exemplarily shows a method for manufacturing a storage unit in a fifth embodiment provided in an embodiment of the present application, referring to Fig.12 As shown, the specific manufacturing process of the storage unit may include:

[0062] Step 1: Fig.12As shown in (a), at least one insulating layer 11 and at least one first conductive layer 12 are alternately stacked to form a stacked structure 10; wherein the number of the first conductive layer 12 and the insulating layer 11 can be set according to actual needs and is not limited here. Moreover, when manufacturing the first conductive layer 12 and the insulating layer 11, physical vapor deposition or chemical vapor deposition can be used to manufacture them.

[0063] Step 2: If Fig.12 As shown in (b), dry etching or wet etching may be used to etch the stacked structure 10 to form a vertical hole 20a that penetrates the stacked structure 10 along the stacking direction and has a smooth sidewall.

[0064] Step 3: If Fig.12 As shown in (c), anisotropic etching or isotropic etching is used to etch at least a portion of the insulating layer 11 using a vertical hole 20a, so that at least a portion of the first conductive layer 12 has a bulge in the aperture direction relative to the adjacent insulating layer 11, forming a hole 20 with a concave-convex sidewall. When the anisotropic etching method is used to etch at least a portion of the insulating layer 11, the end surface of the etched insulating layer 11 is planar; when the isotropic etching method is used to etch at least a portion of the insulating layer 11, the end surface of the etched insulating layer 11 is non-planar. Fig.12 (c) and (d) are both illustrated by taking the case where the end surface of the etched insulating layer 11 is flat.

[0065] Step 4: Fig.12 As shown in (d), a storage layer 30 is deposited at least on the sidewall of the hole 20, and a second conductive layer 40 is deposited on the storage layer 30, so that the orthographic projections of the storage layer 30, the second conductive layer 40 and at least a portion of the first conductive layer 12 on a first plane perpendicular to the stacking direction overlap. The storage layer 30 and the second conductive layer 40 can be manufactured by physical vapor deposition or chemical vapor deposition.

[0066] For example, the second conductive layer 40 can fill the space in the hole 20 not occupied by the storage layer 30, and the storage layer 30 and the second conductive layer 40 are arranged in the hole 20. Alternatively, the second conductive layer 40 does not fill the space in the hole 20 not occupied by the storage layer 30, and the filling layer is formed after the second conductive layer 40 is formed, so that the filling layer can fill the space in the hole 20 not occupied by the storage layer 30 and the second conductive layer 40, so that the storage layer 30, the second conductive layer 40 and the filling layer are arranged in the hole 20. Fig.12 (d) in the figure is illustrated by taking the second conductive layer 40 filling up the space in the hole 20 that is not occupied by the storage layer 30 as an example.

[0067] In this way, the storage layer 30 and the second conductive layer 40 can be inserted into the stacked structure along the direction of the aperture, so that at least part of the first conductive layer 12 and the second conductive layer 40 not only face each other in the first direction, but also face each other in the non-first direction, thereby increasing the facing area of ​​the first conductive layer 12 and the second conductive layer 40, and thereby increasing the area of ​​the storage capacitor formed by the first conductive layer 12, the storage layer 30 and the second conductive layer 40, thereby increasing the read and write charges of the storage unit, avoiding the problem of less read and write charges caused by a smaller facing area of ​​the storage capacitor when the thickness of the first conductive layer 12 is smaller, thereby reducing the read and write errors caused by less read and write charges and improving the read and write accuracy of the storage unit.

[0068] In the method for manufacturing a storage unit in the sixth embodiment provided in the embodiment of the present application, the sixth embodiment is basically similar to the manufacturing method in the fifth embodiment, except that: step 3 in the fifth embodiment is adjusted to: using an isotropic etching method, etching at least part of the first conductive layer using a vertical hole, so that at least part of the first conductive layer is recessed relative to the adjacent insulating layer in the direction along the aperture of the hole, and the end surface of at least part of the first conductive layer facing the hole is non-planar, forming a hole with a concave-convex sidewall. In this way, by etching at least part of the first conductive layer, a hole with a concave-convex sidewall can also be formed, which is conducive to realizing that the storage layer and the second conductive layer can be inserted into the stacked structure along the direction of the aperture, increasing the area of ​​the storage unit, thereby increasing the read and write charge of the storage capacitor, and reducing the read and write error of the storage unit. It should be understood that the similarities between the sixth embodiment and the manufacturing method in the fifth embodiment can be found in the introduction of the fifth embodiment, and the repeated parts will not be repeated.

[0069] In the manufacturing method of the storage unit in the seventh embodiment provided in the embodiment of the present application, the seventh embodiment is basically similar to the manufacturing method in the fifth embodiment, except that: the step 3 in the fifth embodiment is adjusted to: using the selective atomic layer deposition method, depositing the conductive end to the end of the first conductive layer exposed in the vertical hole, so that at least part of the first conductive layer has a bulge relative to the adjacent insulating layer in the direction along the aperture of the hole, thereby forming a hole with a concave-convex sidewall. Among them, the deposited conductive end and the manufacturing material of the first conductive layer can be the same or different, and can be selected according to actual needs, which is not limited here. In this way, by depositing the conductive end to the end of at least part of the first conductive layer, a hole with a concave-convex sidewall can also be formed, which is conducive to realizing that the storage layer and the second conductive layer can be inserted into the stacked structure along the direction of the aperture, increasing the area of ​​the storage unit, and then increasing the read and write charge of the storage capacitor, and reducing the read and write error of the storage unit. It should be understood that the similarities between the seventh embodiment and the manufacturing method in the fifth embodiment can be referred to the introduction in the fifth embodiment, and the repeated parts will not be repeated.

[0070] In the manufacturing method of the storage unit in the eighth embodiment provided by the embodiment of the present application, the eighth embodiment is basically similar to the manufacturing method in the fifth embodiment, except that: the step 3 in the fifth embodiment is adjusted to: firstly, selective atomic layer deposition is used to deposit the insulating end to the end of the insulating layer exposed in the vertical hole, and then the isotropic etching method is used to etch at least part of the first conductive layer using the vertical hole, that is, deposition is performed first and then etching is performed, so that on the basis of forming a hole with a concave-convex sidewall, the end surface of at least part of the first conductive layer facing the hole is non-planar, so that the orthographic projection of the storage layer, the second conductive layer and at least part of the first conductive layer on the first plane overlap. Of course, the isotropic etching method can also be first used to etch at least part of the first conductive layer using the vertical hole, and then the selective atomic layer deposition method is used to deposit the insulating end to the end of the insulating layer exposed in the vertical hole, that is, etching is performed first and then deposition is performed, so the execution order of etching and deposition can be interchanged, and can be specifically designed according to actual needs, which is not limited here. In this way, a hole with a concave-convex sidewall can also be formed, which is conducive to inserting the storage layer and the second conductive layer into the stacked structure along the direction of the hole diameter, increasing the area of ​​the storage unit, thereby increasing the read and write charge of the storage capacitor and reducing the read and write error of the storage unit. It should be understood that the similarities between the eighth embodiment and the manufacturing method in the fifth embodiment can be found in the introduction of the fifth embodiment, and the repeated parts will not be repeated.

[0071] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A storage unit, characterized in that: include: A stacked structure, the stacked structure comprising at least one insulating layer and at least one first conductive layer alternately stacked; A hole penetrating the stacking structure along the stacking direction; The hole is filled with a second conductive layer; and a storage layer at least disposed between the second conductive layer and the stacked structure; The storage layer, the second conductive layer and at least a portion of the first conductive layer overlap in their orthographic projections on a plane perpendicular to the stacking direction.

2. The storage unit according to claim 1, characterized in that At least a portion of the first conductive layer is recessed relative to the adjacent insulating layer in a direction along the aperture of the hole; An end surface of the first conductive layer that is recessed relative to the adjacent insulating layer and faces the hole is non-planar.

3. The storage unit according to claim 2, characterized in that The maximum distance between the non-planar surface and an end surface of the adjacent insulating layer facing the hole is any value between 1 nm and 1 μm.

4. The storage unit according to claim 1, wherein: At least a portion of the first conductive layer has a protrusion relative to the adjacent insulating layer in a direction along the aperture of the hole.

5. The storage unit according to claim 4, characterized in that The length of the protrusion along the pore diameter direction of the pore is any value between 1 nm and 1 μm.

6. The storage unit according to any one of claims 1 to 5, characterized in that: The storage layer is made of a material including a ferroelectric material, a phase change material or a resistive material.

7. A method for manufacturing a storage unit, characterized in that: include: Alternately stacking at least one insulating layer and at least one first conductive layer to form a stacked structure; Etching the stacked structure to form a hole penetrating the stacked structure along a stacking direction, so that a surface of the stacked structure facing the hole is concave-convex; depositing a storage layer at least within the hole; A second conductive layer is deposited on the storage layer, so that the storage layer is at least arranged between the second conductive layer and the stacking structure, and the storage layer, the second conductive layer and at least part of the first conductive layer overlap in their orthographic projections on a plane perpendicular to the stacking direction.

8. The method according to claim 7, characterized in that: Etching the stack structure to form a hole penetrating the stack structure along a stacking direction, comprising: Etching the stack structure to form a vertical hole along the stack direction and penetrating the stack structure, wherein the surface of the stack structure facing the vertical hole is a smooth surface; The vertical hole is processed so that the surface of the stacked structure facing the processed vertical hole is concave-convex, thereby forming the hole.

9. The method of claim 8, wherein: The vertical hole is processed, including: At least a portion of the first conductive layer or at least a portion of the insulating layer is etched in the vertical hole.

10. The manufacturing method according to claim 9, characterized in that: Etching at least a portion of the first conductive layer in the vertical hole comprises: An isotropic etching method is adopted to etch at least a portion of the first conductive layer in the vertical hole.

11. The method according to claim 9, characterized in that: Etching at least a portion of the first insulating layer in the vertical hole comprises: An anisotropic etching method or an isotropic etching method is adopted to etch at least a portion of the first insulating layer in the vertical hole.

12. The method according to claim 8, characterized in that: The vertical hole is processed, including: A conductive terminal is deposited on the end of the first conductive layer exposed in the vertical hole.

13. A memory, characterized in that: include: A storage array and a controller coupled to the storage array, wherein the storage array comprises a plurality of storage units according to any one of claims 1 to 6, and the plurality of storage units are deployed in an array manner; The storage array is used to store data; The controller is used to write data into the storage array or read data from the storage array.

14. An electronic device, characterized in that: include: A circuit board and a memory as claimed in claim 13, wherein the memory is arranged on a surface of the circuit board.

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