Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A dielectric film contacting the field plate electrode is formed between the field plate electrode and the gate electrode, and a recess is formed at an upper surface of the dielectric film and between the drain region and the gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-112391 filed on Jul. 7, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a manufacturing technology thereof. For example, the present invention is applicable to a technology effective for a semiconductor device having a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) and a manufacturing technology thereof. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-50048

[0006] Patent Document 1 discloses a technology for improving the performance of a semiconductor device including an LDMOSFET. Summary of the invention

[0007] For example, LDMOSFET is known as a power device that can be mixed with CMOSFET (complementary MOSFET). Power devices require an increase in breakdown voltage and a decrease in on-resistance, and the two are in a trade-off relationship. Therefore, LDMOSFET, as a power device in power devices, also needs to improve the increase in breakdown voltage and the decrease in on-resistance.

[0008] In one embodiment, the semiconductor device has a dielectric film contacting the field plate electrode between the field plate electrode and the gate electrode, and the dielectric film has a recess at the upper surface of the dielectric film between the drain region and the gate electrode to reduce the distance between the field plate electrode and the lower end of the gate electrode. Moreover, a portion of the field plate electrode is buried in the recess.

[0009] In one embodiment, a method of manufacturing a semiconductor device includes the step of forming a dielectric film to contact a portion of an upper surface of a gate electrode, a sidewall spacer, and a semiconductor substrate, and in this step, the dielectric film is formed by using a normal pressure CVD method or a plasma CVD method.

[0010] According to one embodiment, the performance of a semiconductor device including an LDMOSFET can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view showing the structure of a semiconductor device including an LDMOSFET.

[0012] Figure 2is an enlarged view showing the configuration between the lower end of the field plate electrode and the gate electrode.

[0013] Figure 3 is a diagram schematically explaining the difference between dishing and surface roughness of a dielectric film.

[0014] Figure 4 1 and 2 are diagrams showing manufacturing steps of the semiconductor device in the embodiment.

[0015] Figure 5 It shows Figure 4 A diagram of subsequent manufacturing steps of a semiconductor device.

[0016] Figure 6 It shows Figure 5 A diagram of subsequent manufacturing steps of a semiconductor device.

[0017] Figure 7 It shows Figure 6 A diagram of subsequent manufacturing steps of a semiconductor device.

[0018] Figure 8 It shows Figure 7 A diagram of subsequent manufacturing steps of a semiconductor device.

[0019] Fig. 9 It shows Figure 8 A diagram of subsequent manufacturing steps of a semiconductor device.

[0020] Fig.10 It shows Fig. 9 A diagram of subsequent manufacturing steps of a semiconductor device.

[0021] Fig.11A : is a graph showing the "inclined area" existing in the depression and the "depression amount" of the depression.

[0022] Fig. 11B is a graph showing the relationship between the amount of dishing and the breakdown voltage.

[0023] Fig.12 : is a plan view showing a schematic configuration of a semiconductor device in a first modified example.

[0024] Fig.13 It is along Fig.12 A cross-sectional view of the semiconductor device taken along line AA.

[0025] Fig.14 It is along Fig.12 A cross-sectional view of the semiconductor device taken along line BB.

[0026] Fig.15 It shows Fig.14 A magnified view of a portion of .

[0027] Fig.16 is an enlarged view showing a configuration between the field plate electrode and the lower end of the gate electrode in the second modified example.

[0028] Fig.17 is an enlarged view showing a configuration between the field plate electrode and the lower end of the gate electrode in the third modified example.

[0029] Fig.18 : is an enlarged view showing the configuration between the field plate electrode and the lower end of the gate electrode in the fourth modified example.

[0030] Fig.19 is a plan view showing a schematic configuration of a semiconductor device in a fifth modified example.

[0031] Fig. 20A and 20B is an enlarged view showing the arrangement between the field plate electrode and the sidewall spacer. DETAILED DESCRIPTION

[0032] In all the drawings for explaining the embodiments, the same construction is denoted by the same reference numerals in principle, and repeated description thereof is omitted. Note that even a plan view may be hatched for clarity.

[0033] Practicality of field plate electrodes

[0034] For example, LDMOSFET has a source region and a drain region formed in a semiconductor substrate and a gate electrode disposed on the semiconductor substrate via a gate dielectric film. LDMOSFET has a characteristic that the distance between the gate electrode and the drain region is greater than the distance between the gate electrode and the source region.

[0035] This allows the width of the depletion layer extending from the drain region to be increased when the LDMOSFET is turned off. This can relax the electric field in the depletion layer. Therefore, the breakdown voltage of the LDMOSFET can be increased.

[0036] On the other hand, LDMOSFET also needs to reduce the on-resistance of LDMOSFET. For example, in order to reduce the on-resistance, it is considered to increase the impurity concentration of the drift region. However, if the impurity concentration in the drift region increases, the depletion layer is less likely to extend from the drain region. And the interval between the equipotential lines in the depletion layer decreases, and the electric field increases. Therefore, if the impurity concentration in the drift region is increased to reduce the on-resistance, the breakdown voltage is reduced.

[0037] Therefore, a field plate electrode is formed on the LDMOSFET to increase the breakdown voltage while reducing the on-resistance. Specifically, the field plate electrode is formed on the upper surface of the semiconductor substrate to cover a portion of the gate electrode, and a reference potential (0V) is supplied to the field plate electrode. The field plate electrode can widen the interval between the equipotential lines in the drift region caused by the potential difference between the source region and the drain region, and the electric field in the drift region is relaxed. Thus, the breakdown voltage can be increased by forming a field plate electrode on the LDMOSFET. Therefore, the LDMOSFET with a field plate electrode can ensure the breakdown voltage while reducing the on-resistance.

[0038] Inventor's new discovery

[0039] When increasing the impurity concentration of the drift region to reduce the on-resistance, simply forming a field plate electrode may not be sufficient from the perspective of improving the breakdown voltage. The inventors have newly discovered that it is necessary to design a way to improve the breakdown voltage.

[0040] Specifically, even if the field plate electrode is formed on the LDMOSFET, there is a risk that the breakdown voltage cannot be ensured depending on the distance between the field plate electrode and the lower end of the gate electrode. This is because when the impurity concentration increases, the interval between the equipotential lines decreases, and the equipotential lines are likely to enter between the field plate electrode and the lower end of the gate electrode. And the entry of the equipotential lines between the field plate electrode and the lower end of the gate electrode means that the interval between the equipotential lines decreases and the electric field strength increases. Therefore, for example, the electric field concentration occurring at the lower end of the gate electrode causes the breakdown voltage at this lower end of the gate electrode to decrease. Therefore, the inventors have found that when the impurity concentration of the drift region increases, there is a risk that the effect of increasing the breakdown voltage (electric field relaxation effect) by the field plate electrode cannot be fully obtained.

[0041] Therefore, in the present embodiment, in the LDMOSFET with the field plate electrode, attention is paid to the distance between the field plate electrode and the lower end of the gate electrode, and the breakdown voltage of the LDMOSFET with the field plate electrode is improved. The technical idea in the present embodiment will be described below.

[0042] Basic concepts in the embodiments

[0043] The basic concept in this embodiment is to reduce the distance between the field plate electrode and the lower end of the gate electrode. Even if the interval between the equipotential lines in the drift region is reduced by increasing the impurity concentration of the drift region, it becomes difficult for the equipotential lines to enter between the field plate electrode and the lower end of the gate electrode. The difficulty of the equipotential lines entering means that the interval between the equipotential lines can be suppressed in the interval between the field plate electrode and the lower end of the gate electrode. Therefore, the basic concept can suppress the increase in the electric field strength between the field plate electrode and the lower end of the gate electrode. Thus, the basic concept can suppress the reduction in breakdown voltage caused by the electric field concentration at the lower end of the gate electrode. Therefore, the basic concept can improve the performance of semiconductor devices including LDMOSFET.

[0044] When implementing the above basic concept, it is necessary to consider the influence on the characteristics of devices such as CMOSFET mixed with LDMOSFET. That is, LDMOSFET has a structure suitable for CMOSFET mixed with LDMOSFET. And, the basic concept can be implemented in a semiconductor device in which LDMOSFET and CMOSFET are mixed, while minimizing the influence on the characteristics of CMOSFET.

[0045] For example, it is considered to reduce the width of the sidewall spacer formed on the side surface of the gate electrode by adding a manufacturing step. Accordingly, the distance between the field plate electrode and the lower end of the gate electrode can be reduced. However, the CMOSFET also has a sidewall spacer, and the width of the sidewall spacer of the CMOSFET is also reduced. The reduction in the width of the sidewall spacer of the CMOSFET may cause a change in the characteristics of the CMOSFET.

[0046] Therefore, in this embodiment, when the basic concept is implemented, the influence on the characteristics of the CMOSFET mixed with the LDMOSFET is minimized. Next, an embodiment mode for implementing the above basic concept will be described, taking into account the minimization of the influence on the characteristics of the CMOSFET.

[0047] Embodiment Mode

[0048] First, the concept of the embodiment mode will be explained.

[0049] For example, the concept of the embodiment mode is that when a dielectric film contacting the field plate electrode exists between the field plate electrode and the gate electrode, a recess is formed at the upper surface of the dielectric film and between the drain region and the gate electrode (between the field plate electrode and the gate electrode). In addition, a portion of the field plate electrode is buried in the recess. This allows the distance between the lower ends of the field plate electrode and the gate electrode to be reduced.

[0050] Next, details of an embodiment mode based on the above-mentioned concept will be explained.

[0051] The structure of semiconductor devices

[0052] Figure 1 is a cross-sectional view showing the structure of a semiconductor device including LDMOSFET 1 .

[0053] LDMOSFET 1 includes a semiconductor substrate SUB, an epitaxial layer EPI, a p-type well PWL, a gate dielectric film GOX, a gate electrode GE, a sidewall spacer SW, a source region SR, a drain region DR, an offset drain region ODR, a dielectric film 100 , a field plate electrode FP, and a body contact region BC.

[0054] like Figure 1 As shown, an epitaxial layer EPI is formed on a semiconductor substrate SUB. The semiconductor substrate SUB is formed, for example, of single crystal silicon into which n-type impurities (donors) such as arsenic (As) are introduced. The epitaxial layer EPI is also formed of single crystal silicon into which n-type impurities are introduced. The laminate formed by the semiconductor substrate SUB and the epitaxial layer EPI can be referred to as a substrate 1S.

[0055] The epitaxial layer EPI is used as a drift region. The impurity concentration of the epitaxial layer EPI is lower than the impurity density of the semiconductor substrate SUB.

[0056] Next, a p-type well PWL is formed as a p-type semiconductor region in the upper portion of the epitaxial layer EPI. This p-type well PWL is also called a p-type body region. When the LDMOSFET 1 is turned off, the p-type well PWL serves as a punch-through stopper that suppresses "punch-through". When the depletion layer reaches the source region SR from the drain region DR, "punch-through" occurs.

[0057] Subsequently, a gate electrode GE is formed on the substrate 1S via a gate dielectric film GOX. The gate dielectric film GOX is formed of, for example, a silicon oxide film. The gate electrode GE is formed of, for example, a polysilicon film and a metal silicide SL formed on the upper surface of the polysilicon film. A sidewall spacer SW is formed of, for example, a silicon oxide film on the side surface of the gate electrode GE.

[0058] The source region SR and the offset drain region ODR are formed in the epitaxial layer EPI. The source region SR and the offset drain region ODR are separated from each other and sandwich a channel formation region formed at the upper surface of the p-type well PWL.

[0059] The channel formation region corresponds to a region directly below the gate electrode GE. In this channel formation region, when a gate voltage equal to or higher than a threshold voltage is applied to the gate electrode GE, a channel formed by an inversion layer is formed.

[0060] A metal silicide SL is formed on an upper surface of the source region SR. In the present specification, the metal silicide SL is also included in the source region SR. A drain region DR is formed in the epitaxial layer EPI to contact the offset drain region ODR. A metal silicide SL is formed on an upper surface of the drain region DR. In the present specification, the metal silicide SL is also included in the drain region DR. The depth of the drain region DR is shallower than the depth of the offset drain region ODR. Moreover, the impurity concentration of the drain region DR is higher than the impurity concentration of the offset drain region ODR.

[0061] In the LDMOSFET 1, an offset drain region ODR is formed between the drain region DR and the gate electrode GE. Thus, in the LDMOSFET 1, a distance between the gate electrode GE and the drain region DR is greater than a distance between the gate electrode GE and the source region SR. That is, in the LDMOSFET 1, the source region SR and the drain region DR are formed asymmetrically with respect to the gate electrode GE.

[0062] This allows the depletion layer to sufficiently extend from the drain region DR to the offset drain region ODR when the LDMOSFET 1 is turned off, thereby increasing the breakdown voltage between the source region SR and the drain region DR. That is, the offset drain region ODR is formed to ensure a sufficient breakdown voltage.

[0063] Next, if Figure 1 As shown, the dielectric film 100 is formed to contact the substrate 1S, the sidewall spacer SW, and a portion of the upper surface of the gate electrode GE. The dielectric film 100 is formed of, for example, a silicon oxide film. Then, a field plate electrode FP is formed on the dielectric film 100 so as to contact the dielectric film 100. That is, the field plate electrode FP is continuously formed on a portion of the gate electrode GE, the sidewall spacer SW formed on the side surface of the gate electrode GE facing the drain region DR, and the offset drain region ODR. The field plate electrode FP is formed of, for example, a metal silicide film.

[0064] An interlayer dielectric film IL is formed to cover the LDMOSFET 1. The interlayer dielectric film IL is formed of, for example, a silicon oxide film. Figure 1 As shown, a plug PLG1 reaching the drain region DR and a plug PLG2 reaching the source region SR are formed in the interlayer dielectric film IL.

[0065] Here, a body contact region BC formed of a p-type semiconductor region is formed in the substrate 1S to contact the source region SR. The plug PLG2 is electrically connected not only to the source region SR but also to the body contact region BC. Therefore, in the LDMOSFET1, the source region SR and the body contact region BC have the same potential. Since the body contact region BC is connected to the p-type well PWL, the p-type well PWL and the source region SR are connected at the same potential. Therefore, according to the LDMOSFET 1, a potential difference is unlikely to occur between the p-type well PWL and the source region SR. This can suppress the parasitic npn bipolar transistor formed by the source region SR, the p-type well region PWL and the semiconductor substrate SUB (epitaxial layer EPI) from being turned on. That is, the LDMOSFET1 can suppress the "latch-up" caused by the parasitic bipolar transistor.

[0066] The LDMOSFET 1 is configured as described above.

[0067] Next, a detailed configuration between the field plate electrode FP and the lower end of the gate electrode GE will be described. Figure 2 1 is an enlarged view showing a configuration between the field plate electrode FP and the lower end of the gate electrode GE. Hereinafter, the dielectric film 100 located below the field plate electrode FP is particularly described.

[0068] exist Figure 2 In the embodiment, the dielectric film 100 has a first portion P1 contacting the substrate 1S, a second portion P2 contacting the sidewall spacer SW, and a third portion P3 contacting a portion of the upper surface of the gate electrode GE. Moreover, a recess 200 is formed at a connection point between the upper surface of the first portion P1 and the upper surface of the second portion P2. A portion of the field plate electrode FP is buried in the recess 200. In the LDMOSFET 1 configured as described above, as shown in FIG. Figure 2 As shown, the "distance B" (first distance) between the upper surface of the substrate 1S and the recess 200 is greater than the "thickness A" of the gate dielectric film GOX. In this case, the "distance B" is the shortest distance between the upper surface of the substrate 1S and the lower end of the recess 200 in a direction perpendicular to the upper surface of the substrate 1S.

[0069] Here, the upper surface of the dielectric film 100 has concavities and convexities corresponding to the surface roughness. In this regard, the concavity 200 formed at the connection point between the upper surface of the first portion P1 and the upper surface of the second portion P2 of the dielectric film 100 is larger than the above-mentioned concavities and convexities, and the concavity 200 is distinguished from the above-mentioned concavities and convexities.

[0070] In the following, reference will be made to Figure 3 The difference between the concavity 200 and the concavity and convexity corresponding to the surface roughness is described.

[0071] Figure 3is a graph showing the difference between the surface roughness of the recess 200 and the dielectric film 100. Figure 3 In the embodiment, the recess 200 is formed at the connection point between the first portion P1 and the second portion P2 of the dielectric film 100. Figure 3 As shown, a concavoconvex corresponding to the surface roughness is formed on the upper surface of the first portion P1 of the dielectric film 100. The distance "S" (first difference) between the highest position of the concavoconvex and the lowest position of the concavoconvex is greater than the difference "H1" (second difference) between the highest position and the lowest position of the concavoconvex. Specifically, the distance "S" is greater than 2nm. In this way, in the embodiment mode, the concavoconvex 200 is clearly distinguished from the concavoconvex corresponding to the surface roughness.

[0072] Method for manufacturing semiconductor device

[0073] Next, a method of manufacturing a semiconductor device will be described with reference to the drawings.

[0074] First, if Figure 4 As shown, a p-type well PWL, an offset drain region ODR, and a drain region DR are formed in the substrate 1S, and a gate electrode GE is formed on the upper surface of the substrate 1S via a gate dielectric film GOX. Then, a sidewall spacer SW is formed on the side surface of the gate electrode GE. Next, as shown in FIG. Figure 5 As shown, the dielectric film 100 is formed to cover the upper surface of the substrate 1S (the offset drain region ODR and the drain region DR), the sidewall spacers SW, and the gate electrode GE.

[0075] The dielectric film 100 is formed, for example, by using a normal pressure CVD (chemical vapor deposition) method or a plasma CVD method. The film forming conditions when the dielectric film 100 is formed using the normal pressure CVD method are as follows. For example, the film forming temperature is 380 degrees Celsius. The source gases are silane gas (SiH4) and oxygen (O2). In addition, the film forming pressure is 760 Torr (1 Torr = 133.32 Pa).

[0076] On the other hand, the film forming conditions when the dielectric film 100 is formed using the plasma CVD method are as follows. For example, the film forming temperature is 400 degrees Celsius. The source gas is TEOS and oxygen. In addition, the film forming pressure is 3Pa.

[0077] like Figure 5As shown, the dielectric film 100 in this embodiment mode includes a first portion P1 contacting the substrate 1S, a second portion P2 contacting the sidewall spacer SW, and a third portion P3 contacting the upper surface of the gate electrode GE. By using a normal pressure CVD method or a plasma CVD method, the thickness uniformity of the dielectric film 100 is reduced, and a recess 200 is formed at a connection point between the upper surface of the first portion P1 and the upper surface of the second portion S2. That is, in the embodiment mode, the recess 200 is intentionally formed.

[0078] Next, if Figure 6 As shown, the dielectric film 100 is patterned using a photolithography technique and an etching technique. Therefore, the dielectric film 100 covers a portion of the upper surface of the gate electrode GE and exposes another portion of the upper surface of the gate electrode GE. By patterning the dielectric film, the dielectric film 100 is formed of a first portion P1, a second portion P2, and a third portion P3 that contact a portion of the upper surface of the gate electrode GE. Then, as shown in FIG. Figure 7 As shown, a metal silicide SL is formed on the upper surface of the substrate 1S and another portion of the upper surface of the gate electrode GE exposed from the dielectric film 100 using a silicide technology.

[0079] Next, if Figure 8 As shown in FIG. 1 , a tungsten silicide film SF is formed to cover the dielectric film 100 and the gate electrode GE by using a sputtering method, for example. Then, as shown in FIG. Fig. 9 As shown, the tungsten silicide film SF is patterned using photolithography and etching techniques to form a field plate electrode FP. At this time, a portion of the field plate electrode FP is buried in the recess 200. In this way, the LDMOSFET 1 can be formed.

[0080] Afterwards, if Fig.10 As shown, for example, an interlayer dielectric film IL is formed to cover the LDMOSFET 1 formed on the substrate 1S. The interlayer dielectric film IL is formed of, for example, a silicon oxide film. Then, although not shown, a plug passing through the interlayer dielectric film IL and a wiring connected to the plug are formed. Thus, a semiconductor device including the LDMOSFET 1 in the embodiment mode can be manufactured.

[0081] Features in Implementation Mode

[0082] Next, features in the embodiment mode will be described.

[0083] The first feature of this embodiment mode is that Figure 2As shown, for example, a recess 200 is formed at a connection point between the upper surface of the first portion P1 and the upper surface of the second portion P2 of the dielectric film 100 located below the field plate electrode FP. Therefore, a portion of the field plate electrode FP is buried in the recess 200, and thus a distance "L" between the lower end of the field plate electrode FP and the gate electrode GE may be smaller than a configuration without the recess 200.

[0084] According to this first feature, even if the distance between equipotential lines in the drift region decreases due to an increase in the impurity concentration in the drift region (inside the substrate 1S), Figure 2 The distance "L" shown is also reduced due to the presence of the recess 200. Therefore, it is less likely that the equipotential lines enter between the field plate electrode FP and the lower end of the gate electrode GE. Therefore, the distance between the equipotential lines can be suppressed from decreasing between the field plate electrode FP and the lower end of the gate electrode GE. Thus, according to the first feature, even if the impurity concentration of the drift region of the LDMOSFET 1 is increased to reduce the on-resistance of the LDMOSFET 1, the increase in the electric field strength between the field plate electrode FP and the lower end of the gate electrode GE can be suppressed. Thus, the first feature can suppress the reduction in breakdown voltage caused by the electric field concentration at the lower end of the gate electrode GE while reducing the on-resistance of the LDMOSFET 1. In other words, the first feature can improve the reduction in on-resistance and the increase in breakdown voltage, which are in a trade-off relationship with each other. Therefore, the first feature can improve the performance of the semiconductor device including the LDMOSFET 1.

[0085] As described above, forming the recess 200 in the dielectric film 100 can improve the breakdown voltage of the LDMOSFET 1. In this regard, if the recess 200 is formed, the breakdown voltage can be improved, and thus the shape of the recess 200 is not limited to Figure 2 The shape shown in FIG. 1 is because the technical significance of forming the recess 200 is to reduce the distance "L" between the lower ends of the field plate electrode FP and the gate electrode GE. In other words, by the presence of the recess 200, if the distance "L" is reduced, it is less likely that the equipotential line will enter between the lower ends of the field plate electrode FP and the gate electrode GE.

[0086] On the other hand, the present inventors have clarified that when the size of the recess 200 is changed, a certain difference occurs in the effect of improving the breakdown voltage, so this point will be explained below.

[0087] Fig.11A and 11B is a graph explaining the dependence of the size of the notch on the breakdown voltage. Fig.11A is a diagram showing a “tilted area” present in the depression 200 and a “depression amount” of the depression, and Fig. 11B is a graph showing the relationship between the amount of dishing and the breakdown voltage.

[0088] like Fig.11A The "inclined area" and the "recess amount" of the recess 200 are defined as shown. The "inclined area" corresponds to the horizontal length of the upper surface of the first portion P1, which is inclined relative to the upper surface of the substrate 1S. The "recess amount" corresponds to the distance between the highest position of the upper surface of the first portion P1 and the lower end of the recess in a direction perpendicular to the upper surface of the substrate 1S.

[0089] exist Fig. 11B Graph (1) shows the relationship between the depression amount corresponding to the depression 200 and the breakdown voltage, where "inclined area = 0.03 μm". On the other hand, graph (2) shows the relationship between the depression amount corresponding to the depression 200 and the breakdown voltage, where "inclined area = 0.09 μm".

[0090] like Fig. 11B As shown, the same trend obtained in the graph (1) and the graph (2) will be explained. That is, as the "recess amount" increases, the breakdown voltage increases (first trend), but when the "recess amount" exceeds "0.05 μm", the breakdown voltage decreases (second trend). Here, the increase in the "recess amount" means that the size of the recess 200 increases. Thus, the first trend indicates that as the size of the recess 200 increases, the distance "L" decreases, and the entry of the equipotential line is sufficiently suppressed.

[0091] The increase in the “recess amount” means that the distance between the recess 200 and the upper surface of the substrate 1S, or in other words, the thickness of the dielectric film 100 directly below the recess 200 is reduced. And as the “recess amount” increases, the thickness of the dielectric film 100 directly below the recess 200 decreases compared to the thickness of the gate dielectric film GOX. In this case, it is considered that the portion of the dielectric film 100 directly below the recess 200 with a smaller thickness behaves as a hot spot where the breakdown voltage is reduced. In other words, the second trend indicates that as the size of the recess 200 increases and the thickness of the dielectric film 100 directly below the recess 200 decreases compared to the thickness of the gate dielectric film GOX, the area directly above the recess 200 behaves as a hot spot where the breakdown voltage is reduced.

[0092] In summary, in order to improve the breakdown voltage by forming the recess 200 , it is desirable to increase the size of the recess 200 (“recess amount”) so that the thickness of the dielectric film 100 directly below the recess 200 is not reduced compared to the thickness of the gate dielectric film GOX.

[0093] Then, the second feature of this embodiment mode is that, for example, Figure 5 As shown in FIG. 1 , the dielectric film 100 is formed by using a normal pressure CVD method or a plasma CVD method. By changing the method of forming the dielectric film 100 from the low pressure CVD method to the normal pressure CVD method or the plasma CVD method, as shown in FIG. Figure 5As shown, a recess 200 may be formed at a connection point between an upper surface of the first portion P1 and an upper surface of the second portion P2 of the dielectric film 100 .

[0094] The film formed by the normal pressure CVD method or the plasma CVD method has lower thickness uniformity than the film formed by the low pressure CVD method. Figure 5 The recess 200 shown may be formed at a connection point between an upper surface of the first portion P1 and an upper surface of the second portion P2 of the dielectric film 100 .

[0095] For example, generally, it is desired that the dielectric film 100 is a conformal film having high thickness uniformity. Therefore, as a method of forming the dielectric film 100, a low-pressure CVD method is used.

[0096] In this regard, the present inventors have focused on the point that if the dielectric film 100 having low thickness uniformity is formed, rather than boldly forming the conformal dielectric film 100 having high thickness uniformity, the recess 200 is inevitably formed. Specifically, the present inventors have noticed that a film formed by the normal-pressure CVD method or the plasma CVD method has lower thickness uniformity than a film formed by the low-pressure CVD method, and have actively used the normal-pressure CVD method or the plasma CVD method, which are not generally used as a method for forming the dielectric film 100.

[0097] For example, when the normal pressure CVD method is used, in order to easily form the recess 200 in the dielectric film 100, it is desirable to lower the film formation temperature (about 380 degrees Celsius or higher and 420 degrees Celsius or lower). On the other hand, when the plasma CVD method is used, in order to easily form the recess 200 in the dielectric film 100, it is desirable to (1) lower the film formation temperature (about 380 degrees Celsius or higher and 420 degrees Celsius or lower), (2) increase the pressure (about 3 Pa or higher and 4 Pa ​​or lower), or (3) change the balance between high frequency and low frequency (high frequency: about 13 MHz or higher and 14 MHz or lower, low frequency: about 250 kHz or higher and 400 kHz or lower).

[0098] According to the second feature in the above-described embodiment, the recess 200 can be formed in the dielectric film 100 while reducing the influence on the characteristics of a device such as a CMOSFET mixed with the LDMOSFET 1. This is because the field plate electrode FP and the underlying film as the dielectric film 100 are inherent components of the LDMOSFET 1. That is, the dielectric film 100 does not remain in the CMOSFET, so changing the method of forming the dielectric film 100 does not affect the structure of the CMOSFET. Therefore, the second feature in the present embodiment can improve the breakdown voltage of the LDMOSFET 1 without affecting the characteristics of the CMOSFET.

[0099] In addition, in this embodiment mode, the material of the field plate electrode FP is selected so as not to affect the characteristics of the CMOSFET. For example, titanium nitride (TiN) can be used as the material of the field plate electrode FP. This titanium nitride melts in the cleaning process called "APM process / SPM process", so there may be a situation where defects occur when forming the field plate electrode FP. Therefore, when the field plate electrode FP is formed by titanium nitride, the cleaning conditions of the cleaning process used in the step of forming the contact hole reaching the field plate electrode FP need to be changed. In this regard, not only the contact hole reaching the field plate electrode FP is formed, but also the contact hole reaching the CMOSFET (source region, drain region and gate electrode) is formed. Therefore, changing the cleaning conditions means that the cleaning conditions of the cleaning process of the contact hole reaching the CMOSFET are also changed. Therefore, changing the cleaning conditions of the cleaning process of the contact hole may affect the characteristics of the CMOSFET. That is, when the field plate electrode FP is formed by titanium nitride, changing the cleaning conditions of the cleaning process used for the contact hole may affect the characteristics of the CMOSFET.

[0100] Therefore, in this embodiment mode, the field plate electrode FP is formed of metal silicide (eg, tungsten silicide). This is because the metal silicide does not melt in the "APM process / SPM process", and therefore the cleaning conditions do not need to be changed.

[0101] In addition, from the perspective of suppressing the influence on the characteristics of CMOSFET, the field plate electrode FP does not need to be formed of a polysilicon film. This is because the film formation temperature of the polysilicon film is higher than the formation temperature of the metal silicide, and there is a concern that the characteristics of CMOSFET may change due to heat.

[0102] In summary, in this embodiment mode, by forming the field plate electrode FP from a metal silicide film instead of a titanium nitride film or a polysilicon film, the field plate electrode FP can be implemented without adversely affecting the characteristics of the CMOSFET mixed with the LDMOSFET 1 .

[0103] First Modification Example

[0104] Next, a semiconductor device in a first modified example will be described.

[0105] The structure of semiconductor devices

[0106] Fig.12 : is a plan view showing a schematic configuration of a semiconductor device in a first modified example.

[0107] exist Fig.12 In the example, multiple plugs PLG1 (in Fig.12 The eight plugs PLG1 in the figure are arranged to be separated in the Y direction. Fig.12In the figure, two plugs PLG1 are arranged to be separated in the X direction. Fig.12 In the embodiment, a "plug row" formed by eight plugs PLG1 arranged along the Y direction is arranged in two rows along the X direction. Between the two "plug rows" arranged in this way, a "plug row" formed by eight plugs PLG2 arranged along the Y direction is arranged. Here, the plugs PLG1 are electrically connected to the drain region. On the other hand, the plugs PLG2 are electrically connected to the source region.

[0108] Next, if Fig.12 As shown in FIG. 1 , between the left “plug row” and the center “plug row” and between the center “plug row” and the right “plug row”, the gate electrode GE extends in the Y direction. The width of the gate electrode GE in the Y direction is the gate width. On the other hand, the width of the gate electrode GE in the X direction is the gate length. Moreover, the field plate electrode FP partially overlapping the gate electrode GE in the plan view extends in the Y direction. That is, as shown in FIG. Fig.12 As shown, the field plate electrode FP in the first modified example has a left extension portion and a right extension portion, the left extension portion extending in the Y direction while overlapping with the left gate electrode GE portion, and the right extension portion extending in the Y direction while overlapping with the right gate electrode GE portion. Moreover, the left extension portion and the right extension portion are connected to each other by a plurality of connection portions extending in the X direction. In this way, the field plate electrode FP in the first modified example is formed by the left extension portion, the right extension portion, and a plurality of connection portions. Fig.12 In FIG. 8 , the portion where the gate electrode GE overlaps with the field plate electrode FP is indicated by a dotted line.

[0109] Next, Fig.13 It is along Fig.12 2 is a cross-sectional view of the semiconductor device taken along line AA.

[0110] exist Fig.13 In FIG. 1 , the LDMOSFET 1A has a dielectric film 100 formed to contact a portion of the upper surface of the gate electrode GE, the sidewall spacer SW, and the substrate 1S.

[0111] like Fig.13 As shown, the dielectric film 100 is formed of a dielectric film 10, a dielectric film 20, and a dielectric film 30. The dielectric film 10 is formed to contact a portion of the upper surface of the gate electrode GE, the sidewall spacer SW, and the substrate 1S. The dielectric film 20 is formed to contact the other portion (remaining portion) of the upper surface of the gate electrode GE and the dielectric film 10, and covers the gate electrode GE. The dielectric film 30 is formed to contact the dielectric film 20 and cover the gate electrode GE. Moreover, the field plate electrode FP in the first modified example is formed to contact the dielectric film 30.

[0112] The dielectric film 10 is formed of, for example, a silicon oxide film. The dielectric film 20 is formed of, for example, a silicon nitride film. Furthermore, the dielectric film 30 is formed of, for example, a silicon oxide film. The thickness uniformity of the dielectric film 20 is higher than the thickness uniformity of each of the dielectric film 10 and the dielectric film 30.

[0113] Next, Fig.14 It is along Fig.12 0 is a cross-sectional view of the semiconductor device taken along line BB in FIG.

[0114] exist Fig.14 In the embodiment, the field plate electrode FP contacts the dielectric film 30. In addition, the field plate electrode FP extends to cover the gate electrode GE and is electrically connected to the plug PLG2. Fig.13 The plug PLG2 shown is electrically connected to the source region SR. Fig.14 The plug PLG2 shown is electrically connected to the field plate electrode FP. Also, although not shown, Fig.13 The plugs PLG2 and Fig.14 The plug PLG2 shown is electrically connected, for example, via a wiring formed on the interlayer dielectric film IL. That is, the same potential is applied to the field plate electrode FP and the source region SR.

[0115] Next, Fig.15 It shows Fig.14 A magnified view of a portion of .

[0116] exist Fig.15 In the illustrated region RA, recess 200 is formed in dielectric film 100. In detail, recess 200 is formed in each of dielectric films 10, 20, and 30 configuring dielectric film 100. In this way, LDMOSFET 1A included in the semiconductor device in the first modified example is configured.

[0117] Features in the First Modified Example

[0118] For example, Fig.15 As shown, a feature in the first modified example is that a recess 200 is formed in a region RA of the dielectric film 100 located below the field plate electrode FP. In detail, in the region RA, a recess 200 is formed in each of the dielectric film 10, the dielectric film 20, and the dielectric film 30. Therefore, a portion of the field plate electrode FP is buried in the recess 200 formed in the dielectric film 30, and thus the distance between the lower end of the field plate electrode FP and the gate electrode GE can be reduced compared to a configuration without the recess 200.

[0119] Therefore, the features in the first modified example can suppress a decrease in breakdown voltage caused by electric field concentration at the lower end of the gate electrode GE while reducing on-resistance. Therefore, the first modified example can improve the performance of a semiconductor device including the LDMOSFET 1A.

[0120] Hereinafter, advantages of the first modified example will be described.

[0121] In the first modified example, for example, Fig.13 and 14 As shown, the dielectric film 100 is formed of a dielectric film 10 , a dielectric film 20 , and a dielectric film 30 , and each of the dielectric film 20 and the dielectric film 30 is formed to cover the gate electrode GE.

[0122] Therefore, the first modified example can suppress a short-circuit failure between the field plate electrode FP and the gate electrode GE provided on the dielectric film 30. Specifically, according to the first modified example, even if a “patterning offset” occurs in the patterning when forming the field plate electrode FP, the short-circuit failure between the field plate electrode FP and the gate electrode GE can be suppressed because the gate electrode GE is covered with the dielectric film 20 and the dielectric film 30. Therefore, the first modified example can improve the reliability of the semiconductor device including the LDMOSFET 1A.

[0123] In addition, in the first modified example, the gate electrode GE is covered by the dielectric film 20 and the dielectric film 30. Therefore, according to the first modified example, a part of the field plate electrode FP can be arranged above the gate electrode GE without considering a short-circuit failure. Thus, the first modified example can improve the layout freedom on the field plate electrode FP.

[0124] For example, Fig.14 As shown, the field plate electrode FP may be provided to cover the gate electrode GE. In this case, the same potential "0V" as the source region SR is applied to the field plate electrode FP. Therefore, the field plate electrode FP covering the gate electrode GE serves as a shield between the gate electrode GE and the drain region DR. Thus, according to the first modified example, since the field plate electrode FP serves as a shield, the "gate-drain capacitance" in the LDMOSFET 1A can be reduced. That is, the first modified example can reduce the parasitic capacitance present in the LDMOSFET 1A, and can improve the performance of the semiconductor device including the LDMOSFET 1A.

[0125] Furthermore, in the first modified example, a configuration which is less likely to affect the characteristics of the CMOSFET mixed with the LDMOSFET 1A will be described.

[0126] For example, Fig.15 As shown, the dielectric film 100 is formed of the dielectric film 10, the dielectric film 20 and the dielectric film 30. Here, in the first modified example, as shown in FIG. Fig.15As shown, recess 200 is formed in dielectric film 100 in region RA. In this case, from the viewpoint of forming recess 200, each of dielectric film 10, dielectric film 20, and dielectric film 30 can be formed using a film forming method that easily forms recess 200 in region RA. For example, dielectric film 10, dielectric film 20, and dielectric film 30 are considered to be formed with low thickness uniformity using a normal pressure CVD method or a plasma CVD method rather than a low pressure CVD method.

[0127] For example, the dielectric film 20 is formed of a silicon nitride film. The dielectric film 20 is used as a stress source in the so-called "strained silicon technology" that improves the mobility of carriers in the channel by applying stress (strain) to the LDMOSFET 1A. And, it is desirable that the stress source can apply stress uniformly, and therefore it is desirable to be a film with high thickness uniformity. In this regard, a film having lower thickness uniformity than a film formed by a low-pressure CVD method is formed by a normal-pressure CVD method or a plasma CVD method.

[0128] Therefore, it is desirable to form the dielectric film 20 serving as a stress source using a low-pressure CVD method rather than a normal-pressure CVD method or a plasma CVD method. That is, in the first modified example, from the viewpoint of forming the recess 200 while ensuring the function as a stress source, it is desirable to form the dielectric film 10 and the dielectric film 30 using a normal-pressure CVD method or a plasma CVD method while forming the dielectric film 20 using a low-pressure CVD method.

[0129] In this regard, the above-mentioned technique has little effect on the characteristics of the CMOSFET mixed with the LDMOSFET 1A. That is, not only in the LDMOSFET 1A, but also in the CMOSFET, the dielectric film 20 is formed to be used as a stress source in the "strained silicon technology". If the thickness uniformity of the dielectric film 20 is low, there is a risk that the dielectric film 20 cannot be fully used as a good stress source even in the CMOSFET. Thus, if a low thickness uniformity dielectric film 20 is formed using a normal pressure CVD method or a plasma CVD method to form the recess 200, there is a risk of adversely affecting the characteristics of the CMOSFET (such as the mobility of carriers in the channel). In contrast, according to the above-mentioned technique, the dielectric film 20 is formed using a low pressure CVD method. Thus, the first modified example can improve the thickness uniformity of the dielectric film 20. This allows the recess 200 to be formed in the dielectric film 100 of the LDMOSFET 1A without significantly affecting the characteristics of the CMOSFET mixed with the LDMOSFET 1A. Therefore, the first modified example can improve the performance of the LDMOSFET 1A without adversely affecting the characteristics of the CMOSFET mixed with the LDMOSFET 1A.

[0130] Second Modification Example

[0131] Next, LDMOSFET 1B in a second modified example will be described.

[0132] Fig.16 is an enlarged view showing the configuration between the field plate electrode FP and the lower end of the gate electrode GE in the LDMOSFET 1B. Fig.16 The second modified example is characterized in that the recessed portion RC is formed below the sidewall spacer SW.

[0133] Therefore, the second modified example can reduce Fig.16 That is, according to the second modified example, forming the recessed portion RC below the sidewall spacer SW can reduce the distance between the lower ends of the field plate electrode FP and the gate electrode GE, compared with the configuration without the recessed portion RC.

[0134] Therefore, according to the second modified example, even if the impurity concentration of the substrate 1S increases, the equipotential line is less likely to enter between the field plate electrode FP and the lower end of the gate electrode GE. Therefore, according to the second modified example, the LDMOSFET 1B can reduce the on-resistance while suppressing the reduction in breakdown voltage caused by the electric field concentration at the lower end of the gate electrode GE. Therefore, the second modified example can improve the performance of the semiconductor device including the LDMOSFET 1B.

[0135] For example, the recessed portion RC may be formed by applying isotropic etching to the sidewall spacers SW in addition to the anisotropic etching for forming the sidewall spacers SW.

[0136] In the second modified example, the recessed portion RC is formed in the sidewall spacer SW. This allows the conformal dielectric film 100 to be formed with high thickness uniformity, and the presence of the recessed portion RC can reduce the "distance L" between the lower ends of the field plate electrode FP and the gate electrode GE. In other words, in the second modified example, a low-pressure CVD method capable of forming a film with high thickness uniformity can be used as a method of forming the dielectric film 100.

[0137] However, not only the recessed portion RC may be formed in the sidewall spacer SW, but also the recess may be formed in the dielectric film 100. In this case, the "distance L" can be further reduced by the recessed portion RC and the recess. That is, even in the second modified example, the recess may be formed in the dielectric film 100 by using a method of forming the dielectric film 100 such as a normal pressure CVD method or a plasma CVD method instead of a low pressure CVD method.

[0138] Third Modification Example

[0139] Next, an LDMOSFET 1C in a third modified example will be described.

[0140] Fig.17 is an enlarged view showing the configuration between the lower ends of the field plate electrode FP and the gate electrode GE in the LDMOSFET 1C. Fig.17 The third modified example is characterized in that a recessed portion RC2 is formed at the upper surface of the substrate 1S.

[0141] Therefore, the upper surface of the substrate 1S contacting the dielectric film 100 becomes lower than the upper surface of the substrate 1S contacting the sidewall spacer SW. Fig.17 That is, by forming the recessed portion RC2 at the upper surface of the substrate 1S, the third modified example can reduce the "distance L" compared with the configuration without the recessed portion RC2.

[0142] Therefore, according to the third modified example, even if the impurity concentration of the substrate 1S increases, the equipotential line is less likely to enter between the field plate electrode FP and the lower end of the gate electrode GE. Therefore, the LDMOSFET 1C in the third modified example can suppress the decrease in breakdown voltage caused by the electric field concentration at the lower end of the gate electrode GE while reducing the on-resistance. Therefore, the third modified example can improve the performance of the semiconductor device including the LDMOSFET 1C.

[0143] For example, the recessed portion RC2 may be formed by etching the substrate 1S using the sidewall spacers SW as a mask.

[0144] In the third modified example, the recessed portion RC2 is formed in the substrate 1S. This allows the conformal dielectric film 100 to be formed with high thickness uniformity, and the presence of the recessed portion RC2 can reduce the "distance L" between the lower ends of the field plate electrode FP and the gate electrode GE. In other words, in the third modified example, a low-pressure CVD method capable of forming a film with high thickness uniformity can be used as a method of forming the dielectric film 100.

[0145] Not only the recessed portion RC2 may be formed in the substrate 1S, but also the recess may be formed in the dielectric film 100. In this case, the "distance L" can be further reduced by the recessed portion RC2 and the recess. That is, even in the third modified example, the recess may be formed in the dielectric film 100 by using a method for forming the dielectric film 100 such as a normal pressure CVD method or a plasma CVD method instead of a low pressure CVD method.

[0146] Fourth Modification Example

[0147] Next, an LDMOSFET 1D in a fourth modified example will be described.

[0148] Fig.18 1D is an enlarged view showing the configuration between the lower ends of the field plate electrode FP and the gate electrode GE in the LDMOSFET 1D. Fig.18 As shown, the recess 200 is formed in the dielectric film 100 by patterning using the photolithography technique and the etching technique. Therefore, the recess 200 can be formed by patterning. Also in this case, forming the recess 200 in the dielectric film 100 can reduce the "distance L" between the lower ends of the field plate electrode FP and the gate electrode GE.

[0149] Fifth Modification Example

[0150] Fig.19 1 is a plan view showing a schematic configuration of a semiconductor device including an LDMOSFET 1E in a fifth modified example. Fig.19 As shown, the gate electrode GE of the LDMOSFET 1E extends along the Y direction on the active area ACT in a plan view.

[0151] Moreover, in a plan view, the field plate electrode FP extends in the Y direction while partially overlapping with the gate electrode GE. Fig.19 Although not shown in the drawings, a portion of the field plate electrode FP extends in the Y direction in a plan view so as to overlap with the active region ACT between the drain region DR and the sidewall spacer SW.

[0152] Here, for example Fig.19 As shown, the fifth modified example is characterized in that a portion of the field plate electrode FP is electrically connected to the plurality of plugs PLG3. That is, a wiring (not shown) is formed to overlap the field plate electrode FP in a plan view, and the field plate electrode FP and the wiring are connected via Fig.19 Multiple plugs PLG3 are shown connected.

[0153] Therefore, the fifth modified example can strengthen the electrical connection between the field plate electrode FP and the plug PLG3. Specifically, when a recess is formed in the dielectric film located below the field plate electrode FP, it is considered that the thickness uniformity of the field plate electrode FP is reduced. In this case, a portion with a small thickness is formed in the field plate electrode FP, and therefore, the resistance value of the field plate electrode FP may increase due to the small thickness of the portion. Therefore, in the fifth modified example, a plurality of plugs PLG3 are connected to the field plate electrode FP. This can reduce the resistance value of the field plate electrode FP. That is, according to the fifth modified example, by connecting the field plate electrode FP and the plurality of plugs PLG3, the increase in the resistance component caused by the reduction in the thickness uniformity of the field plate electrode FP is reduced. Therefore, the fifth modified example can improve the performance of the semiconductor device including the LDMOSFET 1E.

[0154] Sixth Modification Example

[0155] Next, an LDMOSFET 1F in a sixth modified example will be described.

[0156] Fig. 20A and 20B is an enlarged view showing the configuration between the field plate electrode FP and the sidewall spacer SW. Fig. 20A , an example is shown in which the plug PLG3 connected to the field plate electrode FP is provided near the recess 200 . That is, the plug PLG3 is provided to overlap with the recess 200 .

[0157] like Fig. 20A As shown, if the plug PLG3 is disposed near the recess 200 , a connection failure may occur between the field plate electrode FP and the plug PLG3 due to the shape of the recess 200 .

[0158] on the other hand, Fig. 20B LDMOSFET 1F in the sixth modified example is shown. Specifically, Fig. 20B In the embodiment of the present invention, the plug PLG3 connected to the field plate electrode FP is disposed away from the recess 200 . That is, the plug PLG3 is disposed not to overlap with the recess 200 .

[0159] like Fig. 20B As shown, by disposing the plug PLG3 away from the recess 200, the field plate electrode FP and the plug PLG3 can be connected without being affected by the shape of the recess 200. Therefore, the sixth modification example can improve the reliability of the semiconductor device including the LDMOSFET 1F.

[0160] The present invention made by the present inventors has been specifically described above based on the embodiments, but the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

[0161] In this specification, an epitaxial layer EPI into which n-type impurities are introduced is described, but an epitaxial layer EPI into which p-type impurities are introduced may be applied. When an epitaxial layer EPI into which p-type impurities are introduced is applied, the epitaxial layer EPI may have, for example, a buried semiconductor layer and a drift layer. The buried semiconductor layer is formed to electrically isolate the LDMOSFET from the semiconductor substrate. The drift layer has a lower impurity concentration than the drain region DR, and is formed from the drain region DR toward the gate electrode GE similarly to the offset drain region ODR.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate and separated from the source region; A gate dielectric film is formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; a sidewall spacer formed on a side surface of the gate electrode; a dielectric film formed to contact a portion of an upper surface of the gate electrode, the sidewall spacer, and the semiconductor substrate; as well as a field plate electrode formed on the dielectric film, wherein a recess is formed at an upper surface of the dielectric film and between the drain region and the gate electrode, and A portion of the field plate electrode is buried in the recess.

2. The semiconductor device according to claim 1, Wherein the dielectric film comprises: A first portion in contact with the semiconductor substrate; a second portion in contact with the sidewall spacer; as well as A third portion is in contact with the portion of the upper surface of the gate electrode, wherein the recess is formed at a connection point between the upper surface of the first portion and the upper surface of the second portion.

3. The semiconductor device according to claim 1, A first distance between the upper surface of the semiconductor substrate and the recess is greater than a thickness of the gate dielectric film.

4. The semiconductor device according to claim 2, wherein concavities and convexities corresponding to the surface roughness are formed at the upper surface of the first portion, and A first difference between the highest position of the concavo-convex and the lower end of the concavo-convex is greater than a second difference between the highest position of the concavo-convex and the lowest position of the concavo-convex.

5. The semiconductor device according to claim 4, The first difference is greater than 2 nm.

6. The semiconductor device according to claim 1, The distance between the gate electrode and the drain region is greater than the distance between the gate electrode and the source region.

7. The semiconductor device according to claim 1, The field plate electrode is formed of a metal silicide film.

8. The semiconductor device according to claim 1, Wherein the dielectric film comprises: a first dielectric film formed to contact the portion of the upper surface of the gate electrode, the sidewall spacer, and the semiconductor substrate; a second dielectric film formed to contact the other portion of the upper surface of the gate electrode and the first dielectric film and to cover the gate electrode; as well as A third dielectric film is formed to contact the second dielectric film.

9. The semiconductor device according to claim 8, The thickness uniformity of the second dielectric film is higher than the thickness uniformity of each of the first dielectric film and the third dielectric film.

10. The semiconductor device according to claim 8, The field plate electrode extends to cover the gate electrode and is electrically connected to the source region.

11. The semiconductor device according to claim 1, wherein a recessed portion is formed at a lower portion of the sidewall spacer.

12. The semiconductor device according to claim 1, An upper surface of the semiconductor substrate in contact with the dielectric film is lower than an upper surface of the semiconductor substrate in contact with the sidewall spacer.

13. The semiconductor device according to claim 1, wherein a portion of the field plate electrode extends in a gate width direction of the gate electrode in a plan view to overlap with an active region between the drain region and the sidewall spacer, and wherein the portion of the field plate electrode is electrically connected to a plurality of plugs.

14. The semiconductor device according to claim 1, comprising: plug, connected to the field plate electrode, The plug is arranged to be separated from the recess.

15. A method for manufacturing a semiconductor device, the method comprising: (a) forming a gate electrode on a semiconductor substrate via a gate dielectric film; (b) forming a sidewall spacer on a side surface of the gate electrode; (c) forming a dielectric film so as to contact a portion of the upper surface of the gate electrode, the sidewall spacer, and the semiconductor substrate; as well as (d) forming a field plate electrode on the dielectric film, In the above (c), the dielectric film is formed by using a normal pressure CVD method or a plasma CVD method.

16. The method according to claim 15, Wherein the dielectric film comprises: A first portion in contact with the semiconductor substrate; a second portion in contact with the sidewall spacer; as well as a third portion in contact with the portion of the upper surface of the gate electrode, wherein a recess is formed at a connection point between the upper surface of the first portion and the upper surface of the second portion, and A portion of the field plate electrode is buried in the recess.

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