Bigrid heterojunction thin film transistor and preparation method and application thereof

Abstract

The invention belongs to the related technical field of thin film transistors, and discloses a bigrid heterojunction thin film transistor and a preparation method and application thereof.The bigrid heterojunction thin film transistor comprises a substrate, a first grid, a first insulating layer, a first channel layer, a second channel layer, a source, a drain, a second insulating layer and a second grid, the second insulating layer is embedded in the first insulating layer; the first insulating layer is arranged on the first grid electrode and the substrate; the first channel layer is arranged on the first insulating layer, and the second channel layer is arranged on the first channel layer; the source electrode and the drain electrode are respectively arranged at two opposite ends of the second channel layer and are embedded in the second insulating layer; the second insulating layer is arranged on the second channel layer, the source electrode and the drain electrode; and the second grid electrode is arranged on the surface, far away from the second channel layer, of the second insulating layer. The mobility of the thin film transistor is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field related to thin film transistors, and more specifically, relates to a dual-gate heterojunction thin film transistor and a preparation method and application thereof. Background Art

[0002] Driven by applied physics, chemistry, materials and other related disciplines, electronic information technology has developed rapidly. Various intelligent terminal products are gradually changing the production and lifestyle of human society. As the main means of information interaction, high-performance display panels are indispensable for terminals such as televisions, computers, mobile phones, smart watches, and augmented reality / virtual reality (VR / AR) smart glasses. At present, the mainstream display panels are active matrix flat panel displays (AMFPDs), and active matrix-driven flat panel displays use independent storage charges to control the corresponding pixels. Thin film transistors are their core components, and the brightness of each pixel can be adjusted through their switches, thereby realizing image display of different grayscales and colors. Therefore, thin film transistors play a decisive role in the overall performance of new display devices.

[0003] However, as smart terminals cannot be updated, traditional thin-film transistors can hardly meet the market demand for high resolution, high refresh rate and high stability. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a dual-gate heterojunction thin film transistor and a preparation method and application thereof, which aims to solve the problems of low mobility and poor stability of existing thin film transistors.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided a dual-gate heterojunction thin film transistor, the transistor being a layered structure, comprising a substrate, a first gate, a first insulating layer, a first channel layer, a second channel layer, a source, a drain, a second insulating layer and a second gate, the first gate being arranged on the substrate and embedded in the first insulating layer; the first insulating layer being arranged on the first gate and the substrate; the first channel layer being arranged on the first insulating layer, and the second channel layer being arranged on the first channel layer; the source and the drain being arranged at opposite ends of the second channel layer, respectively, and both being embedded in the second insulating layer; the second insulating layer being arranged on the second channel layer, the source and the drain; the second gate being arranged on the surface of the second insulating layer away from the second channel layer.

[0006] Furthermore, the first channel layer and the second channel layer are stacked to form a heterojunction semiconductor layer, and the energy bands of the first channel layer and the second channel layer match each other to form a two-dimensional electron gas.

[0007] Furthermore, the heterojunction semiconductor layer is formed of any two semiconductor thin film materials whose energy bands are matched and can form a two-dimensional electron gas.

[0008] Furthermore, the substrate is a SiO 2 layer of silicon substrate or glass substrate.

[0009] Furthermore, the thickness of the source electrode, the drain electrode, the first gate electrode and the second gate electrode is 50 nm to 120 nm.

[0010] Furthermore, the first insulating layer and the second insulating layer are Al prepared by atomic layer deposition. 2 O 3 Layer, HfO 2 layer and ZrO 2 Any of the layers.

[0011] Furthermore, the first channel layer is an IGO film; and the second channel layer is an indium oxide film.

[0012] The present invention also provides a method for preparing a dual-gate heterojunction thin film transistor, the method for preparing the dual-gate heterojunction thin film transistor as described above, comprising the following steps:

[0013] providing a substrate;

[0014] An electrode is prepared on the substrate by magnetron sputtering as a first gate;

[0015] Forming a first insulating layer on the first gate by using atomic layer deposition;

[0016] Using magnetron sputtering to prepare a semiconductor heterojunction layer on the first insulating layer;

[0017] Using magnetron sputtering to prepare a source electrode and a drain electrode on the semiconductor heterojunction layer;

[0018] Using atomic layer deposition to form a second insulating layer on the source and the drain;

[0019] A second gate is prepared on the second insulating layer by using atomic layer deposition to obtain the thin film transistor.

[0020] Furthermore, before the source and the drain are prepared, a step of annealing the semiconductor heterojunction layer is also included.

[0021] The present invention also provides an application of the double-gate heterojunction thin film transistor as described above in a display panel.

[0022] In general, compared with the prior art, the above technical solutions conceived by the present invention mainly have the following beneficial effects in the dual-gate heterojunction thin film transistor and its preparation method and application provided by the present invention:

[0023] 1. The first channel layer and the second channel layer are stacked into a heterojunction semiconductor layer. The energy bands of the first channel layer and the second channel layer match each other to form a two-dimensional electron gas, which can reduce the scattering effect of impurities in the semiconductor material and effectively improve the mobility of the thin film transistor, thereby realizing a thin film transistor with high mobility and high stability.

[0024] 2. By regulating the transport behavior of carriers in the first channel layer and the second channel layer respectively by the first gate and the second gate, electrostatic control can be effectively improved to regulate the subthreshold swing. The two gates can apply different voltage levels to regulate the two channel layers, which can more effectively regulate the behavior of carriers in the front and rear channels, thereby more effectively regulating the threshold voltage of the thin film transistor.

[0025] 3. After the semiconductor heterojunction layer is prepared, it needs to be annealed to reduce internal defects in the semiconductor film.

[0026] 4. Construct a heterojunction, select semiconductor thin film materials with better stability and semiconductor thin film materials with higher mobility as the materials of the two channel layers respectively. The synergistic effect of the two semiconductor thin film materials can improve the mobility and stability of the entire thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic structural diagram of a double-gate heterojunction thin film transistor provided by the present invention;

[0028] Figure 2-Figure 9 They are schematic diagrams of structures prepared in each step of a method for preparing a dual-gate heterojunction thin-film transistor provided by the present invention.

[0029] In all drawings, the same reference numerals are used to denote the same elements or structures, wherein: 100 - substrate, 200 - first gate, 300 - first insulating layer, 400 - first channel layer, 500 - second channel layer, 600 - source, 700 - drain, 800 - second insulating layer, 900 - second gate. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] See also Figure 1 The present invention provides a dual-gate heterojunction thin film transistor, the transistor is a layered structure, which includes a substrate 100, a first gate 200, a first insulating layer 300, a first channel layer 400, a second channel layer 500, a source 600, a drain 700, a second insulating layer 800 and a second gate 900, the first gate 200 is arranged on the substrate 100 and embedded in the first insulating layer 300. The first insulating layer 300 is arranged on the first gate 200 and the substrate 100, and covers a part of the first gate 200 and the substrate 100. The first channel layer 400 is arranged on the first insulating layer 300, and the second channel layer 500 is arranged on the first channel layer 400. The source 600 and the drain 700 are respectively arranged at two opposite ends of the second channel layer 500, and are both embedded in the second insulating layer 800. The second insulating layer 800 is disposed on the second channel layer 500, the source 600 and the drain 700, and covers the second channel layer 500, a portion of the source 600 and the drain 700. The second gate 900 is disposed on a surface of the second insulating layer 800 away from the second channel layer 500.

[0032] The first channel layer 400 and the second channel layer 500 are stacked to form a heterojunction semiconductor layer. The energy bands of the first channel layer 400 and the second channel layer 500 match each other to form a two-dimensional electron gas, thereby realizing a thin film transistor with high mobility and high stability to meet the requirements of future display panels for high stability and high refresh rate. Among them, the first gate 200 and the second gate 900 are used to regulate the transport behavior of carriers in the first channel layer 400 and the second channel layer 500 respectively, which can effectively improve electrostatic control to regulate the subthreshold swing. The two gates can apply different voltage levels to regulate the two channel layers, which can more effectively regulate the behavior of carriers in the front and rear channels, thereby more effectively regulating the threshold voltage of the thin film transistor.

[0033] In one embodiment, the heterojunction semiconductor layer is formed of any two semiconductor thin film materials with energy band matching that can form a two-dimensional electron gas; the substrate 100 is a SiO 2The source electrode 600, the drain electrode 700, the first gate electrode 200 and the second gate electrode 900 have a thickness of 50 nm to 120 nm and may be one of an Al electrode, an Au electrode, an ITO electrode or a W electrode.

[0034] The first insulating layer 300 and the second insulating layer 800 may be Al2O3 prepared by atomic layer deposition. 2 O 3 , HfO 2 and ZrO 2 Any one of .

[0035] The present invention also provides a method for preparing the dual-gate heterojunction thin film transistor as described above, the method comprising the following steps:

[0036] providing a substrate;

[0037] An electrode is prepared on the substrate by magnetron sputtering as a first gate 200;

[0038] Forming a first insulating layer 300 on the first gate 200 by using atomic layer deposition;

[0039] Using magnetron sputtering to prepare a semiconductor heterojunction layer on the first insulating layer 300;

[0040] Using magnetron sputtering to prepare a source electrode 600 and a drain electrode 700 on the semiconductor heterojunction layer;

[0041] A second insulating layer 800 is formed on the source 600 and the drain 700 by atomic layer deposition;

[0042] A second gate 900 is formed on the second insulating layer 800 by atomic layer deposition to obtain the thin film transistor.

[0043] The material is patterned using a mask during the preparation process, wherein the first insulating layer 300 covers the entire silicon wafer.

[0044] After the semiconductor heterojunction layer is prepared, it needs to be annealed to reduce internal defects in the semiconductor film.

[0045] The present invention also provides an application of the double-gate heterojunction thin film transistor as described above in a display panel.

[0046] The present invention is further described in detail below with reference to specific embodiments.

[0047] Example 1

[0048] Embodiment 1 of the present invention provides a method based on IGO / In 2 O 3The method for preparing a heterojunction double-gate heterojunction thin film transistor is specifically as follows:

[0049] Step 1: Provide the substrate

[0050] Select a 300nm thick SiO 2 The silicon wafer was cut into 2 cm × 2 cm size using a dicing machine, and then ultrasonically cleaned in acetone and isopropanol for 15 min each, rinsed with deionized water, and dried with nitrogen before being used as a substrate. Figure 2 shown.

[0051] Step 2: Gate Metal Preparation

[0052] like Figure 3 As shown, an aluminum electrode is grown on a substrate by magnetron sputtering, and the preparation parameters are: working pressure is 0.6 Pa; argon gas flow rate is 40 sccm; and the DC sputtering power of the aluminum target is 80 W. A mask is used to pattern the aluminum electrode during the sputtering process.

[0053] Step 3: Preparation of Hafnium Oxide Insulation Layer

[0054] like Figure 4 As shown, using the atomic layer deposition process, the oxygen source and the hafnium source are first preheated, the sample is placed in the reaction chamber, and then the chamber is evacuated to grow a hafnium oxide film on the aluminum electrode.

[0055] Step 4: IGO film preparation

[0056] like Figure 5 As shown, magnetron sputtering is used to grow an IGO film on a hafnium oxide insulating layer, and the preparation parameters are: working pressure is 0.65 Pa; argon gas flow rate is 30 sccm; and the RF sputtering power of the aluminum target is 200 W. During the sputtering process, a mask is used to pattern the IGO film.

[0057] Step 5: Indium oxide film preparation

[0058] like Figure 6 As shown, magnetron sputtering is used to grow an indium oxide film on an IGO film, and the preparation parameters are: working pressure is 0.6 Pa; argon gas flow rate is 47.5 sccm; oxygen gas flow rate is 2.5 sccm; and the DC sputtering power of the aluminum target is 50 W. During the sputtering process, a mask is used to pattern the indium oxide film.

[0059] Step 6: Heterojunction Film Annealing

[0060] The heterojunction film was annealed in a tube furnace with the process parameters of annealing at 400°C for 1 hour in an air atmosphere.

[0061] Step 7: Source Metal Preparation

[0062] like Figure 7 As shown, an aluminum electrode is grown on indium oxide by magnetron sputtering, and the preparation parameters are: working pressure is 0.6 Pa; argon gas flow rate is 40 sccm; DC sputtering power of the aluminum target is 80 W. A mask is used to pattern the aluminum electrode during the sputtering process.

[0063] Step 8: Drain Metal Preparation

[0064] like Figure 8 As shown, an aluminum electrode is grown on indium oxide by magnetron sputtering, and the preparation parameters are: working pressure is 0.6 Pa; argon gas flow rate is 40 sccm; DC sputtering power of the aluminum target is 80 W. A mask is used to pattern the aluminum electrode during the sputtering process.

[0065] Step 9: Preparation of Hafnium Oxide Insulation Layer

[0066] like Fig. 9 As shown, using the atomic layer deposition process, the oxygen source and the hafnium source are first preheated, the sample is placed in the reaction chamber, and then the chamber is evacuated to grow a hafnium oxide film on the aluminum electrode.

[0067] Step 10: Gate Metal Preparation

[0068] like Figure 1 As shown, an aluminum electrode is grown on a hafnium oxide film by magnetron sputtering, and the preparation parameters are: working pressure is 0.6 Pa; argon gas flow rate is 40 sccm; and the DC sputtering power of the aluminum target is 80 W. A mask is used to pattern the aluminum electrode during the sputtering process.

[0069] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dual-gate heterojunction thin film transistor, characterized in that: The transistor is a layered structure, which includes a substrate, a first gate, a first insulating layer, a first channel layer, a second channel layer, a source, a drain, a second insulating layer and a second gate. The first gate is arranged on the substrate and embedded in the first insulating layer; the first insulating layer is arranged on the first gate and the substrate; the first channel layer is arranged on the first insulating layer, and the second channel layer is arranged on the first channel layer; the source and the drain are respectively arranged at opposite ends of the second channel layer and are both embedded in the second insulating layer; the second insulating layer is arranged on the second channel layer, the source and the drain; the second gate is arranged on the surface of the second insulating layer away from the second channel layer.

2. The dual-gate heterojunction thin film transistor according to claim 1, characterized in that: The first channel layer and the second channel layer are stacked to form a heterojunction semiconductor layer, and the energy bands of the first channel layer and the second channel layer match each other to form a two-dimensional electron gas.

3. The dual-gate heterojunction thin film transistor according to claim 2, wherein: The heterojunction semiconductor layer is formed by any two semiconductor thin film materials whose energy bands match and can form a two-dimensional electron gas.

4. The dual-gate heterojunction thin film transistor according to claim 1, wherein: The substrate is a silicon substrate or a glass substrate containing a SiO2 layer.

5. The dual-gate heterojunction thin film transistor according to claim 1, wherein: The thickness of the source electrode, the drain electrode, the first gate electrode and the second gate electrode is 50 nm to 120 nm.

6. The dual-gate heterojunction thin film transistor according to claim 1, wherein: The first insulating layer and the second insulating layer are any one of an Al2O3 layer, a HfO2 layer and a ZrO2 layer prepared by atomic layer deposition.

7. The dual-gate heterojunction thin film transistor according to claim 1, wherein: The first channel layer is an IGO film; the second channel layer is an indium oxide film.

8. A method for preparing a dual-gate heterojunction thin film transistor, characterized in that: The preparation method is used to prepare the double-gate heterojunction thin film transistor according to any one of claims 1 to 7, and comprises the following steps: providing a substrate; An electrode is prepared on the substrate by magnetron sputtering as a first gate; Forming a first insulating layer on the first gate by using atomic layer deposition; Using magnetron sputtering to prepare a semiconductor heterojunction layer on the first insulating layer; Using magnetron sputtering to prepare a source electrode and a drain electrode on the semiconductor heterojunction layer; Using atomic layer deposition to form a second insulating layer on the source and the drain; A second gate is prepared on the second insulating layer by using atomic layer deposition to obtain the thin film transistor.

9. The method for preparing a dual-gate heterojunction thin film transistor according to claim 8, characterized in that: Before the source and the drain are prepared, a step of annealing the semiconductor heterojunction layer is also included.

10. Application of the double-gate heterojunction thin film transistor according to any one of claims 1 to 7 in a display panel.

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