Solar cell, cell assembly and photovoltaic system

Abstract

The invention is suitable for the field of photovoltaic technology, and provides a solar cell, a cell assembly and a photovoltaic system, the solar cell comprises a silicon substrate, the silicon substrate is provided with a back surface and a front surface which are oppositely arranged; the diffusion layer is positioned in a first region on the back surface of the silicon substrate; the doped layer is located in a second area on the back face of the silicon substrate, the doped layer comprises at least one of doped amorphous silicon, doped microcrystalline silicon and doped polycrystalline silicon, and the doped layer and the diffusion layer are doped with different polarities; two opposite surfaces of the tunneling layer are respectively in contact with the diffusion layer and the doping layer; the first electrode is communicated with the diffusion layer, the second electrode is communicated with the doping layer, and the first electrode is not communicated with the doping layer; the connection depth of the first electrode extending into the diffusion layer is greater than the connection depth of the second electrode extending into the doping layer. The hot spot risk can be reduced, the overall performance of the solar cell can be improved, and particularly the charge collection efficiency and the current transmission stability of the solar cell can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of photovoltaic technology, and in particular relates to a solar cell, a battery assembly and a photovoltaic system. Background Art

[0002] Photovoltaic modules composed of multiple cells are usually installed in open areas with plenty of sunshine. In long-term use, it is inevitable that flying birds, dust, fallen leaves and other obstructions will fall on the photovoltaic modules. These obstructions will form shadows on the photovoltaic modules. In large photovoltaic module arrays, the row spacing is not suitable and shadows can be formed on each other. Due to the existence of local shadows, the current and voltage of some solar cell chips in the photovoltaic module have changed. Conventional solar cells have diode characteristics, and the obscured cells are reverse biased, which increases the product of the local current and voltage of the photovoltaic module, and its power consumption is extremely high, resulting in local temperature rise on these photovoltaic modules. Defects in some cell chips in the photovoltaic module may also cause the module to heat up locally during operation. This phenomenon is called the "hot spot effect". Therefore, photovoltaic modules with existing batteries have a high risk of hot spots in actual operation. After being packaged into photovoltaic modules, the hot spot effect may reduce the power of the module and bring safety issues such as local temperature rise. In related technologies, the risk of hot spots in photovoltaic modules is often avoided by setting bypass diodes, but this method will significantly reduce the charge collection efficiency. Therefore, it is urgent to use other technical means to reduce the "hot spot effect" while maintaining the charge collection efficiency. Summary of the invention

[0003] The present invention provides a solar cell, a battery assembly and a photovoltaic system, aiming to solve the problem of how to reduce the "hot spot effect" while maintaining the charge collection efficiency.

[0004] The present invention is implemented as follows: a solar cell comprises: a silicon substrate, wherein the silicon substrate has a back surface and a front surface arranged opposite to each other;

[0005] A diffusion layer located in a first region on the back side of the silicon substrate;

[0006] a doping layer located in a second region on the back side of the silicon substrate, the doping layer comprising at least one of doped amorphous silicon, doped microcrystalline silicon and doped polycrystalline silicon, the doping layer and the diffusion layer being doped to different polarities;

[0007] a tunneling layer, wherein two opposite surfaces of the tunneling layer are in contact with the diffusion layer and the doping layer respectively; and

[0008] A first electrode connected to the diffusion layer and a second electrode connected to the doping layer, the first electrode is not conductive with the doping layer; a connection depth of the first electrode extending into the diffusion layer is greater than a connection depth of the second electrode extending into the doping layer.

[0009] Optionally, when the doped layer is a polysilicon layer, a contact area between an end surface of the first electrode and the diffusion layer is greater than a contact area between an end surface of the second electrode and the doped layer.

[0010] Optionally, when the doping layer is doped amorphous silicon or doped microcrystalline silicon, the second electrode is connected to the doping layer through the TCO layer, and the connection depth between the second electrode and the doping layer is 0.

[0011] Optionally, the second region partially overlaps with the first region, the doping layer includes a first portion, a second portion, and a third portion connecting the first portion and the second portion, and the first portion is disposed in an overlapping region of the second region and the first region and is disposed on the diffusion layer;

[0012] An insulating layer is disposed between the diffusion layer and the first portion, and the tunneling layer is disposed on the bottom surface of the second portion and the inner side surface of the third portion.

[0013] Optionally, the distance between the diffusion layer and the front surface of the silicon substrate is greater than the distance between the second portion and the front surface of the silicon substrate, the diffusion layer and the insulating layer extend toward the adjacent doping layer, and the tunneling layer and the doping layer form a protrusion along the extension direction of the diffusion layer.

[0014] Optionally, the horizontal direction is a first direction, the first region and the second region are spaced apart along the first direction; and two opposite surfaces of the tunneling layer along the first direction contact the diffusion layer and the doping layer respectively.

[0015] Optionally, the surface of the silicon substrate facing the doping layer is a polished surface.

[0016] Optionally, an interface passivation layer is disposed between the first portion and the insulating layer in the first region.

[0017] Optionally, the tunneling layer is connected to the interface passivation layer.

[0018] Optionally, the horizontal direction is a first direction, and the first area and the second area are arranged at intervals along the first direction;

[0019] Along the first direction, a groove is provided between some adjacent diffusion layers and doping layers, the groove isolating the doping layer and the diffusion layer, and the distance between the bottom of the groove and the front surface of the silicon substrate is smaller than the distance between the second portion and the front surface of the silicon substrate.

[0020] Optionally, the total area of ​​the grooves accounts for greater than or equal to 20% of the total area of ​​the back side of the silicon substrate.

[0021] Optionally, the edge of the diffusion layer is not connected to the groove wall of the groove.

[0022] Optionally, a glass frit content in the first electrode is less than a glass frit content in the second electrode.

[0023] Optionally, a surface of the diffusion layer facing the insulation layer is a suede surface.

[0024] Optionally, a difference between a distance between the diffusion layer and the front surface of the silicon substrate and a distance between the second portion and the front surface of the silicon substrate is 1 μm to 6 μm.

[0025] Optionally, the diffusion layer is P-type doped single crystal silicon; and the doping layer is N-type doped polycrystalline silicon.

[0026] The present invention also provides a photovoltaic assembly, comprising the above-mentioned solar cell.

[0027] The present invention also provides a photovoltaic system, comprising the photovoltaic assembly mentioned above.

[0028] The beneficial effects achieved by the present invention are that the relationship between the photoelectric conversion efficiency of the solar cell and the risk of controlling hot spots can be balanced due to the reasonable design of the position of the conductive contact structure at the solar cell, and the risk of hot spots can be reduced while ensuring that the conversion efficiency of the solar cell is not significantly lost. At the same time, the different depths of electrode insertion are optimized, which helps to improve the overall performance of the solar cell, especially its charge collection efficiency and the stability of current transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a partial structural schematic diagram of the first solar cell provided by the present invention;

[0030] Figure 2 is a partial structural schematic diagram of a second solar cell provided by the present invention;

[0031] Figure 3 is a partial structural schematic diagram of a third solar cell provided by the present invention;

[0032] Figure 4 is a partial structural schematic diagram of a fourth solar cell provided by the present invention;

[0033] Figure 5 This is a schematic diagram of the first positional relationship among the diffusion layer, the doping layer and the tunneling layer in the solar cell provided by the present invention;

[0034] Figure 6 This is a schematic diagram of the second positional relationship among the diffusion layer, the doping layer and the tunneling layer in the solar cell provided by the present invention;

[0035] Figure 7 is a partial structural schematic diagram of a fifth solar cell provided by the present invention;

[0036] Figure 8 It is a partial structural schematic diagram of the sixth solar cell provided by the present invention.

[0037] Description of reference numerals:

[0038] 100, solar cell; 110, first region; 111, diffusion layer; 120, second region; 121, doping layer; 1211, first part; 1212, third part; 1213, second part; 130, insulating layer; 140, tunneling layer; 150, silicon substrate; 160, first electrode; 170, second electrode; 171, TCO layer; 180, interface passivation layer; 190, groove. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0044] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0045] The present invention can balance the relationship between the photoelectric conversion efficiency of the solar cell and the control of the hot spot risk by rationally designing the position of the conductive contact structure on the solar cell. It can reduce the hot spot risk while ensuring that the conversion efficiency of the solar cell is not significantly lost. At the same time, it optimizes the different depths of electrode insertion, which helps to improve the overall performance of the solar cell, especially its charge collection efficiency and the stability of current transmission.

[0046] Embodiment 1

[0047] like Figure 1 As shown, this embodiment provides a solar cell 100, including:

[0048] A silicon substrate 150, wherein the silicon substrate 150 has a back surface and a front surface that are oppositely disposed;

[0049] A diffusion layer 111 is located in a first region 110 on the back side of the silicon substrate;

[0050] A doping layer 121 is located in the second region 120 on the back side of the silicon substrate, the doping layer 121 includes at least one of doped amorphous silicon, doped microcrystalline silicon and doped polycrystalline silicon, and the doping layer and the diffusion layer are doped with different polarities;

[0051] A tunneling layer 140, wherein two opposite surfaces of the tunneling layer 140 contact the diffusion layer 111 and the doping layer 121 respectively; and

[0052] The first electrode 160 connected to the diffusion layer 111 and the second electrode 170 connected to the doping layer 121 are not conductive with the doping layer 121 ; the connection depth of the first electrode 160 extending into the diffusion layer 111 is greater than the connection depth of the second electrode 170 extending into the doping layer 121 .

[0053] In the solar cell 100 provided in the present application, the "front" and "back" in the front and back sides of the silicon substrate 150 are relative, that is, the "front" refers to the side facing the sunlight along the vertical direction, and the "back" refers to the side facing away from the sunlight along the vertical direction.

[0054] The diffusion layer 111 is located in the first region 110, and the doping layer 121 is located in the second region 120. The first region 110 and the second region 120 are both located on the back of the silicon substrate 150. Specifically, multiple first regions 110 and multiple second regions 120 are arranged at intervals. The tunneling layer 140 is placed between the diffusion layer 111 and the doping layer 121. The two opposite sides of the tunneling layer 140 contact the diffusion layer 111 and the doping layer 121 respectively, that is, there must be a region in which the diffusion layer 111, the tunneling layer 140 and the doping layer 121 are adjacent in sequence, so as to achieve conductive contact between the diffusion layer 111 and the doping layer 121. Specifically, it can be, Figure 5 As shown, the two opposite sides along the horizontal direction can also be, as Figure 6 As shown, two surfaces opposite to each other in the vertical direction.

[0055] It can be understood that the diffusion layer 111 and the doping layer 121 are doped to different polarities. When the diffusion layer 111 is P-type, the doping layer 121 is N-type; when the diffusion layer 111 is N-type, the doping layer 121 is P-type.

[0056] The diffusion layer 111, the silicon substrate 150 and the doping layer 121 form a PN junction structure to realize the separation and collection process of photogenerated carriers of the solar cell 100. The tunneling layer 140 allows electrons and holes to quickly pass through the interface through the quantum tunneling effect, and the diffusion layer 111 and the doping layer 121 conduct electricity through tunneling through the tunneling layer 140.

[0057] When the solar cell 100 generates electricity normally, the diffusion layer 111 and the doping layer 121 perform photoelectric conversion normally to generate electricity. At the component end, when the solar cell 100 is blocked, other solar cells 100 connected in series with it provide reverse current for the blocked solar cell 100, and the adjacent areas of the diffusion layer 111, tunneling layer 140 and doping layer 121 of the solar cell 100 can generate a composite leakage current of appropriate size, which reduces the voltage across the blocked solar cell 100 (the voltage is less than the sum of the voltages of other solar cells 100 connected in series with the solar cell 100 and not blocked), and the heat generation power of the solar cell 100 will be reduced, thereby reducing the high heat risk of the hot spot effect.

[0058] Secondly, by deliberately introducing a conductive contact structure in the solar cell 100, it has a protective effect on the hot spot effect caused by defects in the silicon substrate 150 itself (that is, it can reduce the heat generated by the defects), and can reduce or even eliminate the requirements for controlling the defects of the silicon substrate 150. This reduces the risk of hot spots caused by defects in the silicon substrate 150 and improves the manufacturing capacity of the solar cell 100.

[0059] The first electrode 160 is connected to the diffusion layer 111. The diffusion layer 111 is formed on the silicon substrate 150 through a doping process, and is usually an N-type or P-type single crystal silicon diffusion. The doping concentration of the diffusion layer 111 is generally low, and the density of mobile carriers (such as electrons or holes) is relatively low, but widely distributed. The diffusion layer 111 is usually the main collection area for photogenerated carriers. Since the diffusion layer 111 has a high conductivity, the deeply connected first electrode can efficiently collect and conduct current, so that more photogenerated carriers are fully utilized. The second electrode 170 is connected to the doping layer 121. The carrier density of the doping layer 121 is relatively high. Therefore, the second electrode only needs to extend into the doping layer 121 to a relatively small depth to effectively collect charges. The second electrode has a small insertion depth, and the contact can reduce the complexity of the manufacturing process and the use of electrode materials. The connection depth refers to the vertical insertion distance of the first electrode 160 into the diffusion layer 111 or the second electrode 170 into the doping layer 121, such as Figure 1 h1 and h2 in .

[0060] It can be understood that in this embodiment, the first electrode 160 is connected to the diffusion layer 111, and the diffusion layer 111 is connected to the doping layer 121 through the tunneling layer 140, that is, the first electrode 160 and the doping layer 140 are indirectly connected through the diffusion layer 111 and the tunneling layer 140. In addition to this conductive path, there is no other direct or indirect conductive path between the first electrode 160 and the doping layer 121 in the solar cell 100, and specifically, a gap or an insulating medium may be provided between the first electrode 160 and the doping layer 121.

[0061] In the present application, by rationally designing the position of the conductive contact structure in the solar cell 100, the relationship between the photoelectric conversion efficiency of the solar cell 100 and the risk of controlling hot spots can be balanced, and the risk of hot spots can be reduced while ensuring that there is no significant loss in the conversion efficiency of the solar cell 100. At the same time, optimizing the different depths of electrode insertion helps to improve the overall performance of the solar cell 100, especially its charge collection efficiency and the stability of current transmission.

[0062] It can be understood that the drawings of the present invention are only exemplary drawings, and the layers in the drawings are not necessarily drawn in proportion to the actual situation. The stacked parts of the layers may be aligned or not aligned in the vertical direction, which is not limited here.

[0063] Embodiment 2

[0064] On the basis of the first embodiment, when the doping layer 121 is a polysilicon layer, the contact area between the end surface of the first electrode and the diffusion layer is greater than the contact area between the end surface of the second electrode 170 and the doping layer 121 .

[0065] The contact area refers to the sum of the contact areas of the bottom and the side. The contact resistance between the electrode and the semiconductor material is inversely proportional to the contact area. A larger contact area means a lower contact resistance. The first electrode 160 has a larger contact area with the diffusion layer 111, which helps to reduce the contact resistance, thereby improving the current collection and conduction efficiency.

[0066] Compared with other silicon materials (such as single crystal silicon), the polysilicon layer has more grain boundaries and defects, which may become the recombination centers of carriers, increase non-radiative recombination, and reduce the efficiency of the battery. The contact area between the second electrode 170 and the polysilicon layer is small, which can reduce the influence of grain boundaries and defect areas, reduce the recombination rate of carriers, and thus improve the effective extraction rate of photogenerated carriers.

[0067] Embodiment 3

[0068] like Figure 7 As shown, based on the first embodiment, when the doping layer 121 is doped amorphous silicon or doped microcrystalline silicon, the second electrode 170 is connected to the doping layer 121 through the TCO layer 171, and the connection depth between the second electrode 170 and the doping layer 121 is 0.

[0069] Although the conductivity of doped amorphous silicon and doped microcrystalline silicon is improved due to doping, it is still not comparable to crystalline silicon. In particular, the inherent disordered structure of doped amorphous silicon significantly limits the mobility of carriers, resulting in lower conductivity. Amorphous silicon is disordered, and although microcrystalline silicon has a partial crystalline structure, it still contains more disordered regions and grain boundaries. These structural defects will increase the scattering and recombination of carriers, further reducing the conductivity of the material.

[0070] TCO (e.g., ITO, indium tin oxide) is a transparent and well-conducting material that provides a conductive path without blocking light. By using the TCO layer 171 instead of direct metal electrode contact, the transmittance of light to the solar cell can be improved, the reflection and absorption loss of light can be reduced, and the light capture ability can be enhanced, thereby improving the photoelectric conversion efficiency. The TCO layer 171 provides high conductivity and transparency, ensuring that the current can be smoothly transmitted from the amorphous silicon or microcrystalline silicon layer to the electrode without being affected by the above-mentioned conductivity limitations.

[0071] The TCO layer 171 is stacked on the doping layer 121, and the second electrode 170 is disposed on the TCO layer 171, and the end surface of the second electrode 170 is in contact with the TCO layer 171. The second electrode 170 is not directly connected to the doping layer 121, but is connected through the TCO layer 171, and the connection depth between the second electrode 170 and the doping layer 121 is 0.

[0072] Embodiment 4

[0073] like Figure 2 As shown, based on the first embodiment, the second region 120 partially overlaps with the first region 110, the doping layer 121 includes a first portion 1211, a second portion 1213, and a third portion 1212 connecting the first portion 1211 and the second portion 1213, and the first portion 1211 is disposed in the overlapping region of the second region 120 and the first region 110, and is disposed on the diffusion layer 111;

[0074] An insulating layer 130 is disposed between the diffusion layer 111 and the first portion 1211 , and a tunneling layer 140 is disposed on the bottom surface of the second portion 1213 and the inner side surface of the third portion 1212 .

[0075] In this embodiment, N and P need to be diffused or doped twice on the back side of the silicon substrate 150. N may be diffused first and then doped, or P may be diffused first and then doped. For example, the diffusion layer 111 is P-type, the doping layer 121 is N-type, and P-type diffusion is performed first and then N-type doping is performed:

[0076] The first P-type diffusion is performed in the first region 110 on the back side of the silicon substrate 150, and dopants such as boron are introduced into the silicon substrate 150 to form a P-type diffusion layer 111. The second N-type doping is performed in the second region 120 on the back side of the silicon substrate 150, and dopants such as phosphorus are introduced into the silicon substrate 150 to form an N-type doping layer 121. Since the second region 120 partially overlaps with the first region 110, when the N-type doping is performed, the N-type dopant is partially superimposed on the P-type doping layer 121 to form a step surface.

[0077] After the P-type diffusion is completed and before the N-type doping begins, a tunneling layer 140 is introduced. Common materials used for the tunneling layer 140 include SiO2, Al2O3, SiNx, etc. The tunneling layer 140 is isolated between the doped layer 121 and the adjacent layers, and has a partitioning effect, which reduces the interface defects and recombination centers between the doped layer 121 and the silicon substrate 150, and improves the lifetime and collection efficiency of photogenerated carriers.

[0078] The first portion 1211 is disposed in the overlapping region of the second region 120 and the first region 110, and is stacked on the P-type diffusion layer 111. The second portion 1213 is located in the portion of the second region 120 that does not overlap with the first region 110, forming a pure N-type doped region. An insulating layer 130 is disposed between the diffusion layer 111 and the first portion 1211 to prevent the P-type diffusion layer 111 from directly contacting the N-type first portion 1211. The third portion 1212 connects the first portion 1211 and the second portion 1213, and is in electrical contact with the P-type doped layer 121 through the tunneling layer 140 on the side of the third portion 1212, thereby ensuring electrical contact between the doped layer 121 and the diffusion layer 111.

[0079] In some embodiments, an interface passivation layer 180 is disposed between the first portion 1211 and the diffusion layer 111 in the first region 110 .

[0080] Specifically, the interface passivation layer 180 can be made of the same material as the tunneling layer 140 and can be formed in the same process step as the tunneling layer 140. In this process, the tunneling material is deposited, and the layer deposited on the bottom surface of the second portion 1213 and the inner side surface of the third portion 1212 is the tunneling layer 140, and the layer deposited between the first portion 1211 and the insulating layer 130 is the interface passivation layer 180.

[0081] It can be completed in the same process, and the tunneling layer 140 and the interface passivation layer 180 can be connected.

[0082] Embodiment 5

[0083] like Figure 4 As shown, based on the third embodiment, the distance between the diffusion layer 111 and the front surface of the silicon substrate 150 is greater than the distance between the second portion 1213 and the front surface of the silicon substrate 150, the diffusion layer 111 extends toward the adjacent doping layer 121, the insulating layer 130 extends along the diffusion layer 111, and the tunneling layer 140 and the doping layer 121 form a protrusion along the extension direction of the diffusion layer 111.

[0084] The distance between the diffusion layer 111 and the front of the silicon substrate 150 is greater than the distance between the second part 1213 and the two are staggered in the vertical direction and are not in the same horizontal plane. The diffusion layer 111 extends to the adjacent side where the second part 1213 is provided, but because it is staggered in the vertical direction with the second part 1213, the extended diffusion layer 111 does not overlap with the second part 1213. The diffusion layer 111 has a larger coverage area, further increasing the illumination area. The insulating layer 130 extends closely following the diffusion layer 111 to provide electrical isolation and protection. The tunneling layer 140 and the doping layer 121 form a convex position along the extension direction of the diffusion layer 111 and the insulating layer 130, enclosing the extended parts of the diffusion layer 111 and the insulating layer 130.

[0085] Embodiment 6

[0086] Based on the first embodiment, the horizontal direction is the first direction, the first region 110 and the second region 120 are spaced apart along the first direction; the two opposite sides of the tunneling layer 140 along the first direction contact the diffusion layer 111 and the doping layer 121 respectively.

[0087] The silicon substrate 150 is placed on a placement plane, and the direction parallel to the placement plane is the horizontal direction of the present application, which is the first direction. Along the first direction, the first region 110 and the second region 120 are spaced apart, that is, the diffusion layer 111 and the doping layer 121 are spaced apart. And there is a region in which the diffusion layer 111, the tunneling layer 140 and the doping layer 121 are adjacent in sequence along the first direction.

[0088] Embodiment 7

[0089] Based on the first embodiment, the surface of the silicon substrate 150 facing the doping layer 121 is a polished surface.

[0090] The area covered by the projection of the doping layer 121 on the silicon substrate 150 has a polished surface. The polished surface means that the surface becomes very smooth after fine processing and has a low surface roughness. A smoother surface is easier to perform subsequent processing and doping control, which helps to improve the production yield and the overall reliability of the solar cell 100.

[0091] Embodiment 8

[0092] like Figure 3 and Figure 8 As shown, based on the third embodiment, the horizontal direction is the first direction, and the first area 110 and the second area 120 are arranged at intervals along the first direction;

[0093] Along the first direction, a groove 190 is provided between some adjacent diffusion layers 111 and doping layers 121 , the groove 190 isolates the doping layer 121 and the diffusion layer 111 , and the distance between the bottom of the groove 190 and the front surface of the silicon substrate 150 is smaller than the distance between the second portion 1213 and the front surface of the silicon substrate 150 .

[0094] The groove 190 penetrates the corresponding tunneling layer 140 and the doping layer 121, so that the doping layer 121 and the diffusion layer 111 are isolated. This physical isolation helps to avoid mutual diffusion between different doping regions, thereby maintaining the electrical characteristics and functional stability of each region and reducing current leakage and carrier recombination.

[0095] Embodiment 9

[0096] Based on the eighth embodiment, the total area of ​​the grooves accounts for more than or equal to 20% of the total front area of ​​the silicon substrate 150 .

[0097] When the total area of ​​the grooves accounts for 20% or more of the total area of ​​the back side of the silicon substrate 150, it means that the grooves with a larger area are distributed in the working area of ​​the battery. This design helps to strengthen the electrical isolation effect between the doping layer 121 and the diffusion layer 111 and reduce the mutual interference between different functional areas. The grooves with a larger area can also effectively guide the separation and transmission path of photogenerated carriers, reduce the recombination of carriers in undesirable areas, and thus improve the photoelectric conversion efficiency of the battery.

[0098] Embodiment 10

[0099] like Figure 8 As shown, based on the eighth embodiment, the edge of the diffusion layer 111 is not connected to the wall of the groove 190 .

[0100] The diffusion layer 111 is not diffused over the entire surface of the silicon substrate in the first region, but diffused in a targeted manner to a portion of the first region. Specifically, this can be achieved through a dispensing process, which is used to accurately apply the dopant to a specific area, and then the dopant is allowed to enter the surface of the silicon substrate through a diffusion process.

[0101] In the conventional structure, the diffusion layer 111 is connected to the wall of the groove 190, which may increase the recombination of carriers, because the grain boundaries and defects are mostly concentrated near the wall of the groove 190. By making the edge of the diffusion layer 111 not connected to the wall of the groove 190, the non-radiative recombination phenomenon caused by the grain boundaries and defects can be effectively reduced, and the lifetime of photogenerated carriers can be increased, thereby improving the efficiency of the solar cell.

[0102] Embodiment 11

[0103] Based on the first embodiment, the glass frit content in the first electrode 160 is less than the glass frit content in the second electrode 170 .

[0104] The main function of glass frit (usually glass powder) in the electrode is to enhance the adhesion of the electrode material, improve the contact quality between the electrode and the silicon wafer, and also help to form a stable electrical connection during the sintering process. By reducing the glass frit content in the first electrode 160, it means that the first electrode 160 may focus more on conductivity and low contact resistance, while the second electrode 170 has better mechanical strength and adhesion due to the higher glass frit content.

[0105] Reducing the content of glass frit in the first electrode 160 can reduce the resistance of the electrode material and improve the conductivity, thereby reducing the contact resistance between the electrode and the silicon substrate 150, which helps to improve the efficiency and output power of the battery. The second electrode 170 contains a higher amount of glass frit, which can enhance the mechanical strength and adhesion of the electrode, ensure the stability and reliability of the electrode in long-term use, and help prevent the electrode material from falling off or cracking during sintering or operation.

[0106] Specifically, the first electrode 160 and the second electrode 170 can be prepared step by step to achieve precise control of the glass material content of the first electrode 160 and the second electrode 170. At the same time, combined with the laser enhanced contact optimization (LECO) process, the contact resistance between the electrode and the silicon substrate 150 is optimized, and differentiated electrical properties are achieved in different regions.

[0107] Embodiment 12

[0108] Based on the first embodiment, a surface of the diffusion layer 111 facing the insulation layer 130 is a velvet surface.

[0109] The velvet surface usually refers to a tiny cone or pyramid structure formed on the surface of a silicon wafer by chemical or physical etching. This surface structure can increase the surface area of ​​the silicon wafer and increase the scattering and absorption of light when light hits the surface of the silicon wafer, thereby reducing reflection loss.

[0110] Embodiment 13

[0111] Based on the fourth embodiment, the difference between the distance between the diffusion layer 111 and the front surface of the silicon substrate 150 and the distance between the second portion 1213 and the front surface of the silicon substrate 150 is 1 μm to 6 μm.

[0112] See also Figure 2In H, the distance between the diffusion layer 111 and the second part 1213 along the vertical direction is 1μm to 6μm, and can be specifically 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, 3μm, 3.5μm, 3.9μm, 4μm, 4.5μm, 4.8μm, 5μm, 5.3μm, 5.6μm, 5.9μm, 6μm, etc., and the above are not exhaustive examples.

[0113] Through such distance control, a stronger built-in electric field can be formed between the diffusion layer 111 and the second portion 1213, which promotes the effective separation of photogenerated carriers and reduces recombination losses, thereby improving the photoelectric conversion efficiency of the battery.

[0114] Embodiment 14

[0115] On the basis of the first embodiment, the diffusion layer 111 is P-type doped single crystal silicon; the doping layer 121 is N-type doped polycrystalline silicon.

[0116] Single crystal silicon is a material with a highly ordered crystal structure and no grain boundaries or other large-area defects. Due to its highly consistent lattice arrangement, single crystal silicon can ensure uniform distribution of doping atoms during the diffusion process, forming a high-quality diffusion layer 111. P-type single crystal silicon has high carrier mobility and low defect density, and can provide better electrical performance and photoelectric conversion efficiency.

[0117] The production process of polysilicon is relatively simple and low in cost, making it an ideal choice for large-area doped layers 121. The doping concentration of polysilicon can be easily controlled during chemical vapor deposition (CVD) or physical vapor deposition (PVD). By adjusting the deposition parameters, polysilicon can achieve different doping concentrations and distributions, thereby optimizing the electrical properties of the doped layer 121 and improving the overall efficiency of the solar cell 100. N-type doped polysilicon is not only low in cost, but also can achieve uniform control of doping concentration over a large area, and is suitable for large-scale manufacturing.

[0118] The combination of P-type single-crystalline silicon and N-type polycrystalline silicon takes full advantage of the advantages of both materials to form a highly efficient heterojunction structure. Single-crystalline silicon provides high mobility and low recombination loss, while polycrystalline silicon further enhances cell performance through its doping flexibility and cost-effectiveness.

[0119] Embodiment 15

[0120] This embodiment provides a photovoltaic assembly, including the solar cell 100 of the above embodiment.

[0121] Typically, multiple solar cells 100 in a photovoltaic module can be connected in series in sequence to form a battery string. The battery strings can be connected in series, in parallel, or in a combination of series and parallel to achieve current bus output. For example, the connection between the solar cells 100 can be achieved by welding welding strips, and the connection between the battery strings can be achieved by bus bars.

[0122] The beneficial effects of the photovoltaic module of this embodiment are equivalent to the beneficial effects of the above-mentioned solar cell 100, and will not be described in detail here.

[0123] Embodiment 16

[0124] This embodiment provides a photovoltaic system, including the photovoltaic assembly of the above embodiment.

[0125] The beneficial effects of the photovoltaic system of this embodiment are equivalent to the beneficial effects of the above-mentioned solar cell 100, and will not be described in detail here.

[0126] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate having a back surface and a front surface arranged opposite to each other; A diffusion layer located in a first region on the back side of the silicon substrate; a doping layer located in a second region on the back side of the silicon substrate, the doping layer comprising at least one of doped amorphous silicon, doped microcrystalline silicon and doped polycrystalline silicon, the doping layer and the diffusion layer being doped to different polarities; A tunneling layer, wherein two opposite surfaces of the tunneling layer are in contact with the diffusion layer and the doping layer respectively; as well as A first electrode connected to the diffusion layer and a second electrode connected to the doping layer, wherein the first electrode is not conductive to the doping layer; A connection depth of the first electrode extending into the diffusion layer is greater than a connection depth of the second electrode extending into the doping layer.

2. The solar cell according to claim 1, characterized in that When the doped layer is a polysilicon layer, a contact area between an end surface of the first electrode and the diffusion layer is larger than a contact area between an end surface of the second electrode and the doped layer.

3. The solar cell according to claim 1, characterized in that When the doping layer is doped amorphous silicon or doped microcrystalline silicon, the second electrode is connected to the doping layer through the TCO layer, and the connection depth between the second electrode and the doping layer is zero.

4. The solar cell according to claim 1, characterized in that The second region partially overlaps with the first region, the doping layer includes a first portion, a second portion, and a third portion connecting the first portion and the second portion, the first portion is disposed in an overlapping region of the second region and the first region, and is disposed on the diffusion layer; An insulating layer is disposed between the diffusion layer and the first portion, and the tunneling layer is disposed on the bottom surface of the second portion and the inner side surface of the third portion.

5. The solar cell according to claim 4, characterized in that: The distance between the diffusion layer and the front surface of the silicon substrate is greater than the distance between the second portion and the front surface of the silicon substrate. The diffusion layer and the insulating layer extend toward the adjacent doping layer. The tunneling layer and the doping layer form a convex position along the extension direction of the diffusion layer.

6. The solar cell according to claim 1, characterized in that: The horizontal direction is a first direction, and the first region and the second region are arranged at intervals along the first direction; two opposite surfaces of the tunneling layer along the first direction contact the diffusion layer and the doping layer respectively.

7. The solar cell according to claim 1, characterized in that The surface of the silicon substrate facing the doping layer is a polished surface.

8. The solar cell according to claim 4, characterized in that An interface passivation layer is disposed between the first portion and the insulating layer in the first region.

9. The solar cell according to claim 8, characterized in that The tunneling layer is connected to the interface passivation layer.

10. The solar cell according to claim 4, characterized in that: The horizontal direction is a first direction, and the first area and the second area are arranged at intervals along the first direction; Along the first direction, a groove is provided between some adjacent diffusion layers and doping layers, the groove isolating the doping layer and the diffusion layer, and the distance between the bottom of the groove and the front surface of the silicon substrate is smaller than the distance between the second portion and the front surface of the silicon substrate.

11. The solar cell according to claim 10, characterized in that The total area of ​​the grooves accounts for more than or equal to 20% of the total area of ​​the back side of the silicon substrate.

12. The solar cell according to claim 10, characterized in that: The edge of the diffusion layer is not connected to the groove wall of the groove.

13. The solar cell according to claim 1, characterized in that: The glass frit content in the first electrode is less than the glass frit content in the second electrode.

14. The solar cell according to claim 4, characterized in that The diffusion layer has a velvet surface facing the insulation layer.

15. The solar cell according to claim 4, characterized in that: A difference between a distance between the diffusion layer and the front surface of the silicon substrate and a distance between the second portion and the front surface of the silicon substrate is 1 μm to 6 μm.

16. The solar cell according to claim 1, characterized in that: The diffusion layer is P-type doped single-crystal silicon; the doping layer is N-type doped polycrystalline silicon.

17. A photovoltaic module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 16.

18. A photovoltaic system, characterized in that: Comprising the photovoltaic module described in claim 17.

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