Image sensor

Abstract

An image sensor includes: a semiconductor substrate including a pixel array region including a center pixel region and an edge pixel region surrounding the center pixel region in a plan view; color filter groups on the pixel array area, each of the color filter groups including color filters arranged in the same number of rows and columns; and microlenses covering the color filter groups, respectively, in which the color filter groups include a center color filter group on the center pixel region and edge color filter groups on the edge pixel regions, at least two color filters of the color filters in each edge color filter group having thicknesses different from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0089000 filed on July 10, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to image sensors, and in particular, to image sensors having improved electrical and optical properties. Background Art

[0004] Image sensor is a device that converts optical signal into electrical signal. With the development of computer and communication industry, the demand for high performance image sensor is growing in various applications such as digital camera, video camera, personal communication system, game console, security camera, miniature camera for medical application, and / or robot. Image sensor is generally classified into charge coupled device (CCD) image sensor and complementary metal oxide semiconductor (CMOS) image sensor. CMOS image sensor can be operated in a simplified manner, and because the signal processing circuit of CMOS image sensor can be integrated on a single chip, the size of the product with CMOS image sensor can be reduced. In addition, because CMOS image sensor can be operated with relatively low power consumption, it can be easily applied to electronic devices with limited battery capacity. In addition, because CMOS image sensor can be manufactured using existing CMOS manufacturing technology, its manufacturing cost can be reduced. In addition, due to the increase of resolution of CMOS image sensor, the use of CMOS image sensor is growing rapidly. Summary of the invention

[0005] One or more embodiments provide an image sensor having improved optical properties.

[0006] According to one aspect of an example embodiment, an image sensor includes: a semiconductor substrate including a pixel array area, the pixel array area including a central pixel area and an edge pixel area surrounding the central pixel area in a plan view; a color filter group on the pixel array area, each of the color filter groups including color filters arranged in the same number of rows and columns; and microlenses covering the color filter groups, respectively, wherein the color filter groups include a central color filter group on the central pixel area and an edge color filter group on the edge pixel area, and at least two of the color filters in each edge color filter group have different thicknesses from each other.

[0007] According to one aspect of an example embodiment, an image sensor includes: a semiconductor substrate of a first conductivity type, the semiconductor substrate including a pixel array area, a first surface, and a second surface opposite to the first surface; a photoelectric conversion area in the pixel array area, the photoelectric conversion area including impurities of a second conductivity type; a color filter group covering at least a portion of the pixel array area, each color filter group in the color filter group including a first color filter, a second color filter, a third color filter, and a fourth color filter arranged in two rows and two columns; and microlenses covering the color filter groups, respectively, wherein the pixel array area includes a central pixel area and an edge pixel area surrounding the central pixel area in a plan view, the color filter group includes a central color filter group on the central pixel area and an edge color filter group on the edge pixel area, and in each edge color filter group of the edge color filter groups, a thickness of the first color filter is greater than a thickness of the second color filter.

[0008] According to one aspect of an example embodiment, an image sensor includes: a semiconductor substrate including a light receiving area, a light blocking area, a pad area, a first surface, and a second surface opposite to the first surface; a pixel isolation structure, in the light receiving area and the light blocking area of ​​the semiconductor substrate, the pixel isolation structure defines a pixel area; a photoelectric conversion area, in the light receiving area and the light blocking area of ​​the semiconductor substrate; a color filter group on the first surface, each of the color filter groups including a first color filter, a second color filter, a third color filter, and a fourth color filter arranged in two rows and two columns; a transfer gate electrode on the second surface; a pixel circuit layer on the second surface; and microlenses covering the color filter groups, respectively, wherein the light receiving area includes a central pixel area and an edge pixel area surrounding the central pixel area in a plan view, the color filter group includes a central color filter group on the central pixel area and an edge color filter group on the edge pixel area, and in each edge color filter group, the thickness of the first color filter is greater than the thickness of the second color filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing an image sensor according to an embodiment;

[0011] Figure 2A is a circuit diagram showing a unit pixel of an image sensor according to an embodiment;

[0012] Figure 2B is a circuit diagram showing a unit pixel of an image sensor according to an embodiment;

[0013] Figure 3 is a plan view showing an image sensor according to an embodiment;

[0014] Figure 4 It is shown Figure 3 An enlarged plan view of a light receiving area;

[0015] Figure 5A It is shown Figure 4 an enlarged plan view of a portion P1;

[0016] Figure 5B It is shown Figure 4 An enlarged plan view of a portion P1';

[0017] Fig. 6A It is along Figure 5A A cross-sectional view of an image sensor according to an embodiment is shown by taking a line AA' of FIG.

[0018] Figure 6B It is along Figure 5A A cross-sectional view of an image sensor according to an embodiment is shown by taking a line BB' of FIG.

[0019] Figure 6C It is along Figure 5A A cross-sectional view of an image sensor according to an embodiment is shown by taking a line CC' of FIG.

[0020] Figure 7 It is shown Figure 4 an enlarged plan view of a portion P2;

[0021] Fig. 8A It is along Figure 7 A cross-sectional view of an image sensor according to an embodiment is shown by taking line II' of FIG.

[0022] Figure 8B It is along Figure 7 A cross-sectional view of an image sensor according to an embodiment is shown by taking line II-II' of FIG.

[0023] Figure 8C It is along Figure 7 A cross-sectional view of an image sensor according to an embodiment is shown by taking line III-III' of FIG.

[0024] Fig. 9 is a plan view showing an image sensor according to an embodiment;

[0025] Fig.10 is a plan view showing an image sensor according to an embodiment;

[0026] Fig.11 is a cross-sectional view showing an image sensor according to an embodiment;

[0027] Fig.12is a cross-sectional view showing an image sensor according to an embodiment;

[0028] Fig.13 is a cross-sectional view showing an image sensor according to an embodiment;

[0029] Fig.14 is a plan view showing an image sensor according to an embodiment;

[0030] Fig.15 It is along Fig.14 A cross-sectional view of an image sensor according to an embodiment is shown by taking a line AA' of FIG.

[0031] Fig.16 is a plan view showing an image sensor according to an embodiment;

[0032] Fig.17 It is along Fig.16 A cross-sectional view of an image sensor according to an embodiment is shown by taking a line AA' of FIG.

[0033] Fig.18A It is along Figure 3 A cross-sectional view of an image sensor according to an embodiment is shown by taking a line AA′ of FIG.

[0034] Fig.18B It is along Figure 3 A cross-sectional view of an image sensor according to an embodiment is shown taken along line AA′. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. Like reference numerals in the drawings represent like elements, and thus their description will be omitted.

[0036] Figure 1 is a block diagram showing an image sensor according to an embodiment.

[0037] Reference Figure 1 The image sensor may include an active pixel sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7 and an input / output (I / O) buffer 8.

[0038] The active pixel sensor array 1 may include a plurality of unit pixels arranged two-dimensionally and configured to convert optical signals into electrical signals. The active pixel sensor array 1 may be driven by a plurality of driving signals (such as pixel selection signals, reset signals, and charge transfer signals) sent from a row driver 3. In addition, the converted electrical signals may be provided to a correlated double sampler 6.

[0039] The row driver 3 may be configured to provide a driving signal for driving the plurality of unit pixels to the active pixel sensor array 1 based on a result decoded by the row decoder 2. In the case where the unit pixels are arranged in a matrix shape (ie, in rows and columns), the driving signal may be provided to the corresponding row.

[0040] The timing generator 5 may be configured to provide timing signals and control signals to the row decoder 2 and the column decoder 4 .

[0041] The CDS 6 may be configured to receive the electrical signal generated in the active pixel sensor array 1 and perform a hold and sampling operation on the received electrical signal. For example, the CDS 6 may perform a double sampling operation on the signal level and a specific noise level of the electrical signal and may output a difference level corresponding to the difference between the noise level and the signal level.

[0042] The ADC 7 may be configured to convert an analog signal corresponding to the difference level output from the CDS 6 into a digital signal and then output the converted digital signal to the I / O buffer 8 .

[0043] The I / O buffer 8 may be configured to latch the digital signal and sequentially output the latched digital signal to the image signal processing unit based on the result of decoding by the column decoder 4 .

[0044] Figure 2A and Figure 2B are circuit diagrams, each of which shows a unit pixel of an image sensor according to an embodiment.

[0045] Reference Figure 2A , the unit pixel P may include a first photoelectric conversion device PD1 and a second photoelectric conversion device PD2, a first transfer transistor TX1 and a second transfer transistor TX2, and four pixel transistors. For example, each of the four pixel transistors may correspond to a reset transistor RX, a source follower transistor SF, a selection transistor SEL, and a dual conversion gain transistor DCX, but the embodiments of the present disclosure are not limited to this example. In other words, the pixel transistor may be provided in each unit pixel P in various ways.

[0046] The first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 may be configured to generate charges in response to incident light, in which case the generated charges may be accumulated in the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2. In an embodiment, the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 may be a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and a combination thereof.

[0047] The first transfer transistor TX1 and the second transfer transistor TX2 may be configured to transfer the charge accumulated in the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 to the floating diffusion area FD. The first transfer transistor TX1 and the second transfer transistor TX2 may be controlled by a signal applied to the first transfer gate electrode TG1 and the second transfer gate electrode TG2. The first transfer transistor TX1 and the second transfer transistor TX2 may share the floating diffusion area FD, but the embodiments of the present disclosure are not limited to this example. For example, the first transfer transistor TX1 and the second transfer transistor TX2 may be respectively connected to different floating diffusion areas FD from each other.

[0048] The floating diffusion area FD may be configured to receive charges generated in the first photoelectric conversion device PD1 or the second photoelectric conversion device PD2 and accumulatively store the charges therein. The source follower transistor SF may be controlled by the amount of photocharges accumulated in the floating diffusion area FD.

[0049] The reset transistor RX may periodically initialize the charge accumulated in the floating diffusion region FD by a reset signal applied to the reset gate electrode RG. In detail, the reset transistor RX may include a drain terminal connected to the dual conversion gain transistor DCX and a drain terminal connected to the pixel power supply voltage V DD If the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel supply voltage V DD The electric charge may be transferred to the floating diffusion area FD. Therefore, the electric charge may be discharged from the floating diffusion area FD, and in this case, the floating diffusion area FD may be initialized.

[0050] The dual conversion gain transistor DCX may be provided between and connected to the floating diffusion region FD and the reset transistor RX. The dual conversion gain transistor DCX may control the conversion gain by changing the capacitance of the floating diffusion region FD in response to a dual conversion gain control signal applied to the dual conversion gain gate electrode DCG. Different conversion gains may be achieved by the operation of the dual conversion gain transistor DCX. Therefore, the dual conversion gain transistor DCX may be turned on in a high brightness mode and may be turned off in a low brightness mode.

[0051] The source follower transistor SF may be a source follower buffer amplifier configured to generate a source-drain current proportional to the amount of charge of the floating diffusion area FD to be input to the source follower gate electrode. The source follower transistor SF may amplify the potential change of the floating diffusion area FD and may output the amplified signal to the output line Vout through the selection transistor SEL. The source follower transistor SF may include a transistor connected to the pixel power supply voltage V DD and a drain terminal connected to the source terminal of the selection transistor SEL.

[0052] The selection transistor SEL may be used to select a row of unit pixels P to be read out during a read operation. If the selection transistor SEL is turned on by a selection signal applied to the selection gate electrode SG, an electrical signal output to the drain electrode of the source follower transistor SF may be output to the output line Vout.

[0053] Reference Figure 2B , the unit pixel P may include first to fourth photoelectric conversion devices PD1 , PD2 , PD3 , and PD4 , first to fourth transfer transistors TX1 , TX2 , TX3 , and TX4 , and four pixel transistors.

[0054] The first to fourth transfer transistors TX1, TX2, TX3, and TX4 may share a floating diffusion region FD. The first to fourth transfer transistors TX1, TX2, TX3, and TX4 may be controlled by signals applied to the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4.

[0055] The four pixel transistors may correspond to the reference Figure 2A The reset transistor RX, the source follower transistor SF, the select transistor SEL and the dual conversion gain transistor DCX are described.

[0056] Figure 3 is a plan view showing an image sensor according to an embodiment. Figure 4 It is shown Figure 3 An enlarged plan view of the light receiving area.

[0057] Reference Figure 3 and Figure 4 , the image sensor may include a pixel array region R1 and a pad region R2.

[0058] The pixel array region R1 may include a plurality of pixels P arranged two-dimensionally in two different directions (e.g., in a first direction D1 and a second direction D2). Each pixel P may include a photoelectric conversion device and a readout device. Each pixel P of the pixel array region R1 may be configured to output an electrical signal generated by incident light.

[0059] The pixel array region R1 may include a light receiving region AR and a light blocking region OB. When viewed in a plan view, the light blocking region OB may surround the light receiving region AR. For example, when viewed in a plan view, the light blocking region OB may be provided to surround the light receiving region AR in four different directions (e.g., an upper direction, a lower direction, a left direction, and a right direction). In an embodiment, a reference pixel P into which light is not incident may be provided in the light blocking region OB, in which case the magnitude of the electrical signal generated by the unit pixel P may be calculated by comparing the amount of charge obtained from the unit pixel P in the light receiving region AR with the amount of charge generated in the reference pixel P.

[0060] In the light receiving area AR, the pixel array area R1 may include a central pixel area CR in which a plurality of pixels are arranged, and an edge pixel area ER provided to surround the central pixel area CR when viewed in a plan view. That is, when viewed in a plan view, the edge pixel area ER may be provided to surround the central pixel area CR in four different directions (e.g., an upper direction, a lower direction, a left direction, and a right direction). Here, the angle of incident light incident into the edge pixel area ER may be different from the angle of incident light incident into the central pixel area CR.

[0061] Color filters and micro lenses may be disposed on the pixel array region R1.

[0062] Color filters may be disposed on the pixel array region R1 to respectively cover the pixels P. The color filters may be arranged in n rows and n columns (ie, the same number of rows and columns) to form color filter groups ECFG, ECFG′, and CCFG.

[0063] The color filter may include a red color filter, a green color filter, and a blue color filter. The red color filter, the green color filter, and the blue color filter may be configured to allow selective transmission of incident light incident from the outside.

[0064] The microlenses may be configured to collect incident light incident from the outside. When viewed in a plan view, the microlenses may be two-dimensionally arranged in two different directions (eg, a first direction D1 and a second direction D2).

[0065] In an embodiment, each microlens may be provided to cover one of the color filter groups. In an embodiment, each microlens may cover a color filter group in which the color filters are arranged in two rows and two columns. FIG. 5A to FIG. 10 The color filters and microlenses are described in more detail.

[0066] Figure 5A It is shown Figure 4 An enlarged plan view of portion P1. Figure 5B It is shown Figure 4 An enlarged plan view of portion P1'. FIG. 6A to FIG. 6C Along the Figure 5A , taken along lines AA′, BB′, and CC′ to illustrate a cross-sectional view of an image sensor according to an embodiment. Figure 7 It is shown Figure 4 An enlarged plan view of portion P2. FIG. 8A to FIG. 8C Along the Figure 7 1 and 2 are taken along lines II′, II-II′, and III-III′ to illustrate cross-sectional views of an image sensor according to an embodiment. Fig. 9 and Fig.10 is a plan view showing an image sensor according to some embodiments.

[0067] Reference FIG. 5A to FIG. 10 , when viewed in a vertical cross section, the image sensor may include a photoelectric conversion layer 10 , a pixel circuit layer 20 , and an optically transparent layer 30 .

[0068] When viewed in a vertical cross section, the photoelectric conversion layer 10 may be disposed between the pixel circuit layer 20 and the optically transparent layer 30. The photoelectric conversion layer 10 may be configured to convert light incident from the outside into an electrical signal. The photoelectric conversion layer 10 may include a semiconductor substrate 100 and a pixel isolation structure DTI, a floating diffusion region FD, a device isolation layer 105, and a photoelectric conversion region PD placed in the semiconductor substrate 100.

[0069] In detail, the semiconductor substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The semiconductor substrate 100 may be a substrate including a bulk silicon substrate and an epitaxial layer, which are stacked in sequence and have a first conductivity type (e.g., p-type), and in the case where the bulk silicon substrate is removed during the manufacturing process of the image sensor, the semiconductor substrate 100 may consist of only a p-type epitaxial layer. In an embodiment, the semiconductor substrate 100 may be a bulk semiconductor substrate in which a well of a first conductivity type is formed. The first surface 100a of the semiconductor substrate 100 may face the color filter, and the second surface 100b of the semiconductor substrate 100 may face the pixel circuit layer 20.

[0070] In each pixel region PR, a device isolation layer 105 may be disposed near the second surface 100b of the semiconductor substrate 100. The device isolation layer 105 may be provided in a device isolation trench T1 formed by recessing the second surface 100b of the semiconductor substrate 100. The device isolation layer 105 may be formed of an insulating material or include an insulating material. The device isolation layer 105 may be formed near the second surface 100b to define an active portion in the semiconductor substrate 100. For example, the device isolation layer 105 may define a first active portion and a second active portion in the semiconductor substrate 100. The first active portion and the second active portion may be spaced apart from each other in each pixel region PR and may have sizes different from each other.

[0071] The pixel isolation structure DTI may be provided in a pixel isolation trench formed by recessing the first surface 100a of the semiconductor substrate 100. The pixel isolation structure DTI may define a plurality of pixel regions PR. The pixel isolation structure DTI may penetrate the semiconductor substrate 100 from the second surface 100b to the first surface 100a. The pixel isolation structure DTI may be provided as a portion of the through-device isolation layer 105. The pixel isolation structure DTI may include an insulating liner pattern 111, a semiconductor pattern 113, and an insulating gap filling pattern 115.

[0072] The pixel isolation structure DTI may include portions extending in the first direction D1 and parallel to each other, and portions extending in the second direction D2 and parallel to each other. When viewed in a plan view, the pixel isolation structure DTI may be provided to surround each pixel region PR or each photoelectric conversion region PD.

[0073] The pixel isolation structure DTI may have an upper width at a level near the second surface 100b of the semiconductor substrate 100, and may have a lower width at a level near the first surface 100a of the semiconductor substrate 100. The lower width may be smaller than the upper width. For example, the width of the pixel isolation structure DTI may decrease as it moves from the second surface 100b of the semiconductor substrate 100 to the first surface 100a. The pixel isolation structure DTI may have a length in the third direction D3. The length of the pixel isolation structure DTI may be substantially equal to the vertical thickness of the semiconductor substrate 100.

[0074] A photoelectric conversion region PD may be provided in the semiconductor substrate 100 of each pixel region PR. The photoelectric conversion region PD may generate photocharges proportional to the intensity of the incident light. The photoelectric conversion region PD may be formed by injecting impurities having a second conductivity type different from the semiconductor substrate 100 into the semiconductor substrate 100. The photoelectric conversion region PD of the second conductivity type and the semiconductor substrate 100 of the first conductivity type may form a pn junction serving as a photodiode. In an embodiment, each of the photoelectric conversion regions PD may be provided to have an impurity concentration difference between portions adjacent to the first surface 100a and the second surface 100b, thereby having a non-zero potential gradient between the first surface 100a and the second surface 100b of the semiconductor substrate 100. For example, the photoelectric conversion region PD may include a plurality of impurity regions stacked vertically.

[0075] The pixel circuit layer 20 may be disposed on the second surface 100b of the semiconductor substrate 100. The pixel circuit layer 20 may include a pixel circuit (eg, a MOS transistor) electrically connected to the photoelectric conversion region PD. Figure 2A The pixel transistors described (eg, reset transistor RX, select transistor SEL, dual conversion gain transistor DCX, and source follower transistor SF).

[0076] The transmission gate electrode TG may be located on the second surface 100b of the semiconductor substrate 100. The transmission gate electrode TG may be provided as a portion penetrating the semiconductor substrate 100. For example, when viewed in a vertical cross section, the transmission gate electrode TG may have a shape of a letter "T". A gate insulating layer GIL may be interposed between the transmission gate electrode TG and the semiconductor substrate 100.

[0077] The floating diffusion region FD may be provided in a portion of the first active portion located on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by implanting impurities into the semiconductor substrate 100, and may have a conductivity type different from that of the semiconductor substrate 100. For example, the floating diffusion region FD may be an impurity region (e.g., of the second conductivity type).

[0078] At least one pixel transistor may be provided in the second active portion in each pixel region PR. The pixel transistor provided in each pixel region PR may be a reference Figure 2A and Figure 2BAt least one of the reset transistor RX, the source follower transistor SF, the dual conversion gain transistor DCX and the selection transistor SEL described. The pixel transistor may include a pixel gate electrode provided to intersect with the second active portion, and a source / drain region provided in the second active portion and on both sides of the pixel gate electrode. The pixel gate electrode may have a bottom surface parallel to the top surface of the second active portion. The pixel gate electrode may be formed of at least one of doped polysilicon, a metal material, a conductive metal nitride material, a conductive metal silicide material, a conductive metal oxide material and a combination thereof, or include at least one of doped polysilicon, a metal material, a conductive metal nitride material, a conductive metal silicide material, a conductive metal oxide material and a combination thereof.

[0079] The interlayer insulating layer 210 may be placed on the second surface 100b of the semiconductor substrate 100 and may be composed of a plurality of layers. The interlayer insulating layer 210 may cover an interconnection structure connected to the transfer gate electrode TG and the pixel circuit. The interconnection structure may include a metal line 223 and a contact plug 221 connecting the metal lines 223 to each other.

[0080] The optical transparent layer 30 may be disposed on the first surface 100a of the semiconductor substrate 100. The optical transparent layer 30 may include a planarization insulating layer 310, a light blocking pattern 320, a protective layer 330, a color filter, micro lenses 340a and 340b, and a passivation layer. The optical transparent layer 30 may be configured to perform operations of focusing and filtering light incident from the outside, and provide the light to the photoelectric conversion layer 10.

[0081] In detail, the planarization insulating layer 310 may cover the first surface 100a of the semiconductor substrate 100. The planarization insulating layer 310 may be formed of a transparent insulating material and may include a plurality of layers. The planarization insulating layer 310 may be formed of an insulating material having a different refractive index from that of the semiconductor substrate 100. The planarization insulating layer 310 may be formed of or include at least one of a metal oxide and a silicon oxide. For example, the planarization insulating layer 310 may be formed of Al 2 O 3 , CeF 3 , HfO 2 、ITO、MgO、Ta 2 O 5 、TiO 2 、ZrO 2 , Si, Ge, ZnSe, ZnS and PbF 2 At least one of the following forms, or includes Al 2 O 3 , CeF 3 , HfO 2、ITO、MgO、Ta 2 O 5 、TiO 2 、ZrO 2 , Si, Ge, ZnSe, ZnS and PbF 2 At least one of. Optionally, the planarization insulating layer 310 may be formed of at least one of an organic material having a high refractive index (e.g., siloxane resin, benzocyclobutene (BCB), polyimide, acrylic, polychloroparaxylene (parylene C), poly(methyl methacrylate) (PMMA), polyethylene terephthalate (PET), etc.), or include at least one of the organic materials. In addition, the planarization insulating layer 310 may be formed of strontium titanate (SrTiO 3 ), polycarbonate, glass, bromine, sapphire, cubic zirconia, potassium niobate (KNbO 3 ), carbon silicon (SiC), gallium (III) phosphide (GaP) and gallium (III) arsenide (GaAs), or includes strontium titanate (SrTiO 3 ), polycarbonate, glass, bromine, sapphire, cubic zirconia, potassium niobate (KNbO 3 ), at least one of carbon silicon (SiC), gallium (III) phosphide (GaP) and gallium (III) arsenide (GaAs).

[0082] The light blocking pattern 320 may be disposed on the planarization insulating layer 310 to separate the color filter groups CFG from each other. When viewed in a plan view, similar to the pixel isolation structure DTI, the light blocking pattern 320 may have a lattice shape. When viewed in a plan view, the light blocking pattern 320 may overlap the pixel isolation structure DTI. That is, the light blocking pattern 320 may include a portion extending along the first direction D1 and a portion extending along the second direction D2. The width of the light blocking pattern 320 may be substantially equal to or less than the minimum width of the pixel isolation structure DTI. The light blocking pattern 320 may be formed of at least one of a metal material (e.g., titanium, tantalum, or tungsten), or include at least one of the metal materials.

[0083] Instead of the light blocking pattern 320, a low refractive pattern may be disposed on the planarization insulating layer 310. The low refractive pattern may be formed of a material having a lower refractive index than the light blocking pattern 320. The low refractive pattern may be formed of or include an organic material and may have a refractive index of about 1.1 to 1.3. For example, the light blocking pattern 320 may be a polymer layer containing silicon dioxide nanoparticles.

[0084] The protective layer 330 may cover the planarization insulating layer 310 and the light blocking pattern 320. The protective layer 330 may have a substantially constant thickness. The protective layer 330 may be a single layer structure or a multi-layer structure including at least one of an aluminum oxide layer and a silicon oxycarbide layer.

[0085] A color filter may be formed on a region of the protective layer 330 corresponding to the pixel region PR. The color filter may fill a space defined by the light blocking pattern 320. The color filter may include a red filter, a green filter, or a blue filter, or a magenta filter, a cyan filter, or a yellow filter, in which case the color of the color filter may be determined based on the position of the unit pixel.

[0086] The color filters may constitute color filter groups ECFG and CCFG arranged in n rows and n columns. Figure 5A , Figure 5B and Figure 7 , only four color filter groups CFG_a, CFG_b, CFG_c, and CFG_d / CFG_e and CFG_f are shown in each of the color filter groups ECFG and CCFG. Each of the color filter groups CFG_a, CFG_b, CFG_c, CFG_d, CFG_e, and CFG_f may be composed of color filters arranged in n rows and n columns, and may include first to fourth color filters (CF1_a to CF4_a, CF1_b to CF4_b, CF1_c to CF4_c, CF1_d to CF4_d, or CF1_e to CF4_e). As an example embodiment, in FIG. 5A to FIG. 10 4 shows color filter groups CFG_a, CFG_b, CFG_c, CFG_d, CFG_e, and CFG_f arranged in 2 rows and 2 columns.

[0087] The center color filter group CCFG can be set at Figure 4 The edge filter groups ECFG and ECFG' may be arranged on the central pixel region CR. Figure 4 The center color filter group CCFG and the edge color filter group ECFG are located at the edge pixel area ER. Figure 3 The positions on the pixel array region R1 may be different from each other. For example, when viewed in a plan view, the edge color filter groups ECFG and ECFG′ may be disposed to surround the center color filter group CCFG.

[0088] Microlenses 340a and 340b may be disposed on the color filters. In detail, microlenses 340a and 340b may be disposed to cover edge color filter groups ECFG and ECFG' and a center color filter group CCFG, respectively. As an example, each of microlenses 340a and 340b may cover a color filter group CFG_a, CFG_b, CFG_c, CFG_d, CFG_e, or CFG_f in which color filters are arranged in 2 rows and 2 columns.

[0089] The microlenses 340a and 340b may include a first microlens 340a covering the edge color filter groups ECFG and ECFG' and a second microlens 340b covering the center color filter group CCFG. When viewed in a plan view, the center of the first microlens 340a may be offset from the center of the edge color filter groups ECFG and ECFG', respectively. For example, the center of the first microlens 340a may be offset toward Figure 3 The incident light is offset in the direction of the center of the pixel array area R1. Figure 4 The light in the edge pixel region ER can be incident on the Figure 4 The area at the center of the edge pixel area ER.

[0090] The micro lenses 340a and 340b may have a convex shape and may have a certain radius of curvature. The micro lenses 340a and 340b may include an optically transparent resin.

[0091] A passivation layer may be provided on the microlens 340 to conformally cover the surfaces of the microlenses 340a and 340b. As an example, the passivation layer may be formed of or include an inorganic oxide material.

[0092] The filter set will refer to Fig. 9 and Fig.10 Give a description.

[0093] Each of the color filter groups CFG_1, CFG_2, CFG_3, and CFG_4 (CFG) may include first to fourth color filters CF1, CF2, CF3, and CF4 arranged in 2 rows and 2 columns. In the color filter groups CFG_1, CFG_2, CFG_3, and CFG_4 (CFG), the first color filter CF1 and the second color filter CF2 may be disposed to face each other in a diagonal direction, and the third color filter CF3 and the fourth color filter CF4 may be disposed to face each other in a diagonal direction.

[0094] Reference Fig. 9, the first to fourth color filters CF1, CF2, CF3, and CF4 in each of the color filter groups CFG_1, CFG_2, CFG_3, and CFG_4 may be configured to have the same color. As an example, each of the first to fourth color filters CF1, CF2, CF3, and CF4 in each of the color filter groups CFG_1, CFG_2, CFG_3, and CFG_4 may be one of a red color filter, a green color filter, and a blue color filter. As another example, the first to fourth color filters CF1, CF2, CF3, and CF4 in each of the color filter groups CFG_1, CFG_2, CFG_3, and CFG_4 may be provided to have complementary colors such as cyan, magenta, or yellow.

[0095] Reference Fig.10 , the first to fourth color filters CF1, CF2, CF3, and CF4 in each color filter group CFG may be configured to have different colors. As an example, each of the first color filter CF1 and the second color filter CF2 may include a green color filter, the third color filter CF3 may include a blue color filter, and the fourth color filter CF4 may include a red color filter. In each color filter group CFG, the first to fourth color filters CF1, CF2, CF3, and CF4 may be arranged in a Bayer pattern. As another example, the first to fourth color filters CF1, CF2, CF3, and CF4 in each of the color filter groups CFG_1, CFG_2, CFG_3, and CFG_4 may be provided to have complementary colors such as cyan, magenta, or yellow.

[0096] Return to reference FIG. 5A to FIG. 6C , the edge filter groups ECFG and ECFG' may include first to fourth edge filter groups CFG_a, CFG_b, CFG_c, and CFG_d disposed adjacent to each other. The first edge filter group CFG_a may include first to fourth color filters CF1_a, CF2_a, CF3_a, and CF4_a. Similarly, the second to fourth edge filter groups CFG_b, CFG_c, and CFG_d may include first to fourth color filters (CF1_b, CF2_b, CF3_b, and CF4_b / CF1_c, CF2_c, CF3_c, and CF4_c / CF1_d, CF2_d, CF3_d, and CF4_d), respectively.

[0097] Figure 5A Shows the settings Figure 3 The second edge filter group CFG_b may be located in the upper right direction of the first edge filter group CFG_a and away from the first edge filter group CFG_a. Figure 4In addition, in the first edge filter group CFG_a, the second color filter CF2_a may be located in the upper right direction of the first color filter CF1_a and farther away from the first color filter CF1_a. Figure 4 Similarly, the second color filters CF2_b, CF2_c, and CF2_d in the second to fourth edge color filter groups CFG_b, CFG_c, and CFG_d may represent a color filter that is farther away from the first color filters CF1_b, CF1_c, and CF1_d than the first color filters CF1_b, CF1_c, and CF1_d. Figure 4 A color filter is applied to the central pixel region CR.

[0098] Figure 5B Shows the settings Figure 3 The second edge filter group CFG_b may be located in the lower left direction of the first edge filter group CFG_a and away from the edge filter group ECFG'. Figure 4 In addition, in the first edge filter group CFG_a, the second color filter CF2_a may be located in the lower left direction of the first color filter CF1_a and farther away from the first color filter CF1_a. Figure 4 Similarly, the second color filters CF2_b, CF2_c, and CF2_d in the second to fourth edge color filter groups CFG_b, CFG_c, and CFG_d may represent a color filter that is farther away from the first color filters CF1_b, CF1_c, and CF1_d than the first color filters CF1_b, CF1_c, and CF1_d. Figure 4 A color filter is applied to the central pixel region CR.

[0099] In this specification, for the convenience of description, the following description relates to the device placed in Figure 3 The first edge filter group is located at the upper right corner of the pixel array region R1. However, the second to fourth edge filter groups may be located farther away from the first edge filter group. Figure 4 In addition, in each edge filter group, the second to fourth color filters may be color filters that are farther from the central pixel region than the first color filter.

[0100] In the first edge filter group CFG_a, the second color filter CF2_a may be disposed at a position greater than the first color filter CF1_a. Figure 3 Similarly, the third color filter CF3_a and the fourth color filter CF4_a may be located farther away from the first color filter CF1_a. Figure 4 The pixel region CR is located at a position adjacent to the first color filter CF1_a and the second color filter CF2_a.

[0101] In the first edge filter group CFG_a, the first to fourth color filters CF1_a, CF2_a, CF3_a, and CF4_a may have different thicknesses from each other. For example, the thickness T2a of the second color filter CF2_a may be less than the thickness T1a of the first color filter CF1_a. In addition, the thickness T3a of the third color filter CF3_a and the thickness T4a of the fourth color filter CF4_a may also be less than the thickness T1a of the first color filter CF1_a. Here, the thickness of each of the first to fourth color filters CF1_a, CF2_a, CF3_a, and CF4_a may represent a length measured in the third direction D3.

[0102] Unlike the center color filter group CCFG, the first edge color filter group CFG_a can be set at Figure 3 The edge of the pixel array region R1 is near the edge of the pixel array region R1, so the light may not be incident vertically into the first edge filter group CFG_a, and may be incident obliquely into the edge region of the first edge filter group CFG_a. Depending on the incident angle of the light, the propagation length of the light passing through the color filter may be different from the thickness of the color filter. In addition, in the case of Figure 3 In the first edge filter group CFG_a at the edge of the pixel array region R1, the incident angle of light passing through the first color filter CF1_a may be different from the incident angle of light passing through the second color filter CF2_a. Here, because the second color filter CF2_a is arranged outside the first color filter CF1_a, the incident angle of light passing through the second color filter CF2_a may be greater than the incident angle of light passing through the first color filter CF1_a. In the case where the first to fourth color filters CF1_a, CF2_a, CF3_a and CF4_a have the same thickness, the amount of light of the incident light passing through the second color filter CF2_a may be less than the amount of light of the incident light passing through the first color filter CF1_a. Therefore, there may be a difference in the amount of light between the light passing through the first color filter CF1_a and the second color filter CF2_a. This may cause a channel difference problem in the image sensor.

[0103] In contrast, according to an embodiment, the second color filter CF2_a may be formed to have a thickness T2a smaller than the thickness T1a of the first color filter CF1_a, and therefore, the optical paths of light passing through the first color filter CF1_a and the second color filter CF2_a may have substantially the same length. Similarly, the third color filter CF3_a and the fourth color filter CF4_a may be formed to have thicknesses T3a and T4a smaller than the thickness T1a of the first color filter CF1_a, respectively, in which case the optical paths of light passing through the first color filter CF1_a, the third color filter CF3_a, and the fourth color filter CF4_a may have substantially the same length. Therefore, a channel difference problem that may occur in an image sensor may be prevented.

[0104] Similar to the above-mentioned first edge filter group CFG_a, the first to fourth color filters (CF1_b, CF2_b, CF3_b and CF4_b / CF1_c, CF2_c, CF3_c and CF4_c / CF1_d, CF2_d, CF3_d and CF4_d) can be set in the second to fourth edge filter groups CFG_b, CFG_c and CFG_d, and two color filters in the first to fourth color filters (CF1_b, CF2_b, CF3_b and CF4_b / CF1_c, CF2_c, CF3_c and CF4_c / CF1_d, CF2_d, CF3_d and CF4_d) can have different thicknesses from each other.

[0105] Next, the thickness difference of the first to fourth color filters (CF1a, CF2_a, CF3_a and CF4_a / CF1_b, CF2_b, CF3_b and CF4_b / CF1_c, CF2_c, CF3_c and CF4_c / CF1_d, CF2_d, CF3_d and CF4_d) between the edge color filter group ECFG will be described below.

[0106] The first edge color filter group CFG_a and the second edge color filter group CFG_b may be disposed to face each other in a diagonal direction. Here, the second edge color filter group CFG_b may be disposed at a position greater than the first edge color filter group CFG_a. Figure 3 Near the edge of the pixel array area R1.

[0107] The first color filter CF1_b and the second color filter CF2_b of the second edge color filter group CFG_b may be placed farther away than the first color filter CF1_a and the second color filter CF2_a of the first edge color filter group CFG_a. Figure 4 In other words, compared with the first color filter CF1_a and the second color filter CF2_a of the first edge color filter group CFG_a, the first color filter CF1_b and the second color filter CF2_b of the second edge color filter group CFG_b may be arranged at Figure 3 Near the edge of the pixel array area R1. Figure 3 The center of the pixel array area R1 is moved to the edge of the pixel array area R1, and the incident angle of the incident light can further deviate from the right angle. Therefore, the above channel difference problem may occur when the Figure 3 The problem occurs more seriously in the second to fourth edge color filter groups CFG_b, CFG_c, and CFG_d near the edge of the pixel array region R1.

[0108] According to an embodiment, the second color filter CF2_b of the second edge color filter group CFG_b may be formed to have a thickness T2b that is smaller than the thickness T1b of the first color filter CF1_b of the second edge color filter group CFG_b, in which case the channel difference problem in the color filter group may be prevented or suppressed. In addition, the thickness T2b of the second color filter CF2_b of the second edge color filter group CFG_b may be smaller than the thickness T2a of the second color filter CF2_a of the first edge color filter group CFG_a. In other words, the first color filter and the second color filter of the second edge color filter group CFG_b may be formed so that the difference between their thicknesses T1b and T2b is greater than the difference between the thickness T1a of the first color filter and the thickness T2a of the second color filter of the first edge color filter group CFG_a. As an example, the first color filters CF1_a, CF1_b, CF1_c, and CF1_d of the edge color filter group ECFG may be formed to have substantially the same thickness, and the thicknesses of the second color filters CF2_a, CF2_b, CF2_c, and CF2_d of the edge color filter group ECFG may increase as the thickness increases. Figure 3 However, in an embodiment, at least two color filters among the first color filters CF1_a, CF1_b, CF1_c, and CF1_d of the edge color filter group ECFG may have different thicknesses from each other.

[0109] The first color filter CF1_c and the third color filter CF3_c of the third edge color filter group CFG_c may be placed farther away than the first color filter CF1_a and the third color filter CF3_a of the first edge color filter group CFG_a. Figure 4 Similarly, the thickness T3c of the third color filter CF3_c of the third edge color filter group CFG_c may not only be smaller than the thickness T1c of the first color filter CF1_c of the third edge color filter group CFG_c, but may also be smaller than the thickness T3a of the third color filter CF3_a of the first edge color filter group CFG_a, and thus the channel difference problem in the third edge color filter group CFG_c may be prevented.

[0110] In addition, the first color filter CF1_d and the fourth color filter CF4_d of the fourth edge color filter group CFG_d may be placed farther away than the first color filter CF1_a and the fourth color filter CF4_d of the first edge color filter group CFG_a. Figure 4Similarly, the thickness T4d of the fourth color filter CF4_d of the fourth edge color filter group CFG_d may be not only smaller than the thickness T1d of the first color filter CF1_d of the fourth edge color filter group CFG_d, but also smaller than the thickness T4a of the fourth color filter CF4_a of the first edge color filter group CFG_a, thereby preventing the channel difference problem in the fourth edge color filter group CFG_d. Below, in order to provide a concise description, the same features as the first edge color filter group CFG_a and the second edge color filter group CFG_b will be omitted.

[0111] Reference Figures 7 to 8C , the central color filter group CCFG may include a plurality of color filter groups CFG_e and CFG_f disposed adjacent to each other. In this specification, for ease of description, the first central color filter group CFG_e, which is one of the central color filter groups CCFG, will be described as a representative example of the central color filter group CCFG.

[0112] The first central color filter group CFG_e may include first to fourth color filters CF1_e, CF2_e, CF3_e, and CF4_e. In the first central color filter group CFG_e, thicknesses T1e, T2e, T3e, and T4e of the first to fourth color filters CF1_e, CF2_e, CF3_e, and CF4_e may be substantially equal to each other.

[0113] In the first central color filter group CFG_e, most of the light may be incident perpendicular to the first surface 100a of the semiconductor substrate 100. That is, most of the light passing through the color filters CF1_e, CF2_e, CF3_e, and CF4_e in the first central color filter group CFG_e may be incident at right angles, and there may be no difference in the angle of incidence between them. Therefore, even when the color filters CF1_e, CF2_e, CF3_e, and CF4_e in the first central color filter group CFG_e have the same thickness, the channel difference problem does not occur.

[0114] Figures 11 to 13 is a cross-sectional view showing an image sensor according to some embodiments. In the following description, for the sake of brevity, the previous reference FIG. 5A to FIG. 10 Described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0115] Reference Fig.11, the pixel isolation structure DTI may have an upper width at a level near the second surface 100b of the semiconductor substrate 100. The pixel isolation structure DTI may have a lower width at a level near the first surface 100a of the semiconductor substrate 100. The upper width may be smaller than the lower width. For example, the width of the pixel isolation structure DTI may gradually decrease as it moves from the first surface 100a of the semiconductor substrate 100 toward the second surface 100b.

[0116] Reference Fig.12 , the pixel isolation structure DTI may have an upper width at a level near the second surface 100b of the semiconductor substrate 100. The pixel isolation structure DTI may have a lower width at a level near the first surface 100a of the semiconductor substrate 100. The pixel isolation structure DTI may have an intermediate width in the semiconductor substrate 100. Each of the upper width and the lower width may be greater than the intermediate width. The width of the pixel isolation structure DTI may decrease and then increase as it proceeds from the second surface 100b of the semiconductor substrate 100 to the first surface 100a. For example, the width of the pixel isolation structure DTI may have a maximum value near the first surface 100a and the second surface 100b of the semiconductor substrate 100, and may have a minimum value in the semiconductor substrate 100. The pixel isolation structure DTI may include a first pixel isolation structure DTI1 and a second pixel isolation structure DTI2.

[0117] Reference Fig.13 Each pixel region PR may include a first photoelectric conversion region PD1 and a second photoelectric conversion region PD2. The first photoelectric conversion region PD1 and the second photoelectric conversion region PD2 may be impurity regions doped with impurities having a conductivity type different from that of the first conductivity type semiconductor substrate 100 (eg, a second conductivity type or n-type).

[0118] The pixel isolation structure DTI may be disposed between the first photoelectric conversion region PD1 and the second photoelectric conversion region PD2. The pixel isolation structure DTI may prevent a crosstalk problem from occurring between the first photoelectric conversion region PD1 and the second photoelectric conversion region PD2. For example, the pixel isolation structure DTI may prevent light incident into the first photoelectric conversion region PD1 from entering the second photoelectric conversion region PD2.

[0119] Fig.14 is a plan view showing an image sensor according to an embodiment. Fig.15 It is along Fig.14 A cross-sectional view of an image sensor according to an embodiment is shown taken along line AA′. Fig.16 is a plan view showing an image sensor according to an embodiment. Fig.17 It is along Fig.16The sectional view of the image sensor according to the embodiment is shown by taking the line AA' of FIG. FIG. 5A to FIG. 10 Described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0120] Reference Fig.14 and Fig.15 , each color filter group CFG' may include nine color filters (including CF1', CF2', and CF3') arranged in 3 rows and 3 columns. For ease of description, the color filters arranged in the diagonal direction in the color filter group CFG' will be referred to as first to third color filters CF1', CF2', and CF3'.

[0121] The incident angle of light passing through the first color filter CF1', the incident angle of light passing through the second color filter CF2', and the incident angle of light passing through the third color filter CF3' may be different from each other. Here, the third color filter CF3', the second color filter CF2', and the first color filter CF1' may be close to each other in the order listed. Figure 4 Therefore, the average incident angle of light incident into the color filter may decrease as moving from the third color filter CF3' toward the first color filter CF1'.

[0122] According to an embodiment, the thickness of the first to third color filters CF1', CF2', and CF3' may decrease as they proceed from the first color filter CF1' to the third color filter CF3'. For example, the thickness T3' of the third color filter CF3' may be less than the thickness T2' of the second color filter CF2', and the thickness T2' of the second color filter CF2' may be less than the thickness T1' of the first color filter CF1'. Therefore, the lengths of the optical paths of the light passing through the first to third color filters CF1', CF2', and CF3' may be substantially equal to each other. As a result, a channel difference problem that may occur in an image sensor may be prevented.

[0123] Reference Fig.16 and Fig.17 , each color filter group CFG" may include sixteen color filters arranged in 4 rows and 4 columns. For ease of description, the color filters arranged along the diagonal direction in the color filter group CFG" will be referred to as the first to fourth color filters CF1", CF2", CF3" and CF4".

[0124] In the color filter group CFG", the incident angle of light passing through the first color filter CF1", the incident angle of light passing through the second color filter CF2", the incident angle of light passing through the third color filter CF3", and the incident angle of light passing through the fourth color filter CF4" may be different from each other. Here, the fourth color filter CF4", the third color filter CF3", the second color filter CF2", and the first color filter CF1" may be close to each other in the order listed. Figure 4 Therefore, the average value of the incident angle of light incident into the first to fourth color filters CF1", CF2", CF3" and CF4" can gradually decrease in the following order: fourth color filter CF4", third color filter CF3", second color filter CF2" and first color filter CF1".

[0125] According to an embodiment, the thicknesses of the first to fourth color filters CF1", CF2", CF3", and CF4" may decrease as proceeding from the first color filter CF1" to the fourth color filter CF4". For example, the thickness T4" of the fourth color filter CF4" may be less than the thickness T3" of the third color filter CF3", the thickness T3" of the third color filter CF3" may be less than the thickness T2" of the second color filter CF2", and the thickness T2" of the second color filter CF2" may be less than the thickness T1" of the first color filter CF1". Therefore, the lengths of the optical paths of light passing through the first to fourth color filters CF1", CF2", CF3", and CF4" may be substantially equal to each other. As a result, channel difference problems that may occur in image sensors may be prevented.

[0126] Fig.18A and Fig.18B is a cross-sectional diagram, where each diagram is along Figure 3 AA′ is cut out to illustrate the image sensor according to the embodiment.

[0127] Reference Figure 3 , Fig.18A and Fig.18B , the image sensor may include a sensor chip S1 and a logic chip S2. The sensor chip S1 may include a pixel array region R1 and a pad region R2.

[0128] A plurality of conductive pads CP for inputting or outputting control signals and photoelectric signals may be provided in the pad region R2. When viewed in a plan view, the pad region R2 may be provided to surround the pixel array region R1, in which case the image sensor may be easily connected to an external device. The conductive pads CP may be used to transmit an electrical signal generated in the unit pixel P to an external device.

[0129] In the light receiving area AR, the sensor chip S1 may be configured to have the same technical features as the above-mentioned image sensor. That is, as described above, when viewed in a vertical cross section, the sensor chip S1 may include a pixel circuit layer 20, an optically transparent layer 30, and a photoelectric conversion layer 10 therebetween. As described above, the photoelectric conversion layer 10 of the sensor chip S1 may include a semiconductor substrate 100, a pixel isolation structure DTI defining a pixel area, and a photoelectric conversion region PD provided in the pixel area. The pixel isolation structure DTI may have substantially the same structure in the light receiving area AR and the light blocking area OB.

[0130] In the light blocking region OB, the optically transparent layer 30 may include a light blocking pattern OBP, a back contact plug PLG, a contact pattern CT, an organic layer 350 , and a passivation layer 360 .

[0131] A portion of the pixel isolation structure DTI may be connected to the back contact plug PLG in the light blocking area OB.

[0132] In detail, in the light blocking region OB, the semiconductor pattern 113 may be connected to the back contact plug PLG. A negative bias may be applied to the semiconductor pattern 113 through the contact pattern CT and the back contact plug PLG. In this case, dark current that may be generated at the interface between the pixel isolation structure DTI and the semiconductor substrate 100 may be reduced.

[0133] The back contact plug PLG may have a width greater than that of the pixel isolation structure DTI. The back contact plug PLG may be formed of or include at least one of a metal material and a metal nitride material. For example, the back contact plug PLG may be formed of or include at least one of titanium and titanium nitride.

[0134] The contact pattern CT may be buried in the contact hole in which the back contact plug PLG is formed. The contact pattern CT may include a material different from that of the back contact plug PLG. For example, the contact pattern CT may be formed of or include aluminum (Al).

[0135] The contact pattern CT may be electrically connected to the semiconductor pattern 113 of the pixel isolation structure DTI. The contact pattern CT may be used to apply a negative bias voltage to the semiconductor pattern 113 of the pixel isolation structure DTI, in which case the negative bias voltage may be supplied from the light blocking region OB to the light receiving region AR.

[0136] In the light blocking region OB, the light blocking pattern OBP may extend continuously from the back contact plug PLG and may be disposed on the top surface of the planarization insulating layer 310. In other words, the light blocking pattern OBP may be formed of the same material as the back contact plug PLG, or include the same material as the back contact plug PLG. The light blocking pattern OBP may be formed of at least one of a metal material and a metal nitride material, or include at least one of a metal material and a metal nitride material. For example, the light blocking pattern OBP may be formed of at least one of titanium and titanium nitride, or include at least one of titanium and titanium nitride. The light blocking pattern OBP may not extend to the light receiving region AR of the pixel array region R1.

[0137] The light blocking pattern OBP may prevent light from being incident on the photoelectric conversion region PD provided in the light blocking region OB. The photoelectric conversion region PD in the reference pixel region of the light blocking region OB may be configured to output a noise signal instead of a photoelectric signal. The noise signal may be generated by electrons generated by heat or dark current.

[0138] In the light blocking region OB, an organic layer 350 and a passivation layer 360 may be provided on the light blocking pattern OBP. The organic layer 350 may be formed of or include the same material as the microlens 340.

[0139] In the light blocking region OB, a first penetration conductive pattern 511 may be provided to penetrate the semiconductor substrate 100, and the first penetration conductive pattern 511 may be electrically connected to the metal line 223 of the pixel circuit layer 20 and the interconnection structure 1111 of the logic chip S2. The first penetration conductive pattern 511 may have a first bottom surface and a second bottom surface located at different levels. A first gap filling pattern 521 may be provided in the first penetration conductive pattern 511. The first gap filling pattern 521 may be formed of or include at least one low refractive material, and may have an insulating property.

[0140] In the pad region R2, a conductive pad CP may be provided on the first surface 100a of the semiconductor substrate 100. The conductive pad CP may be buried in the semiconductor substrate 100 and near the first surface 100a. In an embodiment, the conductive pad CP may be provided in a pad groove formed in the first surface 100a of the semiconductor substrate 100 and located in the pad region R2. The conductive pad CP may be formed of at least one of a metal material (e.g., aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof), or include at least one of the metal materials. In the mounting process of the image sensor, a bonding wire may be bonded to the conductive pad CP. The conductive pad CP may be electrically connected to an external device by a bonding wire.

[0141] In the pad region R2, a second penetration conductive pattern 513 may be provided to penetrate the semiconductor substrate 100, and the second penetration conductive pattern 513 may be electrically connected to the interconnect structure 1111 of the logic chip S2. The second penetration conductive pattern 513 may extend to an area on the first surface 100a of the semiconductor substrate 100, and may be electrically connected to the conductive pad CP. A portion of the second penetration conductive pattern 513 may cover the bottom surface and the side surface of the conductive pad CP. A second gap filling pattern 523 may be provided in the second penetration conductive pattern 513. The second gap filling pattern 523 may be formed of or include at least one low-refractive material, and may have insulating properties. In the pad region R2, a pixel isolation structure DTI may be provided around the second penetration conductive pattern 513.

[0142] The logic chip S2 may include a logic semiconductor substrate 1000, a logic circuit TR, an interconnect structure 1111 connected to the logic circuit, and a logic interlayer insulating layer 1100. The uppermost layer of the logic interlayer insulating layer 1100 may be bonded to the pixel circuit layer 20 of the sensor chip S1. The logic chip S2 may be electrically connected to the sensor chip S1 through the first through conductive pattern 511 and the second through conductive pattern 513.

[0143] In an embodiment, the sensor chip S1 and the logic chip S2 are illustrated as being electrically connected to each other through the first and second penetrating conductive patterns 511 and 513 , but embodiments of the present disclosure are not limited to this example.

[0144] Reference Fig.18B , can be omitted Fig.18A The first and second penetrating conductive patterns 511 and 513 of the sensor chip S1 and the logic chip S2 may be directly bonded to each other to electrically connect the sensor chip S1 and the logic chip S2 to each other.

[0145] In more detail, the sensor chip S1 of the image sensor may include a first bonding pad BP1 provided in the uppermost metal layer of the pixel circuit layer 20, and the logic chip S2 may include a second bonding pad BP2 provided in the uppermost metal layer of the interconnect structure 1111. The first bonding pad BP1 and the second bonding pad BP2 may be formed of, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN), or include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0146] The first bonding pad BP1 of the sensor chip S1 and the second bonding pad BP2 of the logic chip S2 can be electrically and directly connected to each other by a hybrid bonding method. Here, the hybrid bonding method can refer to a method of bonding two materials of the same kind at an interface between the two materials (for example, by a fusion process). For example, in the case where the first bonding pad BP1 and the second bonding pad BP2 are formed of copper (Cu), they can be physically and electrically connected to each other in a Cu-Cu bonding manner. In addition, the surfaces of the insulating layers of the sensor chip S1 and the logic chip S2 can be bonded to each other in a dielectric-dielectric bonding manner.

[0147] According to embodiments, optical properties of an image sensor may be improved.

[0148] While certain example embodiments of the present disclosure have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A semiconductor substrate including a pixel array region, the pixel array region including a central pixel region and an edge pixel region surrounding the central pixel region in a plan view; color filter groups on the pixel array area, each of the color filter groups including color filters arranged in the same number of rows and columns; as well as micro lenses respectively covering the color filter groups, The color filter group includes a central color filter group on the central pixel area and an edge color filter group on the edge pixel area, and At least two of the color filters in each of the edge color filter groups have different thicknesses from each other.

2. The image sensor according to claim 1, wherein: Each of the edge color filter groups includes a first color filter, a second color filter, a third color filter, and a fourth color filter, and Wherein, the thickness of the first color filter is greater than the thickness of the second color filter.

3. The image sensor according to claim 2, wherein: The second color filter is farther away from the central pixel area than the first color filter.

4. The image sensor according to claim 2, wherein: The second color filter, the third color filter and the fourth color filter are further away from the central pixel area than the first color filter, wherein the second color filter faces the first color filter in a diagonal direction, and Wherein, the thickness of the third color filter and the thickness of the fourth color filter are smaller than the thickness of the first color filter.

5. The image sensor according to claim 2, wherein: The edge color filter group includes a first edge color filter group and a second edge color filter group, the second edge color filter group is farther away from the central pixel area than the first edge color filter group, and The thickness of the second color filter of the second edge color filter group is smaller than the thickness of the second color filter of the first edge color filter group.

6. The image sensor according to claim 5, wherein: A thickness of the first color filter of the second edge color filter set is substantially the same as a thickness of the first color filter of the first edge color filter set.

7. The image sensor according to claim 1, wherein: In the central color filter group, the color filters have substantially the same thickness.

8. The image sensor according to claim 1, wherein: The microlens includes a first microlens covering the edge color filter group and a second microlens covering the center color filter group, and Wherein, when viewed in a plan view, the center of the first microlens is offset from the corresponding center of the edge color filter group. 9 . The image sensor according to claim 1 , further comprising a pixel isolation structure in the semiconductor substrate, the pixel isolation structure defining a plurality of pixel regions in the pixel array region.

10. The image sensor according to claim 9, wherein: The semiconductor substrate includes a first surface and a second surface opposite to each other, wherein the color filter group is on the first surface, and Wherein, the width of the pixel isolation structure increases from the first surface toward the second surface.

11. The image sensor according to claim 9, wherein: The semiconductor substrate includes a first surface and a second surface opposite to each other, wherein the color filter group is on the first surface, and Wherein, the width of the pixel isolation structure decreases from the first surface toward the second surface.

12. The image sensor according to claim 9, wherein: The semiconductor substrate includes a first surface and a second surface opposite to each other, wherein the color filter group is on the first surface, and The width of the pixel isolation structure has a minimum value between the first surface and the second surface.

13. An image sensor, comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate comprising a pixel array region, a first surface, and a second surface opposite to the first surface; a photoelectric conversion region in the pixel array region, the photoelectric conversion region including impurities of a second conductivity type; a color filter group covering at least a portion of the pixel array area, each of the color filter groups comprising a first color filter, a second color filter, a third color filter, and a fourth color filter arranged in two rows and two columns; as well as micro lenses respectively covering the color filter groups, The pixel array area includes a central pixel area and an edge pixel area surrounding the central pixel area in a plan view. The color filter group includes a central color filter group on the central pixel area and an edge color filter group on the edge pixel area, and Wherein, in each of the edge color filter groups, the thickness of the first color filter is greater than the thickness of the second color filter.

14. The image sensor according to claim 13, wherein: In each of the edge color filter groups, the second color filter is farther away from the central pixel region than the first color filter.

15. The image sensor according to claim 13, wherein: The edge color filter group includes a first edge color filter group and a second edge color filter group, the second edge color filter group is farther away from the central pixel area than the first edge color filter group, and The thickness of the second color filter of the second edge color filter group is smaller than the thickness of the second color filter of the first edge color filter group. 16 . The image sensor of claim 15 , wherein a thickness of the first color filter of the second edge color filter set is substantially the same as a thickness of the first color filter of the first edge color filter set. 17 . The image sensor of claim 13 , further comprising a light blocking pattern separating the color filter groups from each other.

18. The image sensor according to claim 13, wherein: In each of the color filter groups, the first color filter, the third color filter, and the fourth color filter have the same color. 19 . The image sensor according to claim 13 , further comprising a pixel isolation structure in the semiconductor substrate and surrounding the photoelectric conversion region in a plan view.

20. An image sensor, comprising: A semiconductor substrate including a light receiving region, a light blocking region, a pad region, a first surface, and a second surface opposite to the first surface; a pixel isolation structure, wherein the pixel isolation structure defines a pixel area in the light receiving area and the light blocking area of ​​the semiconductor substrate; a photoelectric conversion region in the light receiving region and the light blocking region of the semiconductor substrate; color filter groups on the first surface, each of the color filter groups comprising a first color filter, a second color filter, a third color filter, and a fourth color filter arranged in two rows and two columns; a transfer gate electrode on the second surface; a pixel circuit layer on the second surface; as well as micro lenses respectively covering the color filter groups, The light receiving area includes a central pixel area and an edge pixel area surrounding the central pixel area in a plan view. The color filter group includes a central color filter group on the central pixel area and an edge color filter group on the edge pixel area, and Wherein, in each of the edge color filter groups, the thickness of the first color filter is greater than the thickness of the second color filter.

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