Shallow trench isolation structure for image sensor, manufacturing method of shallow trench isolation structure and image sensor

Abstract

The invention provides a shallow trench isolation structure for an image sensor, a manufacturing method of the shallow trench isolation structure and the image sensor. The shallow trench isolation structure for the image sensor comprises a substrate; the shallow trench is positioned in the substrate; the first high-K isolation layer is located on the side wall and the bottom of the shallow trench; and the filling dielectric layer is located on the first high-K isolation layer and fills the shallow trench. According to the invention, the high-K isolation layer is formed in the shallow trench isolation structure of the substrate, positive charges are induced on the surface of the substrate, and external redundant charged particles are prevented from entering a PD region, so that dark current and white pixels caused by silicon damage in the substrate are inhibited, and the imaging quality of the image sensor is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shallow trench isolation structure for an image sensor, a manufacturing method thereof, and an image sensor. Background Art

[0002] In the CIS (CMOS Image Sensor) process, STI (Shallow Trench Isolation) is usually used to isolate different devices to prevent adverse effects caused by mutual connection. STI silicon etching can cause damage to the silicon surface of the pixel area, forming lattice defects and interface states. Although subsequent processes can make up for the defects caused by silicon etching, the interface states cannot be completely eliminated. Lattice defects and dangling bonds on the silicon etching surface may capture metal ions or electrons in subsequent process steps. These charged particles will cause dark current in the image sensor, and in severe cases, cause white pixels. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] In view of the existing problems, the present application provides a shallow trench isolation structure for an image sensor, including: substrate; a shallow trench in the substrate; a first high-K isolation layer located on the sidewalls and the bottom of the shallow trench; A filling dielectric layer is located on the first high-K isolation layer and fills the shallow trench.

[0005] Exemplarily, the shallow trench isolation structure further includes a second isolation layer located between the first high-K isolation layer and the substrate.

[0006] Exemplarily, the second isolation layer includes silicon oxide.

[0007] Exemplarily, the first high-K isolation layer includes at least one of Al2O3, HfO2, Ta2O5, ZrO2, and TiO2.

[0008] Another aspect of the present application provides a method for manufacturing a shallow trench isolation structure for an image sensor, comprising: providing a substrate; forming a shallow trench in the substrate; forming a first high-K isolation layer on the substrate and on the sidewalls and bottom of the shallow trench; forming a filling dielectric layer on the first high-K isolation layer, wherein the filling dielectric layer fills the shallow trench; The filling dielectric layer and the first high-K isolation layer on the substrate are removed by planarization.

[0009] Exemplarily, before forming the first high-K isolation layer on the substrate and on the sidewalls and bottom of the shallow trench, the method further includes forming a second isolation layer on the substrate and on the sidewalls and bottom of the shallow trench.

[0010] Exemplarily, the second isolation layer includes silicon oxide.

[0011] Exemplarily, the second isolation layer is formed by at least one of ALD, PECVD, LPCVD and APCVD.

[0012] Exemplarily, the first high-K isolation layer includes at least one of Al2O3, HfO2, Ta2O5, ZrO2, and TiO2.

[0013] According to another aspect of the embodiments of the present application, an image sensor is provided, comprising the shallow trench isolation structure as described above.

[0014] According to the shallow trench isolation structure for image sensors and its manufacturing method, and image sensor provided by the present application, a high-K isolation layer is formed in the shallow trench isolation structure of the substrate, positive charges are induced on the surface of the substrate, and external excess charged particles are blocked from entering the PD region (Photo diode, photoelectric conversion region), thereby suppressing dark current and white pixels caused by silicon damage in the substrate, so as to improve the imaging quality of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the principles of the present application. In the drawings: Figure 1 A schematic flow chart showing a method for manufacturing a shallow trench isolation structure for an image sensor according to a specific embodiment of the present application; FIG. 2A to FIG. 2I A cross-sectional schematic diagram of a shallow trench isolation structure obtained by sequentially implementing each step of a method for manufacturing a shallow trench isolation structure for an image sensor according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0016] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0017] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0018] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part.

[0019] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0020] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0021] In CIS, there are hundreds or thousands of PDs. When PDs receive light, they will generate electronic transitions and convert optical signals into electrical signals. Image sensors are mainly divided into backside illumination CMOS imagesensor (BSI CIS) and front side illumination CMOS imager sensor (FSI CIS). BSI CIS arranges the photosensitive area containing PDs on the circuit to reduce light loss, such as metal wire reflection and dielectric layer absorption, so as to significantly increase the photoelectric conversion effect and significantly improve the imaging quality. In the manufacturing process of CIS, STI structure is usually used to isolate different devices to prevent adverse effects caused by mutual connection. The silicon etching of STI will cause damage to the silicon surface of the pixel area, form lattice defects and interface states, and easily produce dangling bonds. Although the subsequent process can make up for the defects caused by silicon etching, the interface state cannot be completely eliminated. The lattice defects and dangling bonds on the silicon etching surface may capture metal ions or electrons in the subsequent process. These charged particles will cause dark current in the image sensor, and in severe cases will cause white pixels, thereby reducing the imaging quality of the image sensor.

[0022] Therefore, in view of the existence of the aforementioned technical problems, the present application embodiment proposes a method for manufacturing a shallow trench isolation structure for an image sensor, such as Figure 1 As shown, it mainly includes the following steps: Step S110: providing a substrate; Step S120: forming a shallow trench in the substrate; Step S130: forming a first high-K isolation layer on the substrate and on the sidewalls and bottom of the shallow trench; Step S140: forming a filling dielectric layer on the first high-K isolation layer, wherein the filling dielectric layer fills the shallow trench; Step S150: planarizing and removing the filling dielectric layer and the first high-K isolation layer on the substrate.

[0023] The manufacturing method of the shallow trench isolation structure for an image sensor provided in an embodiment of the present application forms a high-K isolation layer in the shallow trench isolation structure of the substrate, induces positive charges on the surface of the substrate, and prevents excess external charged particles from entering the PD area, thereby suppressing dark current and white pixels caused by silicon damage in the substrate, so as to improve the imaging quality of the image sensor.

[0024] Embodiment 1

[0025] Below, reference FIG. 2A to FIG. 2I The manufacturing method of the shallow trench isolation structure for the image sensor of the embodiment of the present application is described in detail, wherein: FIG. 2A to FIG. 2I A cross-sectional schematic diagram of a shallow trench isolation structure for an image sensor obtained by sequentially implementing each step of a method for manufacturing a shallow trench isolation structure for an image sensor according to an embodiment of the present application is shown.

[0026] First, step S110 is performed to provide a substrate. Figure 2A As shown, the substrate 200 can be used as a pixel wafer to form a pixel array to receive incident light and convert it into an electrical signal. The material of the substrate 200 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI).

[0027] Then, if Figure 2B As shown, a hard mask layer 201 is formed on the provided substrate 200 by deposition, and the material of the hard mask layer 201 includes but is not limited to insulating materials such as silicon nitride. The hard mask layer 201 can be formed by various deposition methods commonly used in the art, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). Exemplarily, a liner layer (not shown) is also formed on the substrate 200 before the hard mask layer 201 is formed. The liner layer includes silicon oxide, which is generally used to reduce the stress between the hard mask layer 201 and the substrate 200. The liner layer can be formed by thermal oxidation.

[0028] Next, step 120 is performed to form a shallow trench in the substrate. Figure 2CAs shown, a patterned mask layer 202 is formed on the hard mask layer 201, and the patterned mask layer can be a photoresist layer. Then, the hard mask layer 201 and the substrate 200 are etched using the patterned mask layer 202 as a mask to form a Figure 2D Shallow trench 203 is shown. The residual photoresist layer can be removed by conventional wet cleaning and ashing processes.

[0029] Next, step 130 is performed to form a first high-K isolation layer on the substrate and on the sidewalls and bottom of the shallow trench. First, optionally, as Figure 2E As shown, a second isolation layer 204 is formed on the provided substrate 200 and on the sidewalls and bottom of the shallow trench 203 by deposition. Exemplarily, the second isolation layer 204 is formed by at least one of atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) and atmospheric pressure chemical vapor deposition (APCVD). Exemplarily, the material of the second isolation layer 204 includes but is not limited to silicon oxide. Then, as Figure 2F As shown, a first high-K isolation layer 205 is formed on the second isolation layer 204. Exemplarily, various deposition methods commonly used in the art can be used to form the first high-K isolation layer 205, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). In some examples, the first high-K isolation layer includes at least one of Al2O3, HfO2, Ta2O5, ZrO2 and TiO2. It should be noted that the second isolation layer is optional in the present application, and is not necessary. The present application can directly form the first high-K isolation layer without forming the second isolation layer.

[0030] Next, step 140 is performed to form a filling dielectric layer on the first high-K isolation layer, wherein the filling dielectric layer fills the shallow trench. Figure 2G As shown, a filling dielectric layer 206 is deposited on the first high-K isolation layer 205 to fill the shallow trench 203 to form a shallow trench isolation structure. Exemplarily, the filling dielectric layer 206 includes but is not limited to at least one of materials with good insulating properties such as silicon dioxide, fluorosilicate glass, undoped silicate glass and tetraethyl orthosilicate.

[0031] Next, step 150 is performed to planarize and remove the filling dielectric layer and the first high-K isolation layer on the substrate.

[0032] like Figure 2HAs shown, the filling dielectric layer 206 on the substrate 200 is planarized, stopping at the hard mask layer 201. Exemplarily, non-limiting examples of the planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method. Fig.2I As shown, the remaining hard mask layer 201 is removed to form Fig.2I The shallow trench isolation structure shown includes a filling dielectric layer 206, a first high-K isolation layer 205 and a second isolation layer 204. Exemplarily, the residual hard mask layer 201 may be removed by wet etching.

[0033] At this point, the process steps implemented in the manufacturing method of the shallow trench isolation structure for the image sensor according to one embodiment of the present application have been completed. It can be understood that the manufacturing method of the shallow trench isolation structure for the image sensor of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0034] The manufacturing method of the shallow trench isolation structure for an image sensor provided in an embodiment of the present application forms a high-K isolation layer in the shallow trench isolation structure of the substrate, induces positive charges on the surface of the substrate, and prevents excess external charged particles from entering the PD area, thereby suppressing dark current and white pixels caused by silicon damage in the substrate, so as to improve the imaging quality of the image sensor.

[0035] Embodiment 2

[0036] The present application also provides a shallow trench isolation structure for an image sensor, and the shallow trench isolation structure for an image sensor can be prepared by the method in the aforementioned first embodiment.

[0037] Below, reference Fig.2I The shallow trench isolation structure for the image sensor of the present application is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.

[0038] Specifically, Fig.2I As shown, the shallow trench isolation structure for an image sensor according to an embodiment of the present application includes: a substrate 200; a shallow trench in the substrate 200, a first high-K isolation layer 205 covering the sidewall and bottom of the shallow trench, and a filling dielectric layer 206 filling the shallow trench.

[0039] For example, continue as Fig.2I As shown, a second isolation layer 204 is further formed between the first high-K isolation layer 205 and the substrate 200. In some examples, the second isolation layer 204 includes, but is not limited to, silicon oxide.

[0040] Embodiment 3

[0041] The present application also provides an image sensor, which includes the above-mentioned shallow trench isolation structure.

[0042] The shallow trench isolation structure for an image sensor and its manufacturing method, as well as the image sensor provided in the embodiments of the present application, form a high-K isolation layer in the shallow trench isolation structure of the substrate, induce positive charges on the surface of the substrate, and prevent excess external charged particles from entering the PD area, thereby suppressing dark current and white pixels caused by silicon damage in the substrate, so as to improve the imaging quality of the image sensor.

[0043] The present application has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present application is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present application, and these variations and modifications all fall within the scope of protection claimed by the present application. The scope of protection of the present application is defined by the attached claims and their equivalents.

Claims

1. A shallow trench isolation structure for an image sensor, characterized in that: include: substrate; a shallow trench in the substrate; a first high-K isolation layer located on the sidewalls and the bottom of the shallow trench; A filling dielectric layer is located on the first high-K isolation layer and fills the shallow trench.

2. The shallow trench isolation structure according to claim 1, wherein: The invention also includes a second isolation layer located between the first high-K isolation layer and the substrate.

3. The shallow trench isolation structure according to claim 2, characterized in that: The second isolation layer includes silicon oxide.

4. The shallow trench isolation structure according to claim 1, wherein: The first high-K isolation layer includes at least one of Al2O3, HfO2, Ta2O5, ZrO2 and TiO2.

5. A method for manufacturing a shallow trench isolation structure for an image sensor, characterized in that: include: providing a substrate; forming a shallow trench in the substrate; forming a first high-K isolation layer on the substrate and on the sidewalls and bottom of the shallow trench; forming a filling dielectric layer on the first high-K isolation layer, wherein the filling dielectric layer fills the shallow trench; The filling dielectric layer and the first high-K isolation layer on the substrate are removed by planarization.

6. The method for manufacturing a shallow trench isolation structure according to claim 5, wherein: Before forming the first high-K isolation layer on the substrate and on the sidewalls and bottom of the shallow trench, the method further includes forming a second isolation layer on the substrate and on the sidewalls and bottom of the shallow trench.

7. The method for manufacturing a shallow trench isolation structure according to claim 6, wherein: The second isolation layer includes silicon oxide.

8. The method for manufacturing a shallow trench isolation structure according to claim 7, wherein: The second isolation layer is formed by at least one method selected from the group consisting of ALD, PECVD, LPCVD and APCVD.

9. The method for manufacturing a shallow trench isolation structure according to claim 5, characterized in that: The first high-K isolation layer includes at least one of Al2O3, HfO2, Ta2O5, ZrO2 and TiO2.

10. An image sensor, characterized in that: It comprises the shallow trench isolation structure as claimed in any one of claims 1 to 4.

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