Back contact battery and preparation method thereof

Abstract

The present invention relates to the technical field of solar cells, and provides a back contact cell and a preparation method thereof. By adding a certain proportion of carbon elements into the deposition of a first semiconductor layer and a mask layer, the acid and alkali corrosion resistance of the first semiconductor layer and the mask layer is improved, which is beneficial to prolonging the texturing time. At the same time, by increasing the laser etching depth, the texturing time is prolonged to form a second semiconductor opening area with a recessed velvet structure, and then local polishing is performed to flatten the tip of the tetrahedral structure to form a velvet surface with an inverted frustum-shaped structure in the second semiconductor opening area, which is beneficial to improving the passivation effect and improving the filling factor.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a back contact cell and a preparation method thereof. Background Art

[0002] When preparing the existing back-contact battery, a second semiconductor opening area is formed on the first semiconductor layer on the back of the silicon wafer. The residual mask layer, N-type doped polycrystalline layer and tunneling silicon oxide layer in the second semiconductor opening area are removed by texturing and cleaning, and a velvet surface is formed on the front of the silicon wafer and the surface of the silicon wafer located in the second semiconductor opening area. In the existing back-contact battery preparation process, the second semiconductor opening area is treated by texturing and cleaning, and the treatment time should not be too long, otherwise the first semiconductor layer is easily damaged; but if the texturing and cleaning time is too short, the depth and velvet effect of the P area are not good, which easily leads to a decrease in the passivation effect and a decrease in the fill factor (FF), thereby affecting the battery performance.

[0003] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0004] The object of the present invention is to provide a back contact battery and a preparation method thereof, so as to solve the technical problem of how to ensure the passivation effect while not damaging the first semiconductor layer during texturing and cleaning of the second semiconductor opening area.

[0005] In order to achieve the above objectives, in a first aspect, an embodiment of the present invention provides a back contact battery, comprising:

[0006] A silicon wafer having a front side and a back side;

[0007] A first semiconductor layer is arranged on the back of the silicon wafer, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer sequentially formed on the silicon wafer; the carbon doping concentration in the N-type doped polysilicon layer is 5×10 17 cm -3 -1×10 19 cm -3 ;

[0008] The first semiconductor layer is separated by multiple second semiconductor opening areas, the second semiconductor opening areas and the surface of the first semiconductor layer around the second semiconductor opening areas are covered with a second semiconductor layer, the second semiconductor layer is composed of an intrinsic amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer; a first semiconductor opening area is arranged between adjacent second semiconductor opening areas, the first semiconductor opening area separates the second semiconductor layer; wherein the surface of the silicon wafer located in the second semiconductor area is a velvet surface with an inverted frustum-shaped structure, and the second semiconductor layer fills the velvet surface in the corresponding area to form a frustum-shaped velvet structure.

[0009] Optionally, the height of the suede surface of the inverted frustum-shaped structure is 1-4 μm, and the top surface area of ​​the inverted frustum-shaped structure accounts for 1 / 9-1 / 2 of the bottom surface area.

[0010] Optionally, the width of the formed second semiconductor opening region is 400-600 μm, and the width of the formed first semiconductor opening region is 200-300 μm.

[0011] Optionally, the back contact cell further comprises: an anti-reflection layer; the anti-reflection layer is arranged on one side of the front side of the silicon wafer, and a frustum-shaped velvet structure is formed in the area of ​​the anti-reflection layer corresponding to the front side of the silicon wafer.

[0012] Optionally, the back contact battery also includes: an insulating groove; the insulating groove is located between the adjacent first semiconductor opening area and the second semiconductor opening area; the first semiconductor opening area and the second semiconductor layer are both covered with a transparent conductive film layer, and the insulating groove separates the transparent conductive film layer located in the first semiconductor opening area from the transparent conductive film layer located on the second semiconductor layer.

[0013] Optionally, the width of the insulating groove is 20-100 μm.

[0014] In a second aspect, an embodiment of the present invention further provides a method for preparing a back contact battery, comprising:

[0015] S1. Provide a silicon wafer, and polish both sides of the silicon wafer;

[0016] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer;

[0017] When depositing the N-type doped polysilicon layer, the mass flow rate of silane is 1000-3000sccm, the mass flow rate of phosphine is 1000-2500sccm, the mass flow rate of hydrogen is 7000-9000sccm, the mass flow rate of methane is 200-2000sccm, the pressure is 200-500 Pa, the power is 5-20KW, and the time is 800-1300 seconds; when depositing the mask layer, the mass flow rate of silane is 1000-2000sccm, the mass flow rate of ammonia is 2000-15000sccm, the mass flow rate of methane is 200-2000sccm, the pressure is 200-300 Pa, the power is 3-20KW, and the time is 300-800 seconds; the mass flow ratio of silane to methane in the N-type doped polysilicon layer is 1:(0.1~3), and the carbon doping concentration in the N-type doped polysilicon layer is 5×10 17 cm -3 -1×10 19 cm -3 The mass flow ratio of silane to methane in the mask layer is 1:(0.5-2), and the carbon doping concentration in the mask layer is 1×10 17 cm -3 -9×10 18 cm -3 ;

[0018] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; the etching depth of the second semiconductor opening region is 150-300nm;

[0019] S4, texturing and cleaning the opening areas on the front and back sides of the silicon wafer;

[0020] The texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% to 5%, the mass percentage of the texturing additive is 0.5% to 1%, the texturing time is 8 to 45 minutes, and the texturing temperature is 75° C. to 85° C. After texturing and cleaning, an inverted truncated cone-shaped texturing surface with grooves is formed on the P-type semiconductor region on the back of the silicon wafer, and the maximum depth H of the grooves is 1 to 4 μm;

[0021] After the above-mentioned silicon wafer is cleaned and texturized, the back side of the silicon wafer is single-sided polished by chain cleaning. The solution used for polishing is a mixture of potassium hydroxide or sodium hydroxide and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% to 5%. The polishing time is 5 to 30 minutes, and the texturizing temperature is 50°C to 70°C. The single-sided polishing causes the tip of the inverted frustum-shaped structure of the velvet surface of the P-type semiconductor region on the back side of the silicon wafer to be cut off by 1 / 5 to 1 / 2, forming a velvet effect of an inverted frustum-shaped structure. During the polishing process, the mask layer on the back side of the silicon wafer is also removed by the final cleaning solution.

[0022] S5, forming a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer;

[0023] S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0024] S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region;

[0025] S8, depositing a conductive film layer on the back side of the silicon wafer;

[0026] S9, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove;

[0027] S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0028] Optionally, step S2 specifically includes:

[0029] The thickness of the tunneling silicon oxide layer is 1-2nm, the thickness of the N-type doped polysilicon layer is 70-120nm, and the thickness of the mask layer is 40-90nm; the tunneling silicon oxide layer, the N-type doped polysilicon layer, and the mask layer are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 400-500°C.

[0030] Optionally, step S3 specifically includes:

[0031] The first etching opening is performed by laser or mask etching, the laser is ultraviolet or green laser, the pulse width is less than 10ns, the width of the formed second semiconductor opening area is 400-600μm, and the laser etching depth is 150-300nm.

[0032] Optionally, in step S7, the solution used to remove the mask layer is HF acid solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20° C.-30° C., and the removal time is 60-300 s.

[0033] Optionally, in step S7, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer includes:

[0034] The passivation layer is one or a combination of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; the anti-reflection layer is one or a combination of silicon nitride, aluminum oxide or a silicon oxide layer.

[0035] Optionally, in step S8, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region includes:

[0036] The second etching opening is performed by laser, the laser is ultraviolet or green laser, and the pulse width is less than 10ns; the width W1 of the formed first semiconductor opening region is 200-300 μm.

[0037] Optionally, in step S9, depositing a conductive film layer on the back side of the silicon wafer includes:

[0038] A transparent conductive film layer is deposited on the back of a silicon wafer using physical vapor deposition technology or activated plasma deposition technology. The thickness of the transparent conductive film layer is 40-80nm. The material of the transparent conductive film layer is an indium oxide-based film doped with tin / tungsten / titanium / zinc, or an aluminum / boron-doped zinc oxide-based film.

[0039] Optionally, in step S10, etching an opening on the back side of the silicon wafer for a third time to form an insulating groove includes:

[0040] An opening is etched on the back of the silicon wafer by mask etching or laser, forming an insulating groove between the first semiconductor opening area and the second semiconductor opening area. The width of the insulating groove is 20-100 μm. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 KΩ.

[0041] The embodiments of the present invention have at least the following beneficial effects:

[0042] The present invention adopts the above-mentioned technical scheme, by adding a certain proportion of carbon element into the deposited first semiconductor layer and the mask layer, so that the acid and alkali corrosion resistance of the first semiconductor layer and the mask layer is improved, which is beneficial to prolonging the texturing time; at the same time, by increasing the laser etching depth, the texturing time is extended to form a recessed texturing structure in the second semiconductor opening area, and then local polishing is performed to flatten the tip of the four-sided pyramid structure to form a texturing surface with an inverted cone-shaped structure in the second semiconductor opening area, which is beneficial to improving the passivation effect and improving FF. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of the internal structure of a back contact battery provided by an embodiment of the present invention;

[0045] Figure 2 The embodiment of the present invention provides Figure 1 Schematic diagram of the local method structure of I;

[0046] Figure 3 A schematic flow chart of a method for preparing a back-contact battery provided in an embodiment of the present invention;

[0047] Figure 4 A process structure diagram corresponding to step S1 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0048] Figure 5 A process structure diagram corresponding to step S2 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0049] Figure 6 A process structure diagram corresponding to step S3 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0050] Figure 7 A process structure diagram corresponding to step S4 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0051] Figure 8 A process structure diagram corresponding to step S5 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0052] Fig. 9 A process structure diagram corresponding to step S6 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0053] Fig.10 A process structure diagram corresponding to step S7 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0054] Fig.11 A process structure diagram corresponding to step S8 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0055] Fig.12 A process structure diagram corresponding to step S9 in a method for preparing a back contact battery provided in an embodiment of the present invention;

[0056] Fig.13 This is a process structure diagram corresponding to step S10 in a method for preparing a back-contact battery provided in an embodiment of the present invention.

[0057] Description of Figure Numbers.

[0058] 1-silicon wafer; 2-tunneling silicon oxide layer; 3-N-type doped polysilicon layer; 4-mask layer; 5-intrinsic hydrogenated amorphous silicon layer; 6-P-type doped amorphous layer or P-type microcrystalline silicon layer; 7-passivation layer; 8-anti-reflection layer; 9-transparent conductive film layer; 10-metal electrode. DETAILED DESCRIPTION

[0059] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0060] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0062] like Figure 3 As shown, an embodiment of the present invention provides a method for preparing a back contact battery, comprising the following steps:

[0063] S1. Provide a silicon wafer, and polish both sides of the silicon wafer.

[0064] Specifically, the silicon wafer is an N-type single crystal silicon wafer, and both the front and back sides of the silicon wafer are polished and cleaned. Optionally, the silicon wafer is a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer, see Figure 4 .

[0065] S2. Forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer.

[0066] Optionally, the mask layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, preferably silicon nitride.

[0067] Optionally, see Figure 5The thickness of the tunneling silicon oxide layer is 1-2nm, the thickness of the N-type doped polysilicon layer is 70-120nm, and the thickness of the mask layer is 40-90nm; the tunneling silicon oxide layer, the N-type doped polysilicon layer, and the mask layer are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 400-500°C.

[0068] When depositing the tunnel oxide layer, the mass flow rate of nitrous oxide is 8000-1200sccm, the pressure is 100-200 Pa, the power supply is 3-20KW, and the time is 20-100 seconds; when depositing the N-type doped polysilicon layer, the mass flow rate of silane is 1000-3000sccm, phosphine (2% PH3 and 98% The mass flow rate of H2 is 1000-2500sccm, the mass flow rate of hydrogen is 7000-9000sccm, the mass flow rate of methane is 200-2000sccm, the pressure is 200-500 Pa, the power is 5-20KW, and the time is 800-1300 seconds; when depositing the mask layer, the mass flow rate of silane is 1000-2000sccm, the mass flow rate of ammonia is 2000-15000sccm, the mass flow rate of methane is 200-2000sccm, the pressure is 200-300 Pa, the power is 3-20KW, and the time is 300-800 seconds; in the N-type doped polysilicon layer, the mass flow ratio of silane to methane is 1: (0.1-3), and the carbon doping concentration in the N-type doped polysilicon layer is 5×10 17 cm -3 -1×10 19 cm -3 The ratio of silane to methane in the mask layer is 1:(0.5-2), and the carbon doping concentration in the mask layer is 1×10 17 -9×10 18 cm -3 By doping a certain proportion of methane (carbon element), the corrosion rate of the film layer in the alkaline solution can be reduced, which is beneficial to improving the density and corrosion resistance of the polycrystalline and silicon nitride film layer, which is beneficial to the subsequent resistance to solution corrosion, and thus helps to extend the texturing time.

[0069] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region W2.

[0070] Alternatively, if Figure 6As shown, the first etching opening is carried out by laser or mask etching. The laser is an ultraviolet or green laser with a pulse width of less than 10ns. The width W2 of the formed second semiconductor opening area is 400-600μm, and the laser etching depth of the second semiconductor opening area is 150-300nm. The laser etching depth is increased relative to the etching depth of the existing back contact battery. A longer texturing time is required to eliminate the body silicon damaged by the laser, which is beneficial to the subsequent film passivation. The increase in etching depth invisibly increases the surface area of ​​the second semiconductor area, which is beneficial to increase the short-circuit current and fill factor of the battery.

[0071] S4, texturing and cleaning the opening areas on the front and back sides of the silicon wafer.

[0072] Specifically, Figure 7 As shown, the texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%~5%, the mass percentage of the texturing additive is 0.5%~1%, the texturing time is 8~45 minutes, and the texturing temperature is 75℃~85℃; after texturing cleaning, an inverted frustum-shaped structured texturing surface with grooves is formed in the P-type semiconductor region on the back of the silicon wafer, and the maximum depth H of the groove is 1~4μm, as shown in FIG. Figure 2 As shown. The texturing cleaning adopts the method of immersing the silicon wafer in a solution tank for chemical reaction texturing. It should be noted that the deeper the laser etching depth, the more serious the damage to the body silicon by the laser etching, and a longer texturing time is required to eliminate the damaged body silicon part (texturing not only produces the pyramid velvet surface, but also eliminates the laser damage during the texturing process), which is conducive to the subsequent film passivation. A longer texturing time requires a more corrosion-resistant carbon-doped film layer as a guarantee.

[0073] After the above-mentioned silicon wafer is cleaned by texturing, the back of the silicon wafer is single-sided polished by chain cleaning. The solution used for polishing is a mixture of potassium hydroxide or sodium hydroxide and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%~5%, the polishing time is 5~30 minutes, and the texturing temperature is 50℃~70℃. Single-sided polishing causes the tip of the velvet surface of the four-sided pyramid structure of the P-type semiconductor region on the back of the silicon wafer to be cut off by 1 / 5~1 / 2, forming a velvet effect of a frustum-shaped structure. It can be understood that the higher the carbon doping concentration, the slower the corrosion rate of the film layer in the alkali solution, indicating that its alkali resistance performance is higher, so the corresponding polishing time can be longer.

[0074] In this embodiment, since the frustum morphology increases the flatness of the top and reduces the tip points relative to the pyramid morphology, it is beneficial for the film layer to cover the surface of the velvet more evenly, so it is beneficial to improve the passivation effect; the improvement of the passivation effect and the deep-set frustum structure increase the surface area of ​​the second semiconductor layer, and the combination of the two is beneficial to improve FF. During the polishing process, the mask layer on the back of the silicon wafer is also removed by the final cleaning solution; wherein, polishing is performed by polishing and etching with alkaline solution, and after the polishing is completed, it generally needs to pass through a water tank and other cleaning tanks, and finally needs to pass through an HF solution tank, and the mask layer is removed in this HF solution tank. Optionally, the solution used to remove the mask layer is HF acid, the mass percentage of HF acid is 0.5%~5%, the mass percentage of deionized water is 95%~99.5%, the processing temperature is 20℃~30℃, and the removal time is 60~300s.

[0075] S5. Form a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer.

[0076] Specifically, Figure 8 As shown, the second semiconductor layer may be a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous layer or a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type microcrystalline silicon layer, or a stack of a tunneling silicon oxide layer and a P-type doped polycrystalline silicon layer. Preferably, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer.

[0077] S6. Form a passivation layer and anti-reflection layer on the front side of the silicon wafer.

[0078] Alternatively, if Fig. 9 As shown, the passivation layer can be one or a combination of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer. Preferably, the passivation layer is a combination of silicon oxide and aluminum oxide passivation layers, the thickness of silicon oxide is 1-2nm, and the thickness of aluminum oxide is 3-4nm.

[0079] The anti-reflection layer can be one or a combination of silicon nitride, aluminum oxide and silicon oxide. Preferably, the anti-reflection layer is a combination of silicon nitride and silicon oxide, the thickness of silicon nitride is 50-100nm, and the thickness of silicon oxide is 80-150nm.

[0080] S7. Etch an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region.

[0081] Alternatively, if Fig.10 As shown, the second etching opening is performed by laser, the laser can be ultraviolet or green laser, and the pulse width is less than 10ns. The width W1 of the formed first semiconductor opening region is 100-250 μm.

[0082] S8. Depositing a conductive film layer on the back side of the silicon wafer.

[0083] Alternatively, if Fig.11 As shown, a transparent conductive film layer is deposited on the back of a silicon wafer using physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD). The thickness of the transparent conductive film layer is 40-80nm. The material of the transparent conductive film layer can be an indium oxide-based film doped with tin / tungsten / titanium / zinc or an aluminum / boron-doped zinc oxide-based film.

[0084] S9. Etch an opening on the back side of the silicon wafer for the third time to form an insulating groove W3.

[0085] Alternatively, if Fig.12 As shown, mask etching or laser etching is used to etch an opening on the back of the silicon wafer to form an insulating groove between the first semiconductor and the second semiconductor. The width W3 of the insulating groove is 20-100 μm. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 KΩ.

[0086] S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0087] Alternatively, if Fig.13 As shown, metal electrodes are formed on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer by using screen printing technology.

[0088] The second aspect, such as Figure 1 As shown, an embodiment of the present invention further provides a back-contact battery, which is obtained based on the preparation method in the above embodiment, and the back-contact battery includes: a silicon wafer, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. Among them, the silicon wafer has a front side and a back side, wherein the front side refers to the light-receiving surface of the silicon wafer, and the back side is the opposite back side of the light-receiving surface. In the embodiment of the present invention, the side close to the silicon wafer is usually considered as the inside, and the side far from the silicon wafer is considered as the outside.

[0089] The first semiconductor layer is arranged on the back of the silicon wafer, and the first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer sequentially formed on the silicon wafer; the carbon doping concentration in the N-type doped polysilicon layer is 5×10 17 cm -3 -1×10 19 cm -3 .

[0090] The first semiconductor layer is separated by multiple second semiconductor opening regions, and the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with a second semiconductor layer, and the second semiconductor layer is composed of an intrinsic amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer; a first semiconductor opening region is provided between adjacent second semiconductor opening regions, and the first semiconductor opening region separates the second semiconductor layer.

[0091] The third semiconductor layer is arranged on the front side of the silicon wafer, and the third semiconductor layer includes a passivation layer and an anti-reflection layer stacked together.

[0092] Among them, the surface of the silicon wafer located on the front side of the silicon wafer and in the second semiconductor region is finally formed into a velvet surface with an inverted frustum-shaped structure through texturing and cleaning. The velvet surface with an inverted frustum-shaped structure is prepared by texturing, cleaning and polishing processes, and the second semiconductor layer is filled in the corresponding area of ​​the velvet surface, thereby forming a surface structure of the frustum-shaped velvet structure.

[0093] Optionally, the height of the velvet surface of the inverted frustum-shaped structure is 1-4 μm, and the top surface area of ​​the inverted frustum accounts for 1 / 9-1 / 2 of the bottom surface area, wherein the top surface area refers to the area of ​​the smaller end, and the bottom surface area refers to the area of ​​the larger end.

[0094] Optionally, the width W2 of the second semiconductor opening region formed is 400-600 μm, and the width W1 of the first semiconductor opening region formed is 200-300 μm.

[0095] Optionally, the back contact cell further comprises: an anti-reflection layer; the anti-reflection layer is arranged on one side of the front side of the silicon wafer, and the anti-reflection layer and the area corresponding to the front side of the silicon wafer are both formed with a frustum-shaped velvet structure.

[0096] Optionally, the back contact battery further comprises: an insulating groove; the insulating groove is located between the adjacent first semiconductor opening region and the second semiconductor opening region; the first semiconductor opening region and the second semiconductor layer are both covered with a transparent conductive film layer, and the insulating groove separates the transparent conductive film layer located in the first semiconductor opening region from the transparent conductive film layer located on the second semiconductor layer. Optionally, the width W3 of the insulating groove is 20-100 μm.

[0097] The back-contact battery obtained by the preparation method of the above-mentioned back-contact battery in the embodiment of the present invention improves the acid and alkali corrosion resistance of the first semiconductor layer and the mask layer by adding a certain proportion of carbon elements during the deposition of the first semiconductor layer and the mask layer, which is beneficial to prolonging the texturing time; at the same time, by increasing the laser etching depth, the texturing time is extended to form a recessed texturing structure in the second semiconductor opening area, and then local polishing is performed to flatten the tip of the four-sided pyramid structure to form a texturing surface with an inverted cone-shaped structure in the second semiconductor opening area, which is beneficial to improving the passivation effect and improving FF.

[0098] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0099] Example 1

[0100] A method for preparing a back contact battery comprises: S1, providing a silicon wafer, and polishing both sides of the silicon wafer;

[0101] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer;

[0102] Among them, when depositing the N-type doped polysilicon layer, the mass flow rate of silane is 2000sccm, the mass flow rate of phosphine (2% PH3 and 98% H2) is 1800sccm, the mass flow rate of hydrogen is 8000sccm, the mass flow rate of methane is 500sccm, the pressure is 400 Pa, the power is 4KW, and the time is 1900 seconds; when depositing the mask layer, the mass flow rate of silane is 1200sccm, the mass flow rate of ammonia is 9600sccm, the mass flow rate of methane is 1080sccm, the pressure is 230 Pa, the power is 6.5KW, and the time is 920 seconds; the mass flow ratio of silane to methane in the N-type doped polysilicon layer is 1: 0.25, and the carbon doping concentration in the N-type doped polysilicon layer is 9.6×10 18 cm -3 The mass flow ratio of silane to methane in the mask layer is 1:0.9, and the carbon doping concentration in the mask layer is 8.5×10 17 cm -3 ;

[0103] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region W2.

[0104] The laser etching depth of the second semiconductor opening region W2 is 215 nm.

[0105] S4, texturing and cleaning the opening areas on the front and back sides of the silicon wafer.

[0106] The texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 3.5%, the mass percentage of the texturing additive is 0.8%, the texturing time is 18 minutes, and the texturing temperature is 80°C; after texturing cleaning, an inverted truncated cone-shaped texturing surface with grooves is formed on the P-type semiconductor region on the back of the silicon wafer, and the maximum depth H of the grooves is 3.8 μm;

[0107] After the above-mentioned silicon wafer is cleaned by texturing, the back side of the silicon wafer is single-sided polished by chain cleaning. The solution used for polishing is a mixture of potassium hydroxide or sodium hydroxide and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 4.5%. The polishing time is 7.5 minutes and the polishing temperature is 70°C. The single-sided polishing causes the tip of the inverted frustum-shaped structure of the velvet surface of the P-type semiconductor region on the back side of the silicon wafer to be cut off by 9 / 20, thus forming a velvet effect of the inverted frustum-shaped structure. During the polishing process, the mask layer on the back side of the silicon wafer is also removed by the final cleaning solution.

[0108] S5, forming a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer;

[0109] S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0110] S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region;

[0111] S8, depositing a conductive film layer on the back side of the silicon wafer;

[0112] S9, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove;

[0113] S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0114] Example 2

[0115] Referring to the method for preparing a back contact cell of Example 1, the difference is that the mass flow rate of methane when depositing the N-type doped polysilicon layer in step S2 is adjusted so that the mass flow rate of methane is 330 sccm, and the corresponding texturing time is 13 minutes.

[0116] Example 3

[0117] The method for preparing a back contact cell is described with reference to Example 1, except that the mass flow rate of methane during deposition of the mask layer in step S2 is adjusted to be 200 sccm, and the corresponding texturing time is 8 minutes.

[0118] Example 4

[0119] Referring to the method for preparing the back contact cell of Example 1, the difference is that the deposition power of depositing the N-type doped polysilicon layer in step S2 is adjusted to 5 kW, and the corresponding texturing time is 20 minutes.

[0120] Example 5

[0121] The method for preparing a back contact cell is described with reference to Example 1, except that the deposition power of methane is adjusted to 5.5 kw when depositing the mask layer in step S2, and the corresponding texturing time is 25 minutes.

[0122] Example 6

[0123] The method for preparing a back contact battery is referred to in Example 1, except that the depth of the laser etching in step S3 is adjusted so that the etching depth of the second semiconductor opening region is 150 nm, and the corresponding texturing time is 10 minutes.

[0124] Comparative Example 1

[0125] The method for preparing a back contact cell is described with reference to Example 1, except that methane is not introduced when depositing the N-type doped polysilicon layer in step S2.

[0126] Comparative Example 2

[0127] The method for preparing a back contact cell is described with reference to Example 1, except that methane is not introduced when depositing the mask layer in step S2.

[0128] Comparative Example 3

[0129] The method for preparing a back contact cell is described with reference to Example 1, except that methane is not introduced when depositing the N-type doped polysilicon layer and the mask layer in step S2.

[0130] Comparative Example 4

[0131] The method for preparing a back contact cell is described with reference to Example 1, except that the mass flow rate of methane during the deposition of the N-type doped polysilicon layer in step S2 is adjusted to be 100 sccm.

[0132] Comparative Example 5

[0133] The method for preparing a back contact cell is described with reference to Example 1, except that the mass flow rate of methane during deposition of the mask layer in step S2 is adjusted to be 300 sccm.

[0134] Comparative Example 6

[0135] The method for preparing a back contact cell is described with reference to Example 1, except that the depth of the laser etching in step S3 is adjusted so that the etching depth of the second semiconductor opening region is 50 nm.

[0136] Test Case

[0137] The back contact cells obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. Among them, the performance indicators of each embodiment and comparative example were converted using embodiment 1 as a reference benchmark, the data of embodiment 1 was normalized benchmark 1, and other examples were converted based on embodiment 1, such as the conversion efficiency of comparative example 1 / the conversion efficiency of embodiment 1 was 0.959. In the normalization process, the unit of open circuit voltage is V, the unit of fill factor is %, and the unit of battery conversion efficiency is %.

[0138] Table 1 Comparison of performance parameters of various embodiments and comparative examples

[0139]

[0140] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can improve the corrosion resistance of the film layer, ensure the passivation effect and the filling factor, and is beneficial to the improvement of battery performance. Furthermore, according to Example 1 and Examples 2-6, it can be seen that the preferred parameter scheme of the present invention can further improve the performance of passivation and filling factor, and is more conducive to further improvement of battery conversion efficiency.

[0141] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A silicon wafer having a front side and a back side; A first semiconductor layer is arranged on the back of the silicon wafer, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer sequentially formed on the silicon wafer; the carbon doping concentration in the N-type doped polysilicon layer is 5×10 17 cm -3 -1×10 19 cm -3 ; The first semiconductor layer is separated by a plurality of second semiconductor opening regions, the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with a second semiconductor layer, the second semiconductor layer is composed of an intrinsic amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer; a first semiconductor opening region is arranged between adjacent second semiconductor opening regions, the first semiconductor opening region separates the second semiconductor layer; wherein the surface of the silicon wafer located in the second semiconductor opening region is a velvet surface of an inverted frustum-shaped structure, the velvet surface is prepared by etching and velvet cleaning the first semiconductor layer, and the carbon doping concentration in the mask layer covering the first semiconductor layer during etching is 1×10 17 cm -3 -9×10 18 cm -3 The second semiconductor layer fills the velvet in the corresponding area to form a truncated cone shaped velvet structure.

2. The back contact battery according to claim 1, characterized in that: The height of the velvet surface of the inverted frustum-shaped structure is 1-4 μm, and the top surface area of ​​the inverted frustum-shaped structure accounts for 1 / 9-1 / 2 of the bottom surface area.

3. The back contact battery according to claim 1, characterized in that: The width of the second semiconductor opening region formed is 400-600 μm, and the width of the first semiconductor opening region formed is 200-300 μm.

4. The back contact battery according to claim 1, characterized in that: Also includes: The anti-reflection layer is arranged on one side of the front side of the silicon wafer, and a frustum-shaped velvet structure is formed in the area of ​​the anti-reflection layer corresponding to the front side of the silicon wafer.

5. The back contact battery according to claim 1, characterized in that: Also includes: Insulation slot; The insulating groove is located between the adjacent first semiconductor opening region and the second semiconductor opening region; The first semiconductor opening region and the second semiconductor layer are both covered with a transparent conductive film layer, and the insulating groove separates the transparent conductive film layer located in the first semiconductor opening region from the transparent conductive film layer located on the second semiconductor layer.

6. The back contact battery according to claim 5, characterized in that: The width of the insulating groove is 20-100 μm.

7. A method for preparing a back contact battery, characterized in that: include: S1. Provide a silicon wafer, and polish both sides of the silicon wafer; S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer; When depositing the N-type doped polysilicon layer, the mass flow rate of silane is 1000-3000sccm, the mass flow rate of phosphine is 1000-2500sccm, the mass flow rate of hydrogen is 7000-9000sccm, the mass flow rate of methane is 200-2000sccm, the pressure is 200-500 Pa, the power is 5-20KW, and the time is 800-1300 seconds; when depositing the mask layer, the mass flow rate of silane is 1000-2000sccm, the mass flow rate of ammonia is 2000-15000sccm, the mass flow rate of methane is 200-2000sccm, the pressure is 200-300 Pa, the power is 3-20KW, and the time is 300-800 seconds; the mass flow ratio of silane to methane in the N-type doped polysilicon layer is 1:(0.1~3), and the carbon doping concentration in the N-type doped polysilicon layer is 5×10 17 cm -3 -1×10 19 cm -3 The mass flow ratio of silane to methane in the mask layer is 1:(0.5-2), and the carbon doping concentration in the mask layer is 1×10 17 cm -3 -9×10 18 cm -3 ; S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; The etching depth of the second semiconductor opening region is 150-300nm; S4, texturing and cleaning the opening areas on the front and back sides of the silicon wafer; The texturing liquid is a mixture of potassium hydroxide or sodium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%~5%, the mass percentage of the texturing additive is 0.5%~1%, the texturing time is 8~45 minutes, and the texturing temperature is 75℃~85℃; after texturing cleaning, an inverted frustum-shaped texture surface with grooves is formed in the P-type semiconductor region on the back of the silicon wafer, and the maximum depth H of the groove is 1~4μm; After the above-mentioned silicon wafer is cleaned and texturized, the back side of the silicon wafer is single-sided polished by chain cleaning. The solution used for polishing is a mixture of potassium hydroxide or sodium hydroxide and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1% to 5%. The polishing time is 5 to 30 minutes, and the texturizing temperature is 50°C to 70°C. The single-sided polishing causes the tip of the inverted frustum-shaped structure of the velvet surface of the P-type semiconductor region on the back side of the silicon wafer to be cut off by 1 / 5 to 1 / 2, forming a velvet effect of an inverted frustum-shaped structure. During the polishing process, the mask layer on the back side of the silicon wafer is also removed by the final cleaning solution. S5, forming a second semiconductor layer on the back side of the silicon wafer; the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous layer or a P-type microcrystalline silicon layer; S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region; S8, depositing a conductive film layer on the back side of the silicon wafer; S9, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove; S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

8. The method for preparing a back contact battery according to claim 7, characterized in that: Step S2 specifically includes: The thickness of the tunneling silicon oxide layer is 1-2nm, the thickness of the N-type doped polysilicon layer is 70-120nm, and the thickness of the mask layer is 40-90nm; the tunneling silicon oxide layer, the N-type doped polysilicon layer, and the mask layer are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 400-500°C.

9. The method for preparing a back contact battery according to claim 7, characterized in that: Step S3 specifically includes: The first etching opening is performed by laser or mask etching, the laser is ultraviolet or green laser, the pulse width is less than 10ns, the width of the formed second semiconductor opening area is 400-600μm, and the laser etching depth is 150-300nm.

10. The method for preparing a back contact battery according to claim 7, characterized in that: In step S7, the solution used to remove the mask layer is HF acid solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 60-300s.

11. The method for preparing a back contact battery according to claim 7, characterized in that: In step S7, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer includes: The passivation layer is one or a combination of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; the anti-reflection layer is one or a combination of silicon nitride, aluminum oxide or a silicon oxide layer.

12. The method for preparing a back contact battery according to claim 7, characterized in that: In step S8, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region includes: The second etching opening is performed by laser, the laser is ultraviolet or green laser, and the pulse width is less than 10ns; the width of the formed first semiconductor opening area is 200-300μm.

13. The method for preparing a back contact battery according to claim 7, characterized in that: In step S9, depositing a conductive film layer on the back side of the silicon wafer includes: A transparent conductive film layer is deposited on the back of a silicon wafer using physical vapor deposition technology or activated plasma deposition technology. The thickness of the transparent conductive film layer is 40-80nm. The material of the transparent conductive film layer is an indium oxide-based film doped with tin / tungsten / titanium / zinc, or an aluminum / boron-doped zinc oxide-based film.

14. The method for preparing a back contact battery according to claim 7, characterized in that: In step S10, etching an opening on the back side of the silicon wafer for the third time to form an insulating groove includes: An opening is etched on the back of the silicon wafer by mask etching or laser, forming an insulating groove between the first semiconductor opening area and the second semiconductor opening area. The width of the insulating groove is 20-100 μm. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 KΩ.

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