Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and is used for realizing a display product with higher resolution. The display panel comprises a substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, and each sub-pixel driving circuit comprises a first conductive connecting part, a driving transistor, a sensing transistor and a storage capacitor; a first pole plate of the storage capacitor is coupled with a grid electrode of the driving transistor, and a second pole plate of the storage capacitor is located on one side, back to the substrate, of the first pole plate of the storage capacitor; at least part of the first conductive connecting part is located on the side, back to the substrate, of the second pole plate, and the first conductive connecting part is coupled with the second pole plate and the second pole of the driving transistor through a via hole structure; at least part of the second electrode of the sensing transistor is located on the side, back to the substrate, of the first conductive connecting part, and the second electrode of the sensing transistor is coupled with the first conductive connecting part.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the promotion of AR / VR technology, high PPI display products have become a technology that must be conquered. However, display products formed by thin-film transistor devices based on glass-based substrates and PI (polyimide)-based substrates can only achieve 500-600PPI at present, which cannot meet the demand for VR near-eye display higher than 1800PPI. For example: In existing display products using LTPS (low-temperature polycrystalline silicon) or LTPO (low-temperature polycrystalline oxide) technology, a 7T1C or 8T1C internal compensation pixel circuit structure is generally used. Due to the large number of thin-film transistor devices required for this structure, the resolution of the display product can only stop at 600PPI.

[0003] Therefore, how to achieve higher resolution display products has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] An object of the present invention is to provide a display panel and a display device for realizing a display product with a higher resolution.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit includes a first conductive connection portion, a driving transistor, a sensing transistor and a storage capacitor;

[0007] The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is located on a side of the first plate of the storage capacitor facing away from the substrate;

[0008] At least a portion of the first conductive connection portion is located on a side of the second electrode plate facing away from the substrate, and the first conductive connection portion is coupled to the second electrode plate and the second electrode of the driving transistor respectively through a via structure;

[0009] At least a portion of the second electrode of the sensing transistor is located on a side of the first conductive connection portion facing away from the substrate, and the second electrode of the sensing transistor is coupled to the first conductive connection portion.

[0010] Optionally, the second electrode of the driving transistor is located on a side of the gate of the driving transistor facing the substrate, and at least a part of the orthographic projection of the second electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second electrode on the substrate;

[0011] The via structure includes a first via and a second via that are connected to each other, the first conductive connection portion is coupled to the second electrode plate through the second via, and the first conductive connection portion is coupled to the second electrode of the driving transistor through the second via and the first via.

[0012] Optionally, the first conductive connection portion includes a first conductive part and a second conductive part coupled to each other, the first conductive part is located in the via structure, and the first conductive part is coupled to the second electrode plate and the second electrode of the driving transistor respectively, and the second conductive part is located outside the via structure, and the second conductive part is coupled to the second electrode of the sensing transistor.

[0013] Optionally, the sub-pixel driving circuit further includes a first planar layer, wherein the first planar layer is located in the via structure and on a side of the first conductive portion facing away from the substrate;

[0014] The sub-pixel driving circuit further includes a second conductive connection portion, the second conductive connection portion covers the first planar layer and contacts the second conductive portion;

[0015] At least a portion of the second electrode of the sensing transistor is located on a side of the second conductive connection portion facing away from the substrate, and is coupled to the second conductive connection portion.

[0016] Optionally, the orthographic projection of the second conductive portion on the substrate surrounds the orthographic projection of the first conductive portion on the substrate;

[0017] The orthographic projection of the second conductive portion on the base substrate is located inside the orthographic projection of the second conductive connecting portion on the base substrate.

[0018] Optionally, at least a portion of the second electrode of the sensing transistor contacts a side surface of the second conductive connection portion and a side surface of the second conductive portion.

[0019] Optionally, the sub-pixel driving circuit also includes a third conductive connection portion, at least a portion of the third conductive connection portion is located on the side of the second pole of the sensing transistor that is away from the substrate, and the third conductive connection portion is respectively coupled to the second conductive connection portion, the second pole of the sensing transistor, and the anode of the light-emitting element.

[0020] Optionally, the sub-pixel driving circuit also includes a third conductive connection portion, at least a portion of which is located on the side of the second pole of the sensing transistor facing away from the substrate, and the third conductive connection portion is respectively coupled to the second conductive portion, the second pole of the sensing transistor, and the anode of the light-emitting element.

[0021] Optionally, the sub-pixel driving circuit also includes a compensation electrode layer and a data writing transistor, the compensation electrode layer is located on the side of the second pole of the data writing transistor facing away from the substrate, and the compensation electrode layer is coupled to the second pole of the data writing transistor through a third via; the compensation electrode layer is also coupled to the gate of the driving transistor; the orthographic projection of the compensation electrode layer on the substrate at least partially overlaps with the orthographic projection of the second pole on the substrate.

[0022] Optionally, at least a portion of the compensation electrode layer is located on a side of the gate of the driving transistor facing away from the substrate, and the compensation electrode layer is directly overlapped with the gate of the driving transistor.

[0023] Optionally, the display panel includes a first gate metal layer and a second gate metal layer stacked in sequence in a direction away from the base substrate;

[0024] The gate of the driving transistor is provided in the same layer and material as the first gate metal layer, the second electrode is provided in the same layer and material as the second gate metal layer, and at least part of the compensation electrode layer is located between the first gate metal layer and the second gate metal layer.

[0025] Optionally, the compensation electrode layer includes an indium tin oxide layer or a metal layer.

[0026] Optionally, the sub-pixel driving circuit also includes a fourth conductive connection portion and a data writing transistor, the fourth conductive connection portion being coupled to the gate of the driving transistor and the second electrode of the data writing transistor respectively; the fourth conductive connection portion is arranged in the same layer and material as the first conductive connection portion.

[0027] Optionally, the sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the gate of the driving transistor;

[0028] The gate of the sensing transistor is coupled to the corresponding scan line, and the first electrode of the sensing transistor is coupled to the sensing line;

[0029] The first electrode of the driving transistor is coupled to the corresponding power line, and the second electrode of the driving transistor is also coupled to the anode of the light emitting element;

[0030] The data writing transistor and the driving transistor are low temperature polysilicon transistors, and the sensing transistor is an oxide transistor.

[0031] Based on the technical solution of the above display panel, a second aspect of the present invention provides a display device including the above display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 A circuit schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0034] Figure 2 A driving timing diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0035] Figure 3 A first cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention;

[0036] Figure 4 A second cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention;

[0037] Figure 5 A third cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 6 A fourth cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention;

[0039] Figure 7 A schematic diagram of the layout of the bottom gate metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0040] Figure 8 A schematic diagram of the layout of the second source-drain metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0041] Fig. 9 for Figure 7 and Figure 8 Schematic diagram of the layout of the cascade setup;

[0042] Fig.10 A schematic diagram of the layout of the first active layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0043] Fig.11 For Fig. 9On the basis of superposition Fig.10 Schematic diagram of the layout;

[0044] Fig.12 A schematic diagram of the layout of via holes on the first gate insulating layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0045] Fig.13 A schematic diagram of the layout of the first gate metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0046] Fig.14 For Fig.11 On the basis of superposition Fig.12 and Fig.13 Schematic diagram of the layout;

[0047] Fig.15 A schematic diagram of the layout of a compensation metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0048] Fig.16 For Fig.14 On the basis of superposition Fig.15 Schematic diagram of the layout;

[0049] Fig.17 A schematic diagram of the layout of via holes on the second gate insulating layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0050] Fig.18 A schematic diagram of the layout of the second gate metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0051] Fig.19 For Fig.16 On the basis of superposition Fig.17 and Fig.18 Schematic diagram of the layout;

[0052] Fig. 20 A schematic diagram of the layout of the via structure in the sub-pixel driving circuit distributed in a 2*6 array in the display panel provided by an embodiment of the present invention;

[0053] Fig.21 A schematic diagram of the layout of the first conductive connection portion in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0054] Fig. 22 A schematic diagram of the layout of the film layer where the first active layer to the first conductive connection portion is located in the sub-pixel driving circuit distributed in a 2*6 array in the display panel provided by an embodiment of the present invention;

[0055] Fig.23 A schematic diagram of the layout of the first planar layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0056] Fig.24 A schematic diagram of the layout of the second conductive connection portion in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0057] Fig.25 For Fig. 22 On the basis of superposition Fig.23 and Fig.24 Schematic diagram of the layout;

[0058] Fig.26 A schematic diagram of the layout of the second active layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0059] Fig. 27 A schematic layout diagram of a via structure, a first conductive connection portion, a first flat layer, a second conductive connection portion, and a second active layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0060] Fig.28 A schematic diagram of the layout of the third gate metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0061] Fig.29 For Fig. 27 On the basis of superposition Fig.28 Schematic diagram of the layout;

[0062] Fig.30 A schematic diagram of the layout of deep holes penetrating the insulating layer between the first source-drain metal layer and the first active layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0063] Fig.31 A schematic diagram of the layout of shallow holes penetrating the insulating layer between the first source-drain metal layer and the second active layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0064] Fig.32 A schematic diagram of the layout of the first source-drain metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0065] Fig.33 A schematic diagram of the layout of the first active layer to the first source-drain metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0066] Fig.34A schematic diagram of the layout of the eighth via hole in the sub-pixel driving circuit distributed in a 2*6 array in the display panel provided by an embodiment of the present invention;

[0067] Fig.35 A schematic diagram of the layout of the third source-drain metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0068] Fig.36 A schematic diagram of the layout of the second active layer to the third source-drain metal layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0069] Fig.37 A schematic diagram of the layout of vias penetrating the second planar layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0070] Fig.38 A schematic diagram of the layout of vias penetrating the second passivation layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0071] Fig.39 A schematic diagram of the layout of the anode layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0072] Fig.40 A schematic diagram of the layout of the first source-drain metal layer to the anode layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0073] Fig.41 A schematic diagram of the layout of a pixel opening area defined by a pixel defining layer in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention;

[0074] Fig.42 A schematic diagram of the layout of the first source-drain metal layer to the pixel opening region in a sub-pixel driving circuit distributed in a 2*6 array in a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to further illustrate the display panel and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0076] See also Figure 1 , Figure 5 , Figure 6 , Figures 7 to 22, an embodiment of the present invention provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprising a first conductive connection portion 11, a driving transistor M3, a sensing transistor M2 and a storage capacitor Cst;

[0077] The first plate Cst1 of the storage capacitor Cst is coupled to the gate M3-g of the driving transistor M3, and the second plate Cst2 of the storage capacitor Cst is located on a side of the first plate Cst1 of the storage capacitor Cst that faces away from the substrate;

[0078] At least a portion of the first conductive connection portion 11 is located on a side of the second electrode plate Cst2 facing away from the substrate, and the first conductive connection portion 11 is coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 through a via structure 20;

[0079] At least a portion of the second electrode M2 ​​- 2 of the sensing transistor M2 is located on a side of the first conductive connection portion 11 facing away from the substrate, and the second electrode M2 ​​- 2 of the sensing transistor M2 is coupled to the first conductive connection portion 11 .

[0080] It should be noted that Figures 7 to 42 The area framed by the rectangular box in is the layout area corresponding to a sub-pixel driving circuit.

[0081] Exemplarily, the display panel includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0082] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode Ano of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0083] For example, Figure 1 As shown, the sub-pixel driving circuit adopts a 3T1C (ie, three transistors and one capacitor) circuit structure, and the sub-pixel driving circuit specifically includes a driving transistor M3, a sensing transistor M2, a data writing transistor M1 and a storage capacitor Cst.

[0084] The gate of the data writing transistor M1 is coupled to the corresponding scanning line GL, the first electrode M1-1 of the data writing transistor M1 is coupled to the corresponding data line DL, and the second electrode M1-2 of the data writing transistor M1 is coupled to the gate M3-g of the driving transistor M3. Figure 3 As shown, the fifth conductive connection portion 15 is respectively coupled to the first electrode M1 - 1 of the data writing transistor M1 and the corresponding data line DL through the seventh via hole Via7 .

[0085] The gate of the sensing transistor M2 is coupled to the corresponding scan line GL, the first electrode M2-1 of the sensing transistor M2 is coupled to the corresponding sensing line SL, and the second electrode M2-2 of the sensing transistor M2 is coupled to the second electrode M3-2 of the driving transistor M3. Figure 3 As shown, the first electrode M2 ​​- 1 of the sensing transistor M2 is coupled to the corresponding sensing line SL through the eighth via hole Via8 .

[0086] The first plate Cst1 of the storage capacitor Cst is coupled to the gate M3-g of the driving transistor M3, and the second plate Cst2 of the storage capacitor Cst is coupled to the second plate M3-2 of the driving transistor M3. The first plate M3-1 of the driving transistor M3 is coupled to the corresponding power line VDD, and the second plate M3-2 of the driving transistor M3 is coupled to the anode Ano of the light-emitting element in the sub-pixel to which it belongs, and the cathode of the light-emitting element receives the VSS signal. Figure 3 As shown, the first electrode M3 - 1 of the driving transistor M3 is coupled to the corresponding power line VDD through a ninth via hole Via9 .

[0087] Exemplarily, the sensing line SL is coupled to the reference signal line VREF through a first switch S_REF, and by controlling the first switch S_REF to be closed or opened, it is possible to control whether the sensing line SL is electrically connected to the reference signal line VREF. The sensing line SL is also coupled to the sensing signal line SENS through a second switch S_SAMP, and by controlling the second switch S_SAMP to be closed or opened, it is possible to control whether the sensing line SL is electrically connected to the sensing signal line SENS.

[0088] Exemplarily, the data writing transistor M1 and the driving transistor M3 are low temperature polysilicon transistors, such as LTPS NMOS transistors; the sensing transistor M2 is an oxide transistor, such as Oxide TG NMOS transistor.

[0089] like Figure 2As shown, the driving timing diagram of the sub-pixel driving circuit is illustrated. The working timing of the sub-pixel driving circuit includes a display phase and a sensing phase. The display phase specifically includes a reset phase (not shown in the figure), a data writing phase and a light emitting phase; the sensing phase specifically includes a reset phase, a Vth compensation phase and an extraction phase.

[0090] During the display phase:

[0091] In the reset phase, the scan signal transmitted by the scan line GL controls the sensing transistor M2 to be turned on, while the first switch S_REF is closed and the second switch S_SAMP is opened, and the reference signal transmitted by the reference signal line VREF resets the potential of the N2 node.

[0092] In the data writing phase, the scan signal transmitted by the scan line GL controls the data writing transistor M1 to turn on, and writes the data signal to the N1 node;

[0093] In the light emitting stage, the driving transistor M3 is turned on to control the light emitting element to emit light.

[0094] During the sensing phase:

[0095] In the reset phase, the scan signal transmitted by the scan line GL controls the sensing transistor M2 to be turned on, while the first switch S_REF is closed and the second switch S_SAMP is opened, and the reference signal transmitted by the reference signal line VREF resets the potential of the N2 node.

[0096] In the Vth compensation phase, the sensing transistor M2 continues to be turned on to achieve threshold voltage compensation for the N2 node coupled to the driving transistor M3.

[0097] In the extraction phase, the sensing transistor M2 continues to be turned on, while the first switch S_REF is turned off and the second switch S_SAMP is turned on, and the driver chip extracts the threshold voltage of the N2 node coupled to the sensing driver transistor M3 in the current period.

[0098] After Vth is extracted, the Vth compensation value is added to the data signal through an algorithm when data is written in the display phase to achieve Vth external compensation.

[0099] Exemplarily, the first plate Cst1 of the storage capacitor Cst and the gate M3-g of the driving transistor M3 form an integral structure. The second plate Cst2 of the storage capacitor Cst is located on the side of the first plate Cst1 of the storage capacitor Cst facing away from the substrate, and the orthographic projection of the second plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the first plate Cst1 on the substrate.

[0100] Exemplarily, at least a portion of the first conductive connection portion 11 is located on the side of the second electrode plate Cst2 facing away from the base substrate, the orthographic projection of the first conductive connection portion 11 on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate Cst2 on the base substrate, the orthographic projection of the first conductive connection portion 11 on the base substrate at least partially overlaps with the orthographic projection of the second electrode M3-2 of the driving transistor M3 on the base substrate, and the first conductive connection portion 11 is respectively coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 through the via structure 20.

[0101] Exemplarily, at least a portion of the second electrode M2-2 of the sensing transistor M2 is located on a side of the first conductive connection portion 11 facing away from the substrate, and the second electrode M2-2 of the sensing transistor M2 may be directly connected to the first conductive connection portion 11, but is not limited thereto.

[0102] According to the specific structure of the above display panel, the display panel provided by the embodiment of the present invention includes a first conductive connection part 11, which can be coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3 through a via structure 20; at the same time, the second electrode M2-2 of the sensing transistor M2 is arranged on the side of the first conductive connection part 11 facing away from the substrate, and the second electrode M2-2 of the sensing transistor M2 is coupled to the first conductive connection part 11; when the display panel adopts the above structure, the first conductive connection part 11 is realized through a via structure 20 to couple the second electrode plate Cst2 of the storage capacitor Cst, the second electrode M3-2 of the driving transistor M3, and the second electrode M2-2 of the sensing transistor M2 together. Compared with the prior art that at least two via structures 20 are required to achieve the above connection relationship, the technical solution of the present invention effectively reduces the layout space occupied by the sub-pixel driving circuit as a whole, which is conducive to the display panel to achieve a higher PPI. The technical solution of the present invention can achieve a display panel with a PPI of more than 1500.

[0103] See also Figure 1 , Figure 5 , Figure 6 , Figures 7 to 22 In some embodiments, the second electrode M3-2 of the driving transistor M3 is located on a side of the gate M3-g of the driving transistor M3 facing the substrate, and at least a portion of the orthographic projection of the second electrode M3-2 of the driving transistor M3 on the substrate does not overlap with the orthographic projection of the second electrode plate Cst2 on the substrate;

[0104] The via structure 20 includes a first via Via1 and a second via Via2 that are connected to each other. The first conductive connection portion 11 is coupled to the second electrode Cst2 through the second via Via2. The first conductive connection portion 11 is coupled to the second electrode M3-2 of the driving transistor M3 through the second via Via2 and the first via Via1.

[0105] Exemplarily, the first via hole Via1 is located between the second via hole Via2 and the substrate, and the aperture of the first via hole Via1 is smaller than the aperture of the second via hole Via2.

[0106] The above-mentioned arrangement of the via structure 20 including the first via Via1 and the second via Via2 is beneficial to simplifying the layout space occupied by the entire via structure 20, thereby facilitating reducing the layout area of ​​the first conductive connection portion 11 and achieving a higher PPI of the display panel.

[0107] See also Figure 1 , Figure 5 , Figure 6 , Figures 7 to 22 In some embodiments, the first conductive connection portion 11 is provided to include a first conductive portion 111 and a second conductive portion 112 coupled to each other, the first conductive portion 111 is located in the via structure 20, and the first conductive portion 111 is respectively coupled to the second electrode plate Cst2 and the second electrode M3-2 of the driving transistor M3, the second conductive portion 112 is located outside the via structure 20, and the second conductive portion 112 is coupled to the second electrode M2-2 of the sensing transistor M2.

[0108] Exemplarily, the first conductive portion 111 and the second conductive portion 112 are formed as an integral structure.

[0109] For example, the second electrode M2 ​​- 2 of the sensing transistor M2 may be directly connected to the second conductive portion 112 , or may be electrically connected to the second conductive portion 112 through other conductive connection portions without forming a via.

[0110] The above configuration enables the second electrode M2 ​​- 2 of the sensing transistor M2 to be coupled to the portion of the first conductive connection portion 11 outside the via structure 20 , which is beneficial to improving the connection yield between the second electrode M2 ​​- 2 of the sensing transistor M2 and the first conductive connection portion 11 .

[0111] like Figure 3 , Figure 4 , Figures 10 to 29As shown, in some embodiments, the sub-pixel driving circuit also includes a first flat layer PLN1, the first flat layer PLN1 is located in the via structure 20, and is located on the side of the first conductive part 111 facing away from the substrate; the sub-pixel driving circuit also includes a second conductive connection part 12, the second conductive connection part 12 covers the first flat layer PLN1, and is in contact with the second conductive part 112; at least a part of the second electrode M2-2 of the sensing transistor M2 is located on the side of the second conductive connection part 12 facing away from the substrate, and is coupled to the second conductive connection part 12.

[0112] Exemplarily, after the first conductive connection part 11 is made in the via structure 20, the first flat layer PLN1 is continuously filled in the via structure 20, the first flat layer PLN1 fills the via structure 20, and the first flat layer PLN1 does not cover the second conductive part 112, and the surface of the first flat layer PLN1 facing away from the substrate is flat.

[0113] Exemplarily, after the first flat layer PLN1 is manufactured, the second conductive connection part 12 is manufactured, the second conductive connection part 12 completely covers the first flat layer PLN1 and contacts the second conductive part 112, so as to realize the electrical connection between the second conductive connection part 12 and the second conductive part 112. Exemplarily, the second conductive connection part 12 includes an indium tin oxide layer or a metal layer, but is not limited thereto.

[0114] Exemplarily, after the second conductive connection portion 12 is manufactured, the second electrode M2 ​​- 2 of the sensing transistor M2 is manufactured, and the second electrode M2 ​​- 2 of the sensing transistor M2 is electrically connected to the second conductive connection portion 12 , and is electrically connected to the first conductive connection portion 11 through the second conductive connection portion 12 .

[0115] like Figure 3 , Figure 4 , Figures 3 to 42 As shown, exemplarily, the sub-pixel driving circuit further includes a third conductive connection portion 13, at least a portion of the third conductive connection portion 13 is located on the side of the second pole M2-2 of the sensing transistor M2 facing away from the substrate, and the third conductive connection portion 13 is respectively coupled to the second conductive connection portion 12, the second pole M2-2 of the sensing transistor M2, and the anode Ano of the light-emitting element. For example: the third conductive connection portion 13 is provided in the same layer and material as the first source-drain metal layer in the display panel, the third conductive connection portion 13 is respectively coupled to the second conductive connection portion 12 and the second pole M2-2 of the sensing transistor M2 through the fourth via Via4, and the third conductive connection portion 13 is coupled to the anode Ano of the light-emitting element through the fifth via Via5.

[0116] It is worth noting that the fifth via hole Via5 includes a first sub-via hole Via51 and a second sub-via hole Via52 which are connected to each other. The first sub-via hole Via51 is a via hole penetrating the second planar layer, and the second sub-via hole Via52 is a via hole penetrating the second passivation layer PVX2. Fig.41 The pixel opening area K1 defined by the pixel definition layer PDL is illustrated in FIG.

[0117] It should be noted that as the PPI of the display panel continues to increase, such as above 1500PPI, due to the limitation of layout space, the via structure 20 and the fourth via Via4 will overlap in the longitudinal direction perpendicular to the base substrate. In this case, if the first planar layer PLN1 is not provided, there is a risk of short circuit.

[0118] In the display panel provided by the above embodiment, the first flat layer PLN1 is set to fill the via structure 20, and the second conductive connection part 12 is set to cover the first flat layer PLN1, and is electrically connected to the second conductive part 112 of the first conductive connection part 11, thereby realizing the electrical connection between the second conductive connection part 12 and the second pole M3-2 and the second plate Cst2 of the driving transistor M3; then the second pole M2-2 of the sensing transistor M2 is overlapped on the surface of the second conductive connection part 12, and the third conductive connection part 13 is respectively coupled to the second conductive connection part 12 and the second pole M2-2 of the sensing transistor M2 through the fourth via Via4, thereby realizing the electrical connection between the third conductive connection part 13 and the second pole M3-2 of the driving transistor M3, the second plate Cst2 of the storage capacitor Cst, and the second pole M2-2 of the sensing transistor M2. When this setting is adopted, even if the via structure 20 and the fourth via Via4 overlap in the longitudinal direction perpendicular to the substrate, the risk of short circuit will not increase. Moreover, the PPI of the display panel can be further improved by further increasing the overlapping area between the via structure 20 and the fourth via Via4 in the longitudinal direction perpendicular to the substrate.

[0119] like Figure 21 to Figure 25 As shown, in some embodiments, the orthographic projection of the second conductive portion 112 on the base substrate is set to surround the orthographic projection of the first conductive portion 111 on the base substrate; the orthographic projection of the second conductive portion 112 on the base substrate is located inside the orthographic projection of the second conductive connecting portion 12 on the base substrate.

[0120] The above-mentioned orthographic projection of the second conductive part 112 on the base substrate surrounds the orthographic projection of the first conductive part 111 on the base substrate, so that the second conductive part 112 can be distributed around the via structure 20, so that the second conductive part 112 can be arranged in a larger area outside the via structure 20; at the same time, the orthographic projection of the second conductive part 112 on the base substrate is set to be located inside the orthographic projection of the second conductive connection part 12 on the base substrate, so that the second conductive parts 112 located around the via structure 20 can all contact with the second conductive connection part 12, thereby effectively improving the connection performance between the second conductive connection part 12 and the second conductive part 112, and improving the reliability of the electrical connection.

[0121] like Figure 3 and Figure 4 As shown, in some embodiments, at least a portion of the second electrode M2 ​​- 2 of the sensing transistor M2 is configured to contact a side surface of the second conductive connection portion 12 and a side surface of the second conductive portion 112 .

[0122] The above configuration effectively improves the connection performance between the second electrode M2 ​​- 2 of the sensing transistor M2 and the second conductive portion 112 and the second conductive connecting portion 12 , and improves the reliability of the electrical connection.

[0123] like Figure 5 and Figure 6 As shown, in some embodiments, the sub-pixel driving circuit also includes a third conductive connection portion 13, at least a portion of the third conductive connection portion 13 is located on the side of the second pole M2-2 of the sensing transistor M2 facing away from the substrate, and the third conductive connection portion 13 is respectively coupled to the second conductive portion 112, the second pole M2-2 of the sensing transistor M2, and the anode Ano of the light-emitting element.

[0124] Exemplarily, the third conductive connection portion 13 is coupled to the second conductive portion 112 and the second electrode M2-2 of the sensing transistor M2 respectively through the fourth via Via4, and the orthographic projection of the fourth via Via4 on the substrate does not overlap with the orthographic projection of the via structure 20 on the substrate.

[0125] When the display panel does not include the first flat layer PLN1 and the second conductive connection part 12, the third conductive connection part 13 and the fourth via hole Via4 are arranged in the above manner, which can reduce the risk of circuit breakage.

[0126] like Figure 3 , Figure 5 , Figures 11 to 19As shown, in some embodiments, the sub-pixel driving circuit also includes a compensation electrode layer 30 and a data writing transistor M1, the compensation electrode layer 30 is located on the side of the second pole M1-2 of the data writing transistor M1 facing away from the base substrate, and the compensation electrode layer 30 is coupled to the second pole M1-2 of the data writing transistor M1 through a third via Via3; the compensation electrode layer 30 is also coupled to the gate M3-g of the driving transistor M3; the orthographic projection of the compensation electrode layer 30 on the base substrate at least partially overlaps with the orthographic projection of the second pole plate Cst2 on the base substrate.

[0127] Exemplarily, at least a portion of the compensation electrode layer 30 is located on a side of the gate M3 - g of the driving transistor M3 that faces away from the substrate, and the compensation electrode layer 30 is directly overlapped with the gate M3 - g of the driving transistor M3 .

[0128] Exemplarily, the display panel includes a first gate metal layer and a second gate metal layer stacked in sequence in a direction away from the base substrate; the gate M3-g of the driving transistor M3 is arranged in the same layer and material as the first gate metal layer, the second electrode Cst2 is arranged in the same layer and material as the second gate metal layer, and at least a portion of the compensation electrode layer 30 is located between the first gate metal layer and the second gate metal layer.

[0129] It should be noted that when manufacturing a display panel of the above structure, since the compensation electrode layer 30 is added, it is necessary to add a conductive film layer. During actual manufacturing, the compensation electrode layer 30 can be formed before the first gate metal layer or after the first gate metal layer; if it is formed before the first gate metal layer, the conductive film layer is used to form the gate of each transistor, and the conductive film layer can only be made of metal materials. In this case, the first gate metal layer is used to form the compensation electrode layer 30; if it is formed after the first gate metal layer, the conductive film layer is used to form the compensation electrode layer 30, and the conductive film layer can be made of metal layer material or indium tin oxide material. In this case, the first gate metal layer is used to form the gate of each transistor.

[0130] Exemplarily, the film layer closest to the substrate in the first gate metal layer and the conductive film layer is used as a Dopping barrier layer to achieve doping of the active layer in the transistor to form the source and drain of the transistor. The compensation electrode layer 30 serves as a signal transfer layer between the second electrode M1-2 of the data writing transistor M1 and the gate M3-g of the driving transistor M3, and also serves as a compensation electrode of the storage capacitor Cst.

[0131] Exemplarily, the compensation electrode layer 30 includes an indium tin oxide layer or a metal layer, but is not limited thereto.

[0132] In the display panel provided by the above embodiment, the second electrode M1-2 of the data writing transistor M1 and the gate M3-g of the driving transistor M3 are electrically connected together by adding the compensation electrode layer 30, so that the gate M3-g of the driving transistor M3 is connected downward to the second electrode M1-2 of the data writing transistor M1, so that the layout position of the first electrode plate Cst1 of the storage capacitor Cst (that is, the gate M3-g of the driving transistor M3) is no longer restricted by the position of the via hole and the active layer of the data writing transistor M1, and the compensation electrode layer 30 can be further deployed in the horizontal space and vertical space of the pixel, thereby increasing the electrode area, thereby effectively increasing the capacitance of the storage capacitor Cst formed between the compensation electrode layer 30 and the second electrode plate Cst2, improving the potential stability of the gate M3-g of the driving transistor M3, and improving the stability of the driving current; at the same time, because the gate M3-g of the driving transistor M3 has good potential stability, it can better avoid abnormal jumps, ensuring that the display panel can achieve various grayscale displays. Taking a 1500PPI display panel as an example, by adding the compensation electrode layer 30 , the capacitance of the storage capacitor Cst can be increased from 4.2fF to 11.9fF, which is increased by 2.8 times.

[0133] Furthermore, the addition of the compensation electrode layer 30 is also beneficial to stabilizing the gate voltage of the driving transistor M3, reducing the influence of parasitic capacitance, and alleviating the flicker problem.

[0134] like Figure 4 and Figure 6 As shown, in some embodiments, the sub-pixel driving circuit also includes a fourth conductive connection part 14 and a data writing transistor M1, and the fourth conductive connection part 14 is respectively coupled to the gate M3-g of the driving transistor M3 and the second electrode M1-2 of the data writing transistor M1; the fourth conductive connection part 14 is set in the same layer and material as the first conductive connection part 11.

[0135] Exemplarily, the fourth conductive connection portion 14 is coupled to the gate M3 - g of the driving transistor M3 and the second electrode M1 - 2 of the data writing transistor M1 respectively through a sixth via hole Via6 .

[0136] The fourth conductive connection part 14 and the first conductive connection part 11 are provided in the same layer and with the same material, so that the fourth conductive connection part 14 and the first conductive connection part 11 can be formed simultaneously in the same patterning process, which is beneficial to simplifying the manufacturing process of the display panel and reducing the manufacturing cost.

[0137] The process flow corresponding to each embodiment is described in detail below:

[0138] In such Figure 3Under the structure shown, the specific process flow of the display panel is as follows:

[0139] A bottom gate metal material layer is made of Mo on the base buffer layer BUF0, and the bottom gate metal material layer is patterned (Mask1) to form a bottom gate metal layer. The bottom gate metal layer can be used as a bottom gate bg of the driving transistor M3.

[0140] Using SiO x A first buffer layer BUF-L is produced.

[0141] The second source-drain metal material layer is made of Mo, and the second source-drain metal material layer is patterned (Mask2) to form a second source-drain metal layer.

[0142] Using SiO x / SiN x An insulating layer GI0 is produced.

[0143] A first active base layer is formed by using a P-Si material, and the first active base layer is patterned (Mask3) to form a first active layer.

[0144] Using SiO x / SiN x A first gate insulating layer GI1 is manufactured, and the first gate insulating layer is patterned (Mask4) to form a third via hole Via3.

[0145] A first gate metal material layer is made of Mo, and the first gate metal material layer is patterned (Mask5) to form a first gate metal layer.

[0146] The first gate metal layer is used as a mask to perform LDD Mask (Mask6), and Doping is performed on the first active layer.

[0147] The compensation metal material layer is made of Mo or ITO, and the compensation metal material layer is patterned (Mask7) to form a compensation electrode layer.

[0148] Using SiN x A second gate insulating layer GI2 is manufactured, and the second gate insulating layer is patterned (Mask8) to form a seventh via hole Via7.

[0149] A second gate metal material layer is made of Mo, and the second gate metal material layer is patterned (Mask9) to form a second gate metal layer.

[0150] Using SiO x Fabricate the second buffer layer BUF-O.

[0151] Mask 10 is performed to form a via structure 20 .

[0152] The first conductive material layer is made of Mo, and the first conductive material layer is patterned (Mask11) to form a first conductive connecting portion 11.

[0153] An organic material is used to form a first organic film layer, and the first organic film layer is patterned (Mask12) to form a first planar layer PLN1.

[0154] The second conductive material layer is made of ITO, and the second conductive material layer is patterned (Mask 13 ) to form a second conductive connecting portion 12 .

[0155] The second active base layer is made of IGZO, and the second active base layer is patterned (Mask14) to form a second active layer.

[0156] Using SiO x A third gate insulating layer GI3 is manufactured.

[0157] The third gate metal material layer is made of Mo, and the third gate metal material layer is patterned (Mask15) to form a third gate metal layer.

[0158] Using SiO / SiN x An interlayer insulating layer ILD is fabricated.

[0159] Perform CNT-L via process (Mask16).

[0160] Perform CNT-O via process (Mask17).

[0161] A first source-drain metal material layer of a Ti / Al / Ti stacked structure is manufactured, and the first source-drain metal material layer is patterned (Mask18) to form a first source-drain metal layer.

[0162] Using SiO x / SiN x A first passivation material layer is manufactured and patterned (Mask19) to form a first passivation layer PVX1.

[0163] A third source-drain metal material layer of a Ti / Al / Ti stacked structure is manufactured, and the third source-drain metal material layer is patterned (Mask20) to form a third source-drain metal layer.

[0164] A second organic film layer is formed by using an organic material, and the second organic film layer is patterned (Mask21) to form a second planar layer PLN2.

[0165] Using SiO x / SiNx A second passivation material layer is manufactured, and the second passivation material layer is patterned (Mask22) to form a second passivation layer PVX2.

[0166] Perform Mask23 to make anode Ano.

[0167] The pixel defining material layer is made of an inorganic material, and the pixel defining material layer is patterned (Mask 24 ) to form a pixel opening area K1 .

[0168] In such Figure 4 Under the structure shown, the specific process flow of the display panel is relative to Figure 3 The structure of the reduced Msk4 and Mask7. Figure 4 The structure shown requires 22 mask processes.

[0169] In such Figure 5 Under the structure shown, the specific process flow of the display panel is relative to Figure 3 The structure of the reduced Msk12 and Mask13. Figure 5 The structure shown requires 22 mask processes.

[0170] In such Figure 6 Under the structure shown, the specific process flow of the display panel is relative to Figure 3 The structure of the protein reduced Msk4, Mask7, Msk12 and Mask13. Figure 6 The structure shown requires 20 mask processes.

[0171] It should be noted that the solutions in the above embodiments are not limited to the 3T1C circuit structure, but can also be applied to other internal compensation or external compensation pixel circuits, and are also applicable to LTPS PMOS process or Oxide NMOS process.

[0172] An embodiment of the present invention further provides a display device, comprising the display panel provided by the above embodiment.

[0173] Exemplarily, the display device includes a Micro-LED device, a Mini-LED device, an OLED device, etc., but is not limited thereto. The display device can be applied to the AR-VR ultra-high PPI display field.

[0174] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0175] The display panel provided in the above embodiment includes a first conductive connection portion 11, which can be coupled to the second electrode Cst2 and the second electrode M3-2 of the driving transistor M3 through a via structure 20; at the same time, the second electrode M2-2 of the sensing transistor M2 is arranged on the side of the first conductive connection portion 11 facing away from the substrate, and the second electrode M2-2 of the sensing transistor M2 is coupled to the first conductive connection portion 11; when the display panel adopts the above structure, the first conductive connection portion 11 couples the second electrode Cst2 of the storage capacitor Cst, the second electrode M3-2 of the driving transistor M3, and the second electrode M2-2 of the sensing transistor M2 together through a via structure 20. Compared with the prior art that requires at least two via structures 20 to achieve the above connection relationship, the above technical solution effectively reduces the layout space occupied by the sub-pixel driving circuit as a whole, which is conducive to the display panel achieving a higher PPI.

[0176] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display panel, which will not be described in detail here.

[0177] It should be noted that the structure extending along a certain direction means that: the structure includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extending along the certain direction is greater than the length of the secondary part extending along other directions.

[0178] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0179] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0180] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0181] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0182] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0183] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0184] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels arranged on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit includes a first conductive connection portion, a driving transistor, a sensing transistor and a storage capacitor; The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is located on a side of the first plate of the storage capacitor facing away from the substrate; At least a portion of the first conductive connection portion is located on a side of the second electrode plate facing away from the substrate, and the first conductive connection portion is coupled to the second electrode plate and the second electrode of the driving transistor respectively through a via structure; At least a portion of the second electrode of the sensing transistor is located on a side of the first conductive connection portion facing away from the substrate, and the second electrode of the sensing transistor is coupled to the first conductive connection portion.

2. The display panel according to claim 1, characterized in that: The second electrode of the driving transistor is located on a side of the gate of the driving transistor facing the substrate, and at least a part of the orthographic projection of the second electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate; The via structure includes a first via and a second via that are connected to each other, the first conductive connection portion is coupled to the second electrode plate through the second via, and the first conductive connection portion is coupled to the second electrode of the driving transistor through the second via and the first via.

3. The display panel according to claim 1, characterized in that: The first conductive connection portion includes a first conductive portion and a second conductive portion coupled to each other, the first conductive portion is located in the via structure, and the first conductive portion is coupled to the second electrode plate and the second electrode of the driving transistor respectively, and the second conductive portion is located outside the via structure, and the second conductive portion is coupled to the second electrode of the sensing transistor.

4. The display panel according to claim 3, characterized in that: The sub-pixel driving circuit further includes a first planar layer, wherein the first planar layer is located in the via structure and located on a side of the first conductive portion facing away from the substrate; The sub-pixel driving circuit further includes a second conductive connection portion, the second conductive connection portion covers the first planar layer and contacts the second conductive portion; At least a portion of the second electrode of the sensing transistor is located on a side of the second conductive connection portion facing away from the substrate, and is coupled to the second conductive connection portion.

5. The display panel according to claim 4, characterized in that: The orthographic projection of the second conductive portion on the substrate surrounds the orthographic projection of the first conductive portion on the substrate; The orthographic projection of the second conductive portion on the base substrate is located inside the orthographic projection of the second conductive connecting portion on the base substrate.

6. The display panel according to claim 4, characterized in that: At least a portion of a second electrode of the sensing transistor contacts a side surface of the second conductive connection portion and a side surface of the second conductive portion.

7. The display panel according to claim 4, characterized in that: The sub-pixel driving circuit also includes a third conductive connection portion, at least a portion of which is located on the side of the second electrode of the sensing transistor that is away from the substrate, and the third conductive connection portion is respectively coupled to the second conductive connection portion, the second electrode of the sensing transistor, and the anode of the light-emitting element.

8. The display panel according to claim 3, characterized in that: The sub-pixel driving circuit also includes a third conductive connection portion, at least a portion of which is located on the side of the second electrode of the sensing transistor that is away from the substrate, and the third conductive connection portion is respectively coupled to the second conductive portion, the second electrode of the sensing transistor, and the anode of the light-emitting element.

9. The display panel according to any one of claims 1 to 8, characterized in that: The sub-pixel driving circuit also includes a compensation electrode layer and a data writing transistor, wherein the compensation electrode layer is located on the side of the second pole of the data writing transistor facing away from the base substrate, and the compensation electrode layer is coupled to the second pole of the data writing transistor through a third via hole; the compensation electrode layer is also coupled to the gate of the driving transistor; the orthographic projection of the compensation electrode layer on the base substrate at least partially overlaps with the orthographic projection of the second pole on the base substrate.

10. The display panel according to claim 9, characterized in that: At least a portion of the compensation electrode layer is located on a side of the gate of the driving transistor facing away from the substrate, and the compensation electrode layer is directly overlapped with the gate of the driving transistor.

11. The display panel according to claim 9, characterized in that: The display panel comprises a first gate metal layer and a second gate metal layer which are sequentially stacked in a direction away from the base substrate; The gate of the driving transistor is provided in the same layer and material as the first gate metal layer, the second electrode is provided in the same layer and material as the second gate metal layer, and at least part of the compensation electrode layer is located between the first gate metal layer and the second gate metal layer.

12. The display panel according to claim 9, characterized in that: The compensation electrode layer includes an indium tin oxide layer or a metal layer.

13. The display panel according to any one of claims 1 to 8, characterized in that: The sub-pixel driving circuit also includes a fourth conductive connection portion and a data writing transistor, wherein the fourth conductive connection portion is coupled to the gate of the driving transistor and the second electrode of the data writing transistor respectively; the fourth conductive connection portion is arranged in the same layer and material as the first conductive connection portion.

14. The display panel according to any one of claims 1 to 8, characterized in that: The sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor is coupled to a corresponding scanning line, a first electrode of the data writing transistor is coupled to a corresponding data line, and a second electrode of the data writing transistor is coupled to a gate of the driving transistor; The gate of the sensing transistor is coupled to the corresponding scan line, and the first electrode of the sensing transistor is coupled to the sensing line; The first electrode of the driving transistor is coupled to the corresponding power line, and the second electrode of the driving transistor is also coupled to the anode of the light emitting element; The data writing transistor and the driving transistor are low temperature polysilicon transistors, and the sensing transistor is an oxide transistor.

15. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 14.

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