Impedance tuning utility for vector space defined by number of transmission lines

Abstract

Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool. In one embodiment, the method includes measuring a voltage and a current of a transmission line; converting the analog voltage signal and the analog current signal into a digital voltage signal and a digital current signal; calculating a u vector from the digital voltage signal and the digital current signal; the C1 position of the first capacitor is calculated using the real component of the u vector, and the C2 position of the second capacitor is calculated using the imaginary component of the u vector.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 737,677, filed on May 5, 2022, the entire contents of which are hereby incorporated by reference herein. Technical Field

[0003] Embodiments relate to the field of semiconductor manufacturing, and in particular, to a semiconductor processing tool configured to provide impedance tuning with transmission line optimization. Background Art

[0004] In a plasma processing tool, a plasma is ignited by a cathode coupled to a process gas within a chamber. In most tools, a power source is coupled to the cathode via an impedance matching network (sometimes simply referred to as a "match"). The match allows the impedance of the system to be adjusted to match the impedance of the load to which the cathode is coupled. The load has a wide range of impedances determined by parameters such as process conditions, chamber architecture, and the like. In order to provide efficient power transfer from the power source to the load, it is important to match the impedance.

[0005] Impedance tuning algorithms are typically heuristic search algorithms or model-based algorithms. Heuristic search is a guided search and is not always guaranteed to converge to a tuned solution. Model-based solutions are computationally complex. In addition, the efficiency of the tuning process is predicted based on the accuracy of the model 4887P1354l and appropriate gain scheduling to accelerate convergence. Scaling is also problematic because such algorithms need to be customized for each impedance matching design. Further, the operational intensive aspects of such algorithms make such algorithms difficult to deploy in high volume manufacturing (HVM) environments. Summary of the invention

[0006] Embodiments disclosed herein include a method for performing impedance tuning in a semiconductor processing tool. In one embodiment, the method includes measuring a voltage and a current of a transmission line; converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal; calculating a u vector from the digital voltage signal and the digital current signal; calculating a C1 position of a first capacitor using a real component of the u vector; and calculating a C2 position of a second capacitor using an imaginary component of the u vector.

[0007] Embodiments may also include a semiconductor processing tool. In one embodiment, the semiconductor processing tool includes a power supply; an impedance matching network, the impedance matching network including a first capacitor and a second capacitor; a cathode; a power processing module; and a sensor for measuring values ​​including an incident voltage, an incident current, a reflected voltage, and a reflected current, and wherein the measured values ​​are used by the power processing module to adjust the impedance of the impedance matching network.

[0008] Embodiments may also include a method of performing impedance tuning in a semiconductor processing tool. In one embodiment, the method may include measuring a voltage and a current of a transmission line, wherein the voltage includes an incident voltage and a reflected voltage, and wherein the current includes an incident current and a reflected current; converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal; calculating a u vector from the digital voltage signal and the digital current signal, wherein the u vector is a three-element vector; calculating a C1 position of a first capacitor using a real component of the u vector, and calculating a C2 position of a second capacitor using an imaginary component of the u vector, and wherein the three elements of the u vector are oriented in an impedance tuning space to match an output load condition of a semiconductor processing tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a plasma processing tool including a centralized control architecture according to one embodiment.

[0010] Figure 2 is a plan view illustration of a sensor having a current loop, a voltage ring, and a guard ring according to an embodiment.

[0011] Figure 3 is a schematic diagram of a transmission line with sensors for detecting reflected voltage and current as well as incident voltage and current according to an embodiment.

[0012] Figure 4 is a process flow diagram of a process for performing impedance tuning in a semiconductor processing tool according to one embodiment.

[0013] Figure 5 A block diagram illustrates an exemplary computer system that may be used in conjunction with a processing tool according to an embodiment. DETAILED DESCRIPTION

[0014] The system described herein includes sensors for measuring voltage and current in semiconductor tools. In the following description, many specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments can be practiced without these specific details. In other cases, in order not to unnecessarily obscure the embodiments, well-known aspects are not described in detail. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0015] As described above, currently existing tuning algorithms (e.g., heuristic-based search and model-based search) have limitations that make such algorithms unsuitable for HVM environments. Accordingly, embodiments disclosed herein include using the number of transmission lines to construct a vector space for tuning the impedance of a system. For example, a u-vector with up to three elements can be used to create a vector field with no overlapping quadrant representations in order to optimize transmission line parameters for optimal power transfer from the input to the output of an impedance tuning device. Such a three-element vector approach is not computationally cumbersome and allows real-time control of the system in an HVM environment.

[0016] In addition, embodiments are highly scalable. For example, there are no restrictions on impedance matching network topologies or variants. Gain scheduling is also not required. Control of gain is derived from controlling the reactance of the surface (e.g., control of the variable capacitor). In addition, there are no restrictions on impedance matching architectures. That is, mechanical or solid-state variable capacitors can be used according to various embodiments.

[0017] Reference now Figure 1 , a more detailed schematic diagram of a plasma processing tool 100 is shown according to one embodiment. In one embodiment, the plasma processing tool 100 includes a plasma chamber 120. The plasma chamber 120 includes a cathode 122 to couple the received power to one or more gases flowing into the plasma chamber 120. In one embodiment, the plasma chamber 120 can be suitable for any typical plasma process of a semiconductor manufacturing environment. For example, the plasma chamber 120 can be a plasma etching chamber, a plasma deposition chamber, a plasma processing (treatment) chamber, or the like. In a specific embodiment, the plasma chamber 120 can be a plasma enhanced chemical vapor deposition (PECVD) chamber, a physical vapor deposition (PVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber.

[0018] In one embodiment, the plasma chamber 120 may be coupled to a power delivery architecture. For example, the power delivery architecture may include one or more power supplies 132 1 Up to 132 n In the illustrated embodiment, multiple power supplies 132 are shown. However, it should be understood that in some embodiments, a single power supply 132 may be used. In one embodiment, the power supply 132 may include any type of power supply. For example, the power supply 132 may be an RF power supply, a microwave power supply, a direct current (DC) power supply, a pulsed DC power supply, or the like, or any combination of these power supply types.

[0019] In one embodiment, the power source 132 may be coupled to the cathode 122 via an impedance matching network 130. The impedance matching network 130 changes the impedance of the power delivery architecture to match the load in the chamber 120. The impedance of the load may change due to changes in processing conditions (e.g., gas flow rate, pressure, temperature, etc.). As such, the impedance matching network 130 is used to match the changing impedance in order to provide efficient power delivery (i.e., no or minimal reflected power) into the chamber.

[0020] In one embodiment, sensors 151 and 152 may be provided at opposite ends of the impedance matching network 130. For example, sensor 151 1 Up to 151 n The sensor 152 may be on the upstream side of the impedance matching network 130, and the sensor 152 may be on the downstream side of the impedance matching network 130. The "upstream" side may refer to the input side of the matching network 130, and the "downstream" side may refer to the output side of the matching network 130. As shown, multiple sensors 151 1 Up to 151 n is provided on the upstream side of the impedance matching network 130. The number of sensors 151 may be equal to the number of power sources 132. That is, each power source 132 may have a dedicated sensor 151. The downstream side of the impedance matching network 130 may have a single sensor 152. However, it should be understood that when there is more than one output from the matching network 130, there may be additional sensors 152. For example, where there are two outputs (e.g., for the center of the chamber 120 and the edge of the chamber 120), there may be two sensors 152.

[0021] In the case of multiple sensors 151, multiple sensors 151 1 Up to 151 nCan be manufactured on a single PCB. That is, a single module can include multiple sensors. Generally, the embodiments described herein include electrical shielding techniques that limit cross coupling between sensors on a single PCB.

[0022] exist Figure 1 , sensors 151 and 152 are generally illustrated as blocks. However, it should be understood that sensors 151 and 152 can be similar to any of the sensor architectures described in more detail below. For example, each sensor 151 and / or 152 can be a transmission line voltage and transmission line current (i.e., V / I) sensor. The transmission line voltage can be detected by an embedded voltage loop, and the transmission line current can be detected by a current loop. In a specific embodiment, the sensor includes an aperture and a conductive device having a concentric electrically insulating material (e.g., an RF cable) passes through the aperture. Features on the sensor are capable of picking up current and voltage transmitted along the transmission line. For example, the current loop picks up current, and the voltage loop detects voltage.

[0023] In one embodiment, sensors 151 and 152 may be communicatively coupled to process power control module 134. For example, Figure 1 134. However, it should be understood that the processing module may be a microwave process power control module 134, a DC process power control module 134, or the like, depending on what type of power supply 132 is included in the tool 100. In one embodiment, sensors 151 and 152 deliver voltage and / or current to the process power control module. In one embodiment, the process power control module 134 may have external connections for different physical layers and protocols, such as Ethernet (ENET) and standardized industrial connections, such as EtherCAT.

[0024] In one embodiment, the process power control module 134 may be coupled to the impedance matching network via a digital / analog link. Via the digital / analog link, the process power control module 134 may be able to send a control signal to the impedance matching network 130. For example, the control signal may be used to adjust the capacitance of a variable capacitor within the impedance matching network 130. Additionally, the process power control module 134 may be coupled to the power supply 132 via a digital / analog link. As such, the process power control module 134 may be able to coordinate impedance tuning.

[0025] Reference now Figure 2, according to one embodiment, a plan view illustration of a sensor 250 is shown. As shown, the sensor 250 is fabricated on a PCB 253. The sensor 250 may include a current loop 254 and a voltage loop 265 within the current loop 254. The current loop 254 and the voltage loop 265 may surround an aperture 260 passing through the PCB 253.

[0026] In one embodiment, the current loop 254 may include an internal via 255 B and external vias 255 A The vias 255 may be coupled to each other through traces 256 on the top surface of the PCB 253 and through traces 257 on the bottom surface of the PCB 253. In the illustrated embodiment, the current loop 254 includes a pair of windings around the aperture 260.

[0027] In one embodiment, the voltage ring 265 may include an inner conductive ring 266 and an outer conductive ring 268. An insulating ring 267 may be provided between the inner ring 266 and the outer ring 268. The inner ring 266 may be a voltage pickup surface and the outer ring 268 may be grounded. In one embodiment, the inner ring 266 may define the outer perimeter of the aperture 260.

[0028] In one embodiment, the sensor 250 may further include a guard ring 270 around the outer perimeter of the current loop 254. In one embodiment, the guard ring 270 may be grounded. The guard ring 270 may include vias (not shown) that couple the guard ring 270 to a ring of similar size and shape on the bottom side of the PCB 253. As such, an electrical shielding barrier is provided around the pickup component of the sensor 250. Accordingly, sensor performance may be improved.

[0029] In one embodiment, the voltage ring 265 can be coupled to the pick-up circuitry 281 on the PCB 253 . Figure 2 The pickup circuit system 281 in is schematically shown as a dashed box. However, it should be understood that the pickup circuit system 281 may include features such as filters, amplifiers, and the like. In one embodiment, a pad 283 is provided. The pad 283 may be suitable for attaching a connector (not shown) to feed voltage information back to a processing module, such as the processing module described in more detail above.

[0030] In one embodiment, the current loop 254 may be coupled to the pick-up circuitry 282 on the PCB 253 . Figure 2The pickup circuit system 282 in is schematically shown as a dashed box. However, it should be understood that the pickup circuit system 282 may include features such as filters, amplifiers, and the like. In one embodiment, a solder pad 284 is provided. The solder pad 284 may be suitable for attaching a connector (not shown) to feed the current information back to a processing module, such as the processing module described in more detail above.

[0031] In one embodiment, the pickup circuit system 281 is electrically isolated from the pickup circuit system 282. Electrically isolating the two sets of pickup circuit systems 281 and 282 enables the cross coupling between the two circuits to be reduced. In this way, the performance of the sensor 250 can be improved. In one embodiment, the electrical isolation can be provided by a conductive strip 285 provided between the two sets of pickup circuit systems 281 and 282. In one embodiment, the conductive strip 285 can be grounded. In some embodiments, the conductive strip 285 is electrically coupled to the guard ring 270. The conductive strip 285 can be provided on the top surface of the PCB 253. In other embodiments, a via can be provided below the strip 285 so that the electrical isolation extends through the thickness of the PCB 253.

[0032] Reference now Figure 3 , according to one embodiment, a schematic diagram of a transmission line 361 between a power source 332 and a system load 333 is shown. In one embodiment, the power source 332 can be similar to any of the power sources in the power source 132 described in more detail above. For example, in some embodiments, the power source 332 can be an RF power source. In one embodiment, the load 333 can be a load of a plasma processing chamber. For example, the cathode can be coupled to a processing gas in a plasma chamber. The chamber conditions can determine the load of the transmission line 361. That is, changes in pressure, temperature, gas flow rate, etc. can cause changes in the load 333 of the transmission line 361. In order to provide efficient power delivery, an impedance matching network (not shown) matches the impedance of the transmission line 361 to the impedance of the load 333.

[0033] In one embodiment, the transmission line 361 may include a transmission line sensor 340. The transmission line sensor 340 may be substantially similar to the sensor 250 described in more detail above. For example, the transmission line sensor 340 may have a magnetic field coupling component 351 and a capacitive coupling component 352. The magnetic field coupling component 351 may be a current loop, and the capacitive coupling component 352 may be a voltage loop, such as those described in more detail above. The magnetic field coupling component 351 may provide a measured current I m , and the capacitive coupling component 352 can provide the measured voltage V m In one embodiment, the measured current I m The incident current I iand the reflected current I r , and the measured voltage V m The incident voltage V i and the reflected voltage V r The measured current I m and the measured voltage V m can be transmitted to a power processing module (not shown). The power processing module can be communicatively coupled to the impedance matching network. As such, the power processing module can use the measured voltage V m and the measured current I m To set the appropriate impedance of the impedance matching network.

[0034] Reference now Figure 4 , a process flow diagram of a process 480 for tuning the impedance of a semiconductor processing tool (such as a plasma processing tool) is shown, according to an embodiment. In an embodiment, the process 480 can be performed on a power processing module, such as a process power control module described in more detail above. The process 480 can result in the identification of the impedance of a load (e.g., a plasma load) and is configured to set the positioning of a first variable capacitor and a second variable capacitor in an impedance matching network to match the impedance of a transmission line to the impedance of the load.

[0035] In one embodiment, process 480 begins at operation 481, which includes measuring a voltage and a current of a transmission line. In one embodiment, the measured voltage and the measured current may include both an incident portion and a reflected portion. For example, the measured voltage may include a reflected voltage (V r ) and the incident voltage (V i ). Similarly, the measured current may include the reflected current (I r ) and the incident current (I i ).

[0036] The measured current and the measured voltage can be detected by a sensor (such as sensor 250 described in more detail above). For example, one or more sensors may include a current loop and a voltage loop. In one embodiment, the sensor is positioned along a transmission line between a power source and a load (e.g., a plasma load). In some embodiments, one or more sensors are located before an impedance matching network, after an impedance matching network, and / or before and after an impedance matching network. Although described herein as a single sensor, it should be understood that multiple sensors may be used according to various embodiments described herein.

[0037] In one embodiment, process 480 may continue with operation 482, which includes converting the analog voltage signal and the analog current signal into a digital voltage signal and a digital current signal. The conversion from analog to digital may be implemented in a power processing module (e.g., similar to the RF process power control module described above). For example, the conversion may be performed using an analog to digital converter (ADC) or the like.

[0038] In one embodiment, process 480 may continue with operation 483, which includes calculating a u-vector having three elements from the digital voltage signal and the digital current signal. In one embodiment, the three elements of the u-vector may be calculated using equations 1-3.

[0039]

[0040]

[0041] In one embodiment, process 480 may continue with operation 484, which includes calculating C1 position using the real component of the u vector. C1 position is the position of the first variable capacitor within the impedance matching network. Although referred to as having a "position", it should be understood that the first variable capacitor may be a solid-state capacitor and there may not be a mechanical positioning for setting the capacitance of the first variable capacitor. In one embodiment, the C1 position may be calculated using Equation 4.

[0042]

[0043] In Equation 4, α is the gain value, is the real-valued component of the u vector, d is a second vector that provides a linear combination of the u vector and the angular rotation component via a dot product, and is the transpose of the u vector. In one embodiment, α takes a value corresponding to the reactance range of the first variable capacitor.

[0044] In one embodiment, process 480 may continue with operation 485, which includes calculating C2 position using the imaginary component of the u vector. C2 position is the position of the second variable capacitor in the impedance matching network. Although referred to as having a "position", it should be understood that the second variable capacitor may be a solid-state capacitor and there may not be a mechanical positioning for setting the capacitance of the second variable capacitor. In one embodiment, the C2 position may be calculated using Equation 5.

[0045]

[0046] In Equation 4, β is the gain value, is the imaginary component of the u vector, d is a second vector that provides a linear combination of the u vector and the angular rotation component via a dot product, and is the transpose of the u vector. In one embodiment, β takes a value corresponding to the reactance range of the second variable capacitor. Typically, is the ratio of the range of C1 to the range of C2. In one embodiment, appropriate C1 and C2 positioning minimizes the element of u, and as any numerator term u→0, a tuned condition emerges for optimal power transfer from input to output.

[0047] It should be understood that a vector u of up to three elements results in a vector field being formed without overlapping quadrant representations so as to optimize the transmission line parameters to achieve optimal power transfer from the input to the output of the impedance tuning device. In addition, the computational burden of such a method is significantly lower than other tuning algorithms (e.g., heuristic search algorithms and model-based algorithms). Accordingly, embodiments (such as those described herein) allow for calculation and operation in a real-time control system. In addition, such embodiments are easily scalable and are not limited to a single architecture. For example, there is no restriction on the impedance matching network topology or variant. In addition, gain scheduling is not required. Instead, the control gain is derived from the reactance of the control surface. In yet another embodiment, it should be understood that there is no restriction on the impedance mathematical type. For example, according to various embodiments, mechanical or solid-state variable capacitors can be used in the impedance matching network.

[0048] Reference now Figure 5, a block diagram of an exemplary computer system 500 of a processing tool is illustrated according to an embodiment. In one embodiment, the computer system 500 is coupled to the processing tool and controls the processing in the processing tool. The computer system 500 can be connected (e.g., networked) to other machines in a local area network (Local Area Network, LAN), an intranet, an extranet, or the Internet. The computer system 500 can operate with the capacity (capacity) of a server or client machine in a client-server network environment, or as a peer machine operation in a peer (or distributed) network environment. The computer system 500 can be a personal computer (personal computer, PC), a tablet PC, a set-top box (set-top box, STB), a personal digital assistant (Personal Digital Assistant, PDA), a cellular phone, a network device, a server, a network router, a switch or a bridge, or any machine that can execute a set of instructions (sequential or otherwise) specifying the action to be taken by the machine. Further, while only a single machine is illustrated with respect to computer system 500, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

[0049] The computer system 500 may include a computer program product or software 522 having a non-transitory machine-readable medium having instructions stored on the non-transitory machine-readable medium, the instructions being used to program the computer system 500 (or other electronic device) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read only memory (read only memory; "ROM"), random access memory (random access memory; "RAM"), magnetic disk storage medium, optical storage medium, flash memory device, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustic or other form of propagation signal (e.g., infrared signal, digital signal, etc.)), etc.

[0050] In one embodiment, the computer system 500 includes a system processor 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and an auxiliary memory 518 (e.g., a data storage device), which communicate with each other via a bus 530.

[0051] The system processor 502 represents one or more general-purpose processing devices, such as a microsystem processor, a central processing unit, or the like. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor implementing other instruction sets, or a system processor implementing a combination of instruction sets. The system processor 502 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, or the like. The system processor 502 is configured to execute processing logic 526 to perform the operations described herein.

[0052] The computer system 500 may further include a system network interface device 508 for communicating with other devices or machines. The computer system 500 may also include a video display unit 510 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), and a signal generating device 516 (e.g., a speaker).

[0053] The secondary memory 518 may include a machine-accessible storage medium 532 (or more specifically, a computer-readable storage medium) having stored thereon one or more sets of instructions (e.g., software 522) embodying any one or more of the methods or functions described herein. The software 522 may also reside, in whole or in part, within the main memory 504 and / or the system processor 502 during execution by the computer system 500, the main memory 504 and the system processor 502 also constituting machine-readable storage media. The software 522 may further be sent or received over the network 520 via the system network interface device 508. In one embodiment, the network interface device 508 may operate using RF coupling, optical coupling, acoustic coupling, or inductive coupling.

[0054] Although the machine-accessible storage medium 532 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods. Accordingly, the term "machine-readable storage medium" should be taken to include, but is not limited to, solid-state memories and optical and magnetic media.

[0055] In the foregoing description, specific exemplary embodiments have been described. It will be apparent that various modifications may be made to the embodiments without departing from the scope of the appended claims. Accordingly, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for impedance tuning in a semiconductor processing tool, comprising the steps of: Measure voltage and current on transmission lines; Converting analog voltage signals and analog current signals into digital voltage signals and digital current signals; Calculate a u vector from the digital voltage signal and the digital current signal; The real component of the u vector is used to calculate the position of the first capacitor C1, and The imaginary component of the u vector is used to calculate the position of the second capacitor C2. The method according to claim 1 , wherein the u vector is a vector of three elements.

3. The method of claim 2, wherein the three elements of the u-vector are oriented within an impedance tuning space to match output load conditions of the semiconductor processing tool. 4 . The method of claim 1 , wherein the voltage comprises an incident voltage and a reflected voltage, and wherein the current comprises an incident current and a reflected current. The method of claim 1 , wherein C1 and C2 are positioned to minimize those elements of the u vector to drive the u vector to zero. The method of claim 5 , wherein making the u-vector equal to zero is a tuned condition of the tool.

7. The method of claim 1, wherein calculating the C1 and C2 positions comprises taking the dot product of the u vector and d vector. The method of claim 7 , wherein the d-vector includes an angular rotation component.

9. The method of claim 1, wherein the first capacitor and the second capacitor are within a matching network.

10. The method of claim 1, wherein the semiconductor processing tool is a plasma processing tool.

11. The method of claim 1, wherein the semiconductor processing tool comprises a power supply, a matching network, and a cathode, and wherein sensors for measuring the voltage and the current of the transmission line are provided on opposite ends of the matching network.

12. A semiconductor processing tool comprising: power supply; an impedance matching network, the impedance matching network comprising a first capacitor and a second capacitor; cathode; Power processing module; and A sensor is provided for measuring values ​​including an incident voltage, an incident current, a reflected voltage, and a reflected current, and wherein the measured values ​​are used by the power processing module to adjust the impedance of the impedance matching network.

13. The semiconductor processing tool of claim 12, wherein the sensor comprises a current loop and a voltage loop.

14. The semiconductor processing tool of claim 12, wherein the measured values ​​are used to form a three-element u-vector.

15. The semiconductor processing tool of claim 14, wherein the tuned positions of the first and second capacitors are found using a dot product of the three-element u-vector and a d-vector having angularly rotated elements.

16. The semiconductor processing tool of claim 12, wherein the semiconductor processing tool is a plasma processing chamber.

17. The semiconductor processing tool of claim 12, wherein the first capacitor and the second capacitor are variable solid-state capacitors and / or variable mechanical capacitors.

18. A method of performing impedance tuning in a semiconductor processing tool, comprising the steps of: measuring a voltage and a current of a transmission line, wherein the voltage comprises an incident voltage and a reflected voltage, and wherein the current comprises an incident current and a reflected current; Converting analog voltage signals and analog current signals into digital voltage signals and digital current signals; Calculate a u vector from the digital voltage signal and the digital current signal, wherein the u vector is a vector of three elements; Calculating the C1 position of the first capacitor using the real component of the u vector; and The imaginary component of the u-vector is used to calculate a position C2 of a second capacitor, and wherein the three elements of the u-vector are oriented within an impedance tuning space to match an output load condition of the semiconductor processing tool.

19. The method of claim 18, wherein calculating the C1 position and the C2 position comprises taking the dot product of the u vector and the d vector.

20. The method of claim 19, wherein the d-vector includes an angular rotation component.

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