Method and apparatus for etching semiconductor substrate in plasma etch chamber

Abstract

A method and apparatus for etching a substrate in a plasma etch chamber is provided. In one example, the method includes exposing a substrate disposed on a substrate support surface of a substrate support to a plasma within a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support during a plurality of macro etch cycles while exposing the substrate to the plasma. Each macroscopic etch cycle includes a first macroscopic etch period and a second macroscopic etch period. The macro etch cycle includes a plurality of micro etch cycles. Each microscopic etch cycle has a bias power on (BRON) period and a bias power off (BPOFF) period, wherein a duration of the BRON period is less than a duration of the BPOFF period. During the second macroscopic etch period, the bias power is predominantly not applied to the electrodes.

Description

background Technical Field

[0001] Embodiments of the present disclosure generally relate to systems and methods used in semiconductor device manufacturing. More specifically, embodiments provided herein generally include apparatus and methods for etching a semiconductor substrate in a plasma etch chamber. Background Art

[0002] Reliably producing high aspect ratio features is one of the key technical challenges for next generation semiconductor devices. One method of forming high aspect ratio features uses a plasma assisted etching process, such as a reactive ion etching (RIE) plasma process, to form high aspect ratio openings in a material layer (such as a dielectric layer) of a substrate. In a common RIE plasma process, a plasma is formed in a processing chamber and ions from the plasma are accelerated toward a substrate surface to form an opening in a material layer disposed beneath a mask layer formed on the substrate surface.

[0003] A common reactive ion etch (RIE) plasma processing chamber includes a radio frequency (RF) generator that supplies RF power to a power electrode, such as a metal plate positioned adjacent to an "electrostatic chuck" (ESC) assembly, more commonly referred to as a "cathode". The power electrode may be capacitively coupled to the plasma of the processing system through a thick layer of dielectric material (e.g., ceramic material) that is part of the ESC assembly. In a capacitively coupled gas discharge, the plasma is generated by using a radio frequency (RF) generator coupled to the power electrode via an RF matching network ("RF matching"), or a separate power electrode disposed outside the ESC assembly and within the processing chamber, which tunes the apparent load to 50Ω to minimize reflected power and maximize power delivery efficiency.

[0004] In high aspect ratio etch applications, maintaining verticality of etched features often becomes a challenge. Asymmetries in any of the ground return paths, RF power application, pattern density, flow conduction, and substrate charging, among others, often lead to a loss of verticality (also known as tilt) in the sidewalls of the etched features. In some cases, sidewall tilt has an adverse effect on device performance and may even lead to device failure.

[0005] Therefore, there is a need for improved methods and apparatus for plasma etching. Summary of the invention

[0006] A method and apparatus for etching a semiconductor substrate in a plasma etching chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate support surface of a substrate support to a plasma in a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support while exposing the substrate to the plasma during a plurality of macro-etching cycles. Each macro-etching cycle includes a first macro-etching cycle and a second macro-etching cycle. The macro-etching cycle includes a plurality of micro-etching cycles. Each micro-etching cycle has a bias power on (BPON) cycle and a bias power off (BPOFF) cycle, wherein the duration of the BPON cycle is less than the duration of the BPOFF cycle. During the second macro-etching cycle, the bias power is not primarily applied to the electrode.

[0007] In another example, a method for etching a semiconductor substrate in a plasma etching chamber is provided, the method comprising: forming a plasma from a processing gas containing carbon and at least one halogen, exposing a dielectric layer disposed on the semiconductor substrate to the plasma in the plasma etching chamber, and applying a bias power to the semiconductor substrate while being exposed to the plasma during a plurality of macro-etching cycles until an end point is reached. Each macro-etching cycle comprises a first macro-etching cycle and a second macro-etching cycle. The macro-etching cycle comprises a plurality of micro-etching cycles. Each micro-etching cycle has a bias power on period and a bias power off period. The duration of the BPON period is less than the duration of the BPOFF period. During the second macro-etching cycle, the bias power is not primarily applied to the electrode. In at least the macro-etching cycle, the duration of the bias power on period is at least two orders of magnitude less than the duration of the first macro-etching cycle, and the duration of the bias power off period is at least two orders of magnitude less than the duration of the second macro-etching cycle.

[0008] In yet another example, a plasma etching chamber is provided. The plasma etching chamber includes a chamber body having an internal volume, a substrate support disposed in the internal volume of the chamber body, a bias power control system, a gas panel, and a controller. The substrate support is configured to fix a semiconductor substrate on the substrate support during processing. The substrate support has a bias electrode. The bias power control system is coupled to the bias electrode. The gas panel is configured to provide a processing gas to the internal volume. The controller is configured to maintain a plasma formed by the processing gas in the plasma etching chamber, and to apply bias power to the bias electrode while exposing a semiconductor substrate disposed on the substrate support to the plasma during a plurality of macro-etching cycles. Each macro-etching cycle includes a first macro-etching cycle and a second macro-etching cycle. The macro-etching cycle includes a plurality of micro-etching cycles. Each micro-etching cycle has a bias power on cycle and a bias power off cycle. The duration of the BPON cycle is less than the duration of the BPOFF cycle. During the second macro-etching cycle, the bias power is not mainly applied to the electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, a more particular description of the present disclosure briefly summarized above may be made with reference to embodiments, some of which are shown in the accompanying drawings. However, it will be noted that the accompanying drawings only illustrate exemplary embodiments and are therefore not to be considered limiting of the scope thereof, and other equally effective embodiments may be allowed.

[0010] Figure 1 is a flow chart of one example of a method for etching a substrate.

[0011] FIG. 2A to FIG. 2D is an etching process (such as but not limited to reference Figure 1 Partial cross-sectional view of a substrate during various stages of the method described.

[0012] Figure 3 is an example of a bias power timing diagram illustrating a number of macro-etch cycles for reaching an endpoint during performance of a method for etching a substrate.

[0013] Figure 4 is an example of a bias power timing diagram further detailing one macro-etch cycle.

[0014] Figure 5 is a schematic cross-sectional illustration of an exemplary plasma etch chamber configured to practice the methods described herein.

[0015] To facilitate understanding, identical reference numerals have been used, where possible, to identify identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing. More specifically, embodiments provided herein generally include apparatus and methods for etching a substrate in a plasma etching chamber in a manner that reduces the tilt of the vertical sidewalls of the etched features. Such improvements have been achieved by adjusting the waveform of an electrode for applying bias power to a substrate support, which is used to support the substrate during etching in macro and micro schemes. In the macro scheme, multiple macro etching cycles are used to etch the substrate. The waveform includes a cycle in which the bias power is substantially stopped during a portion of each macro etching cycle to allow the discharge of etching byproducts from the plasma etching chamber. By periodically removing the etching byproducts from the chamber, the etchant may be more effectively delivered to the feature being etched in a vertical trajectory. In the micro scheme of the waveform, multiple micro etching cycles are utilized during a portion of each macro etching cycle. Each micro etching cycle includes a first cycle in which the bias power is turned on, and a second cycle in which the bias power is substantially stopped. The duration of the second cycle is greater than the duration of the first cycle to provide time for the etching byproducts to leave the feature being etched (such as a hole, a groove, etc.). By periodically clearing the etch byproducts from the etched features, the etchant may be more effectively delivered to the bottom of the etched features in a vertical trajectory. The reduced number of collisions between the etchant and the etch byproducts enables the etchant to maintain a substantially vertical trajectory in all paths to the bottom of the etched features, thereby advantageously resulting in reduced etching of the sidewalls and thereby resulting in excellent verticality of the sidewalls of the etched features. Enhanced verticality is particularly desirable when forming high aspect ratio features by etching.

[0017] Now go to Figure 1 , a flow chart of an example of a method 100 for etching a substrate is shown. The method 100 may be practiced in a plasma etching chamber, and later in Figure 5 An example of which is depicted in . Method 100 may alternatively be practiced in other suitable plasma processing chambers. FIG. 2A to FIG. 2D Best described, FIG. 2A to FIG. 2D A partial cross-sectional view of a substrate 200 is shown during various stages of an etching method 100. The method 100 can be used to etch features such as vertical vias and trenches. The method 100 is particularly useful when etching high aspect ratio (height to width ratio greater than 10) features, where the verticality of the etched features has a high impact on device performance.

[0018] The method 100 begins at operation 102 by exposing a substrate 200 disposed on a substrate supporting surface of a substrate support to plasma within a plasma etching chamber. Figure 2A, the substrate 200 generally includes a patterned mask 204 disposed on a top surface 210 of a target material 202 to be etched. The mask 204 may be a photoresist, a hard mask, a combination thereof, or other suitable mask. The patterned mask 204 includes an opening 206 that exposes a portion 208 of the top surface 210 of the target material 202 to the plasma in the plasma etching chamber for etching. The substrate 200 may have one or more additional layers (not shown) disposed below the bottom surface 212 of the target material 202.

[0019] In one example, the target material 202 is a dielectric layer. For example, the target material 202 may be an oxide layer. In yet other examples, the target material 202 may be a metal or a semiconductor material.

[0020] In other examples, the target material 202 may include multiple layers. Figure 2A In the embodiment, the target material 202 is included in the second material 202 B The first material 202 is provided on A . First Material 202 A and Secondary Materials 202 B For example, the first material 202 A One of them is an oxide layer or a nitride layer, and the second material 202 B The target material 202 includes a plurality of alternating pairs of oxide and nitride layers.

[0021] The plasma may be formed within the plasma etching chamber, or remotely formed from the plasma etching chamber and delivered to the plasma etching chamber. The plasma is typically formed from a process gas suitable for etching the target material 202. For example, when the target material 202 is a dielectric material, the process gas may include a carbon and halogen containing gas. Examples of suitable carbon and halogen containing gases include C X H Y F Z wherein X, Y, and Z are integers. Other examples of suitable carbon- and halogen-containing gases include C X F Z , where X and Z are integers. In yet other examples, where the target material 202 includes one or more metals, the process gas may include Cl and / or oxygen. In yet other examples, where the target material 202 is silicon, the process gas may include Cl and / or fluorine, such as carbon tetrachloride (CCl4), trifluoromethane (CHF3), etc. In any of the above examples, one or more polymer cleaning gases (such as O2, N2, NF3, etc.) and / or one or more inert gases (such as He, Ar, Kr, etc.) can optionally be provided as part of the process gas.

[0022] At operation 104, while exposing the substrate 200 to the plasma to etch the substrate 200 during a plurality of macro-etching cycles, a voltage waveform is applied to an electrode disposed in the substrate support, such as Figure 2B . Each macro-etching cycle includes a first macro-etching cycle and a second macro-etching cycle. The first macro-etching cycle is generally used to etch a portion 208 of the target material 202 of the substrate 200 exposed through the opening 206 in the patterned mask 204. The duration of each macro-etching cycle can be measured in milliseconds. Within a macro-etching cycle, the first macro-etching cycle is generally longer than the second macro-etching cycle. For example, the first macro-etching cycle can be three times or longer than the second macro-etching cycle.

[0023] During the first macroscopic etching cycle, the voltage waveform includes multiple microscopic etching cycles. The duration of each microscopic etching cycle can be measured in microseconds. Therefore, the duration of the macroscopic etching cycle is usually one order of magnitude greater than the duration of the microscopic etching cycle, for example, 2 to 3 or more orders of magnitude.

[0024] Each micro-etching cycle includes a bias power on period and a bias power off period. During the bias power on period, DC power is applied to an electrode disposed in the substrate support. During the bias power off period, DC power is not primarily applied to the electrode disposed in the substrate support, wherein primarily not applying DC power is defined as not applying DC power from a DC power source coupled to the electrode between zero and 10% of the duration of the bias power off period. In one example, substantially no DC power is applied to the electrode disposed in the substrate support for the entire duration of the bias power off period.

[0025] The DC power applied to the electrode during the bias power on period effectively directs the etchant from the plasma vertically into the feature 224 to etch the exposed portion 208 of the target material 202. Similarly, where DC power is not substantially applied to the electrode during the bias power off period, the target material 202 of the substrate 200 is not etched, thereby allowing the etching byproducts to leave the etched feature 224. Advantageously, since the bias power off period allows the etching byproducts to be substantially removed from the feature 224, the DC power applied in the next bias power on period allows the etchant to be directed vertically to the bottom 220 of the etched feature 224 with a reduced likelihood of collision with the byproducts in the feature 224, thereby resulting in vertically etching the bottom 220 of the feature while less etching the sidewalls 222 of the feature 224. The reduced etching of the sidewalls 222 of the feature 224 advantageously results in a high degree of verticality of the sidewalls 222.

[0026] Similarly during the second macro-etching cycle, DC power is primarily not applied to the electrode disposed in the substrate support, such that DC power from the DC power supply coupled to the electrode is not applied between zero and 10% of the duration of the second macro-etching cycle. In one example, substantially no DC power is applied to the electrode disposed in the substrate support for the entire duration of the second macro-etching cycle.

[0027] As with the bias power off period of the second macro-etch cycle, in which DC power is not primarily applied to the electrodes, the target material 202 of the substrate 200 is also not etched during the second macro-etch cycle. The millisecond duration of the second macro-etch cycle allows etching byproducts that left the etched features 224 during the bias power off period of the previously completed first macro-etch cycle to be removed from the region directly above the substrate 200 and pumped out of the plasma etching chamber. With the etching byproducts removed from the region directly above the substrate 200, the next macro-etch cycle can be performed with a reduced number of collisions between the remaining etching byproducts and the etchant directed into the features 224, thereby further enhancing the verticality of the etched features 224. By comparison, since more time is required to pump the byproducts out of the chamber than to pump the byproducts out of the features 224, the duration of the second macro-etch cycle is 100 to 1000 or more times the duration of the second micro-etch cycle.

[0028] The macro-etching cycle is repeated until the end point is reached at operation 106 when the depth of the etched feature 224 reaches a predefined depth D. Figure 2B As shown in FIG. 1 , the endpoint of the process for etching the target material 202 is at a depth D without damaging the target material 202. The endpoint of the process for etching the target material 202 may be determined by spectroscopy, interferometry, or timed etching techniques, etc., to monitor the plasma composition.

[0029] In some examples, where the target material 202 includes multiple layers (such as in the second material 202 B The first material 202 is provided on A ), the end point depth D may exceed the first material 202 A thickness, but does not damage the second material 202 B , as in Figure 2C In yet other examples, where the target material 202 includes a single layer or multiple layers, when the etched feature 224 destroys the target material 202, a depth D is reached at each end point so that the bottom 220 of the feature 224 is defined by a layer (not shown) below the target material 202, as shown in Figure 2D As shown in .

[0030] Figure 33 is an example of a bias power timing diagram showing a waveform 320 including a bias power timing diagram for performing a method for etching a substrate 200 (such as the method 100 described above or other similar etching processes) at a time (T E ) reaches the end of multiple macro-etching cycles 302. Although not Figure 3 As shown in, but in time (T E ) reaches the end point, for example, at operation 106 described above, the last of the plurality of macro-etching cycles 302 may be terminated. Figure 3 In the bias power timing diagram depicted in FIG. 1 , the vertical axis represents the DC power applied to the electrode disposed in the substrate support, and the horizontal axis represents time. The duration 310 of the entire etching process to reach the end depth D extends from time (T0) to time (T E ) at the end point.

[0031] Each macro-etching cycle 302 typically has a duration of, but is not limited to, 1 to 250 milliseconds. As discussed above, each macro-etching cycle 302 includes a first macro-etching cycle 304 and a second macro-etching cycle 306. Although not required, the first macro-etching cycle 304 occurs before the second macro-etching cycle 306. The first macro-etching cycle 304 has a longer duration than the duration of the second macro-etching cycle 306. In one example, the first macro-etching cycle 304 has a duration of at least 70% of the total duration of the macro-etching cycle 302. In another example, the first macro-etching cycle 304 has a duration of at least 80% of the total duration of the macro-etching cycle 302. In one example, the duration of the second macro-etching cycle 306 is selected to be sufficient to pump out most of the etching byproducts in the processing volume above the substrate support.

[0032] In some examples, the amount of etching byproducts in the processing volume above the substrate support may vary at different times throughout the duration 310 of the etching process. For example, as the etched features 224 become deeper, the amount of etching byproducts in the processing volume above the substrate support per unit time may decrease. Thus, the ratio of the duration of the first macro-etching period 304 to the second macro-etching period 306 may increase during the duration 310, particularly closer to time (T E Alternatively, the second material 202 is etched B In contrast, etching the first material 202 A The ratio of the duration of the first macro-etching period 304 to the second macro-etching period 306 may be different.

[0033] The frequency of the macro-etching cycle 302 is typically in the range of single to hundreds of Hz. For example, the frequency of the macro-etching cycle 302 can be, but is not limited to, about 5 Hz to about 100 Hz. The frequency of the macro-etching cycle 302 can be constant or vary throughout the duration 310 for etching the feature 224. For example, with the waveform 320 closer to T E The frequency of the macro-etch cycles 302 may be higher during the portion of the waveform 320 closer to T0 than during the portion of the waveform 320 closer to T0. It has been explained that using a lower frequency macro-etch cycle 302 at a deeper depth D improves the verticality of the sidewalls 222 of the etched features 224 by allowing more time for byproducts to be removed from the etching chamber between active etching of the target material 202. Alternatively, the frequency of the macro-etch cycles 302 may be higher or lower at different portions of the duration 310 of the etching method 100.

[0034] As in Figure 3 As shown in FIG. 3 , during the second macro-etch cycle 306 , DC power is primarily not applied to the electrodes of the substrate support.

[0035] Referring back to the first macro-etching cycle 304, the first macro-etching cycle 304 includes a time when DC power is applied to an electrode disposed in a substrate support that supports a substrate within a plasma etching chamber. If the target material 202 generally occurs when DC power is applied to the electrode and does not occur when DC power is not applied to the electrode, etching is performed. DC power is cyclically applied to the electrode during the first macro-etching cycle 304, as described below with reference to Figure 4 Further described.

[0036] Figure 4 is an example of a bias power timing diagram further detailing a macro etch cycle 302. Figure 4 , the vertical axis represents the DC power applied to the electrode disposed in the substrate support, and the horizontal axis represents time. Each macro-etching cycle 302 (one of which is Figure 4 ) includes a single first macro-etching cycle 304 and a single second macro-etching cycle 306. Each first macro-etching cycle 304 includes a plurality of micro-etching cycles 402. Each micro-etching cycle 402 includes a first micro-etching cycle 404 and a second micro-etching cycle 406.

[0037] As described above, the first macro-etch cycles 304 are generally used to etch the portions 208 of the target material 202 of the substrate 200 that are exposed through the openings 206 in the patterned mask 204. To achieve etching during each first macro-etch cycle 304, bias power is provided to the electrodes of the substrate support during each of the first macro-etch cycles 404. Since the duration of the first micro-etch cycles 404 is measured in milliseconds, the bias power is applied to the electrodes of the substrate support for many first micro-etch cycles 404 that each include the first macro-etch cycle 304 to effectively etch the target material 202.

[0038] The frequency of the bias power on period (e.g., DC power pulse) of the micro-etching cycle 402 is typically in the range of single to hundreds of kHz. For example, the frequency of the micro-etching cycle 402 can be, but is not limited to, about 25 kHz to about 600 kHz, such as 25 kHz to about 500 kHz. The frequency of the micro-etching cycle 402 can be constant or change over the duration of the macro-etching cycle 302, and / or can be constant or change over the duration 310 of the etching feature 224. For example, waveform 320 is closer to T E The frequency of the micro-etch cycles 402 may be higher during the portion of the waveform 320 closer to T0 than during the portion of the waveform 320 closer to T0. It has been explained that using a lower frequency of the micro-etch cycles 402 at a deeper depth D improves the verticality of the sidewalls 222 of the etched features 224 by allowing more time for byproducts to escape the high aspect ratio features 224 between active etching of the target material 202 during each first micro-etch cycle 404. Alternatively, the frequency of the micro-etch cycles 402 may be higher or lower at different portions of the duration 310 of the etching method 100 to suit other requirements.

[0039] During the micro-etching cycle 402, the voltage waveform 320 includes a first micro-etching period 404 and a second micro-etching period 406. The first micro-etching period 404 corresponds to a bias power on period, and the second micro-etching period 406 corresponds to a bias power off period. During the bias power on period of the first micro-etching period 404, DC power is applied to an electrode disposed in the substrate support. During the bias power off period of the second micro-etching period 406, DC power is not primarily applied to the electrode disposed in the substrate support, wherein primarily not applying DC power is defined as not applying DC power from a DC power source coupled to the electrode between zero and 10% of the duration of the bias power off period. In one example, substantially no DC power is applied to the electrode disposed in the substrate support for the entire duration of the bias power off period.

[0040] Thus, where DC power is applied to the electrode during the first micro-etch cycle 404, the portion 208 of the target material 202 of the substrate 200 exposed through the opening 206 is effectively etched as the bias power directs the etchant from the plasma into the feature 224 being etched in the target material 202. Similarly, where DC power is not primarily applied to the electrode during the second micro-etch cycle 406, the target material 202 of the substrate 200 is not etched, thus allowing the etching byproducts to leave the etched feature 224. Advantageously, since the second micro-etch cycle 406 (i.e., the bias power is off) allows the etching byproducts to be substantially removed from the feature 224, the DC power applied in the next first micro-etch cycle 404 allows the etchant to be directed vertically to the bottom 220 of the etched feature 224 with a reduced likelihood of collision with the byproducts in the feature 224. The reduction in byproduct collisions results in the bottom 220 of the feature being etched vertically, while the sidewalls 222 of the feature 224 are less etched. The reduced etching of sidewalls 222 of features 224 advantageously results in a high verticality of sidewalls 222 .

[0041] Similar to the second macro-etching cycle 306, DC power is not primarily applied to the electrode disposed in the substrate support during the second micro-etching cycle 406. DC power from the DC power supply is primarily not applied to the electrode when DC power is not applied between zero and 90% of the duration of the second micro-etching cycle 406. In one example, substantially no DC power is applied to the electrode disposed in the substrate support for the entire duration of the second micro-etching cycle 406.

[0042] Providing sufficient time to remove byproducts from the feature 224 enhances the ability to achieve a very vertical sidewall 222. Therefore, the first micro-etching cycle 404 has a duration that is generally less than the duration of the second micro-etching cycle 406. In one example, the first micro-etching cycle 404 has a duration that is generally less than 45% (e.g., less than 30%) of the duration of the micro-etching cycle 402. In another example, the first micro-etching cycle 404 has a duration that is generally about 10 to about 45% (e.g., less than 10 to about 15%) of the duration of the micro-etching cycle 402. In addition, because the time required to clear the feature 224 of the etching byproducts may be different at different micro-etching cycles 404 within the same first macro-etching cycle 304, or between different first macro-etching cycles 304, the ratio of the duration of the first micro-etching cycle 404 to the second micro-etching cycle 406 may decrease, increase, or be constant during the duration 410 of the etching method 100, particularly closer to time (T E Alternatively, when etching the second material 202 B In contrast, etching the first material 202A In the embodiment of the present invention, the ratio of the duration of the first micro-etching cycle 404 to the duration of the second micro-etching cycle 406 may be different. In addition to or in lieu of adjusting the duration ratio between the first micro-etching cycle 404 and the second micro-etching cycle 406, the power applied to the bias electrode for etching the feature 224 in the target material 202 may be different at different micro-etching cycles 402 within the same first macro-etching cycle 304, or between different first macro-etching cycles 304. For example, over the duration 310 of the etching method 100, the power used during different micro-etching cycles 402 may be reduced, increased, or adjusted within the same first macro-etching cycle 304 and / or within different first macro-etching cycles 304. As an example, the power applied to the bias electrode during the first micro-etching cycle 404 for etching the first material 202a may be different from the power during the first micro-etching cycle 404 for etching the second material 202b.

[0043] Figure 5 is a schematic cross-sectional view of an exemplary plasma etch chamber 510 configured to practice the methods described above (such as method 100, etc.). In some embodiments, the plasma etch chamber 510 is configured for use in a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process. The plasma etch chamber 510 may also be used in other plasma-assisted processes, such as a plasma-enhanced deposition process (e.g., a plasma-enhanced chemical vapor deposition (PECVD) process, a plasma-enhanced physical vapor deposition (PEPVD) process, a plasma-enhanced atomic layer deposition (PEALD) process), a plasma machining process, a plasma-based ion implantation process, or a plasma doping (PLAD) process. In one configuration, as Figure 5 As shown, the plasma etching chamber 510 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, the plasma may alternatively be generated by an inductively coupled source disposed above the processing region of the plasma etching chamber 510. In this configuration, the coil may be placed on top of the ceramic lid (vacuum boundary) of the plasma etching chamber 510. It is also contemplated that the method 100 described above may be practiced in other types of plasma etching chambers.

[0044] The plasma etching chamber 510 includes a chamber body 513, a substrate support assembly 536, a gas panel 582, a DC power system 583, an RF power system 589, and a system controller 526. The chamber body 513 includes a chamber lid 523, one or more sidewalls 522, and a chamber base 524. The chamber lid 523, one or more sidewalls 522, and the chamber base 524 collectively define a processing volume 529. The substrate 503 is loaded into and removed from the processing volume 529 through an opening (not shown) in one of the sidewalls 522. The substrate 503 is the same as the substrate 200 described above. The opening is sealed with a slit valve (not shown) during plasma processing of the substrate 503.

[0045] A gas panel 582 coupled to a processing volume 529 of a plasma etch chamber 510 includes a process gas panel 519 and a gas inlet 528 disposed through a chamber lid 523. The gas inlet 528 is configured to deliver one or more process gases from the plurality of process gas panels 519 to the processing volume 529. Exemplary process gases have been described above.

[0046] The plasma etching chamber 510 further includes an upper electrode (e.g., chamber lid 523) and a lower electrode (e.g., substrate support assembly 536) disposed in the processing volume 529. The upper electrode and the lower electrode are positioned to face each other. Figure 5 As seen in FIG. 5 , in one embodiment, a radio frequency (RF) source is electrically coupled to the lower electrode. The RF source is configured to deliver an RF signal to ignite and maintain a plasma (e.g., plasma 501) between the upper and lower electrodes. In some alternative configurations, the RF source can also be electrically coupled to the upper electrode. For example, the RF source can be electrically coupled to the chamber lid. In another example, the RF source can also be electrically coupled to the support base 507.

[0047] The substrate support assembly 536 includes a substrate support 505, a substrate support base 507, an insulator plate 511, a ground plate 512, a plurality of lift pins 586, and a bias electrode 504. Each of the lift pins 586 is disposed through a via 585 formed in the substrate support assembly 536 and is used to facilitate the delivery of the substrate 503 to and from the substrate support surface 505A of the substrate support 505. The substrate support 505 is formed of a dielectric material. The dielectric material may include a bulk sintered ceramic material, a corrosion resistant metal oxide (e.g., aluminum oxide (Al2O3), titanium oxide (TiO), gadolinium oxide (Y2O3)), a metal nitride material (e.g., aluminum nitride (AlN), titanium nitride (TiN)), a mixture thereof, or a combination thereof.

[0048] The substrate support base 507 is formed of a conductive material. The substrate support base 507 is electrically isolated from the chamber base 524 by an insulator plate 511, and a ground plate 512 is interposed between the insulator plate 511 and the chamber base 524. In some embodiments, the substrate support base 507 is configured to adjust the temperature of the substrate support 505 and the substrate 503 disposed on the substrate support 505 during substrate processing. In some embodiments, the substrate support base 507 includes one or more cooling channels (not shown) disposed therein, the cooling channels being fluidly coupled to and in fluid communication with a coolant source (not shown), such as a cryogen source or a substrate source having a relatively high electrical resistance. In other embodiments, the substrate support 505 includes a heater (not shown) to heat the substrate support 505 and the substrate 503 disposed on the substrate support 505.

[0049] The bias electrode 504 is embedded in a dielectric material or otherwise coupled to the substrate support 505. Typically, the bias electrode 504 is formed by one or more conductive parts. The conductive parts typically include a mesh, a foil, a plate, or a combination thereof. The bias electrode 504 can be used as an adsorption electrode (i.e., an electrostatic adsorption electrode) for fixing (e.g., electrostatically adsorbing) the substrate 503 to the substrate support surface 505A of the substrate support 505. Typically, a parallel plate structure is formed by the bias electrode 504 and a layer of dielectric material disposed between the bias electrode 504 and the substrate support surface 505A. The dielectric material layer can be aluminum nitride (AlN), aluminum oxide (Al2O3), or other suitable materials.

[0050] The bias electrode 504 is electrically coupled to a clamping network that provides a clamping voltage thereto. The clamping network includes a DC voltage supply 573 (e.g., a high voltage DC supply) coupled to a filter 578A of a filter 578 disposed between the DC voltage supply 573 and the bias electrode 504. In one example, the filter 578A is a low pass filter configured to block RF frequencies and pulsed voltage (PV) waveform signals (e.g., waveform 320) provided by other bias components found within the plasma etching chamber 510 from reaching the DC voltage supply 573 during plasma processing. In one configuration, the static DC voltage is between about -5000V and about 5000V and is delivered using an electrical conductor (such as a coaxial power delivery line 560). In some embodiments, the bias electrode 504 may also use one or more of the pulsed voltage biasing schemes described in further detail below to bias the substrate 504 relative to the plasma 501.

[0051] In some configurations, the substrate support assembly 536 further includes an edge control electrode 515. The edge control electrode 515 is positioned below the edge ring 514 and surrounds the bias electrode 504 and / or is disposed at a distance from the center of the bias electrode 504. Typically, for a plasma etching chamber 510 configured to process a circular substrate, the edge control electrode 515 is annular in shape, made of a conductive material and configured to surround at least a portion of the bias electrode 504. As shown in Figure 5 As seen in FIG. 5 , one or both of the bias electrode 504 and the edge control electrode 515 are positioned within the region of the substrate support 505 and are biased with the waveform 320 using a pulsed voltage (PV) waveform generator 575. In one configuration, the edge control electrode 515 is biased using a different PV waveform generator than the PV waveform generator 575 used for the bias electrode 504. In another configuration, the edge control electrode 515 is biased by splitting a portion of the signal provided from the PV waveform generator 575 to the bias electrode 504.

[0052] The DC power system 583 includes a DC voltage supply 573, a pulsed voltage (PV) waveform generator 575, and a current source 577. The RF power system 589 includes a radio frequency (RF) waveform generator 571, a match 572, and a filter 574. As previously described, the DC voltage supply 573 provides a constant clamping voltage, while the RF waveform generator 571 delivers an RF signal to the processing region, and the PV waveform generator 575 establishes a PV waveform (such as waveform 320) at the bias electrode 504. Applying a sufficient amount of RF power to an electrode (such as a substrate support pedestal 507) causes a plasma 501 to form in the processing volume 529 of the plasma etch chamber 510.

[0053] In some embodiments, the power system 583 further includes a filter assembly 578 to electrically isolate one or more of the components contained within the power system 583. Figure 5 As shown, power delivery line 563 electrically connects the output of RF waveform generator 571 to impedance matching circuit 572, RF filter 574 and substrate support base 507. Power delivery line 560 electrically connects the output of voltage supply 573 to filter assembly 578. Power delivery line 561 electrically connects the output of PV waveform generator 575 to filter assembly 578. Power delivery line 562 connects the output of current source 577 to filter assembly 578. In some embodiments, current source 577 is selectively coupled to bias electrode 504 by using a switch (not shown) provided in delivery line 562 to allow current source 577 to deliver a desired current to bias electrode 504 during one or more phases (e.g., ion current phase) of the voltage waveform generated by PV waveform generator 575. As shown in Figure 5 As seen in FIG. 5 , filter assembly 578 may include a plurality of separate filter components (ie, discrete filters 578A- 578C) that are each electrically coupled to an output node via power delivery line 564 .

[0054] The system controller 526 (also referred to herein as a process chamber controller) includes a central processing unit (CPU) 533, a memory 534, and support circuits 535. The system controller 526 is used to control a process train (e.g., method 100) for etching the substrate 503. The CPU is a general-purpose computer processor in an industrial setting that is configured to control a process chamber and subprocessors associated therewith. The memory 534 (typically a non-volatile memory) described herein may include a random access memory, a read-only memory, a hard drive, or other suitable form of digital storage (local or remote), and may be used to store computer-readable instructions for implementing the method 100 performed by the plasma etching chamber 510. The support circuits 535 are conventionally coupled to the CPU 533 and include caches, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be encoded and stored within the memory 534 for instructing the processor within the CPU 533. A software program (or computer instructions) readable by the CPU 533 in the system controller 526 determines which tasks may be performed by the components in the plasma etch chamber 510, such as performing the method 100 to etch the substrate 200 in the manner described above.

[0055] In general, the program readable by the CPU 533 in the system controller 526 includes code that, when executed by the CPU 533, performs tasks related to the plasma processing method 100 described herein. The program may include instructions for controlling various hardware and electrical components within the plasma etching chamber 510 to perform various process tasks and various process sequences for implementing the methods described herein. Thus, in operation, the plasma etching chamber 510 performs the method 100 on each substrate 200 in a manner that produces excellent verticality of the sidewalls 222 of the etched features 224.

[0056] In one example of an etching method 100 performed in an exemplary plasma etching chamber 510, a substrate 200 disposed on a substrate support surface of a substrate support 505 is exposed to a plasma disposed within the etching chamber 510. The substrate includes a target layer to be etched. In one example, the target layer is a dielectric material, such as an oxide or a nitride. A voltage waveform is applied to an electrode (e.g., bias electrode 504) disposed in the substrate support 505 while exposing the substrate to the plasma during a plurality of macro-etching cycles. The plasma is formed by a process gas suitable for etching the target layer as described above. For example, when etching a dielectric target material (such as an oxide material or a nitride material), the process gas C X F Z and C X H Y F Z One or both of , where x, y, and z are integers.

[0057] In the presence of plasma in a chamber above the substrate, the target material is etched using a waveform having multiple macro-etching cycles, wherein each macro-etching cycle includes multiple micro-etching cycles. Each micro-etching cycle has a bias power on period and a bias power off period, wherein the duration of the bias power on period is less than the duration of the bias power off period. The macro-etching cycle is repeated until an endpoint is reached. Once the endpoint is reached, the plasma is extinguished, the flow of the process gas into the chamber is suspended, and the etched substrate is removed from the plasma etching chamber.

[0058] Thus, methods and apparatus for etching a substrate in a plasma etching chamber have been disclosed that reduce the tilt of the vertical sidewalls of the etched features compared to conventional techniques. The novel etching method utilizes a waveform for applying bias power to an electrode of a substrate support member that supports the substrate during etching in both macroscopic and microscopic schemes. In the macroscopic scheme, multiple macroscopic etching cycles are used to etch the substrate. The waveform includes a period in which the bias power is substantially stopped during a portion of each macroscopic etching cycle to allow the discharge of etching byproducts from the plasma etching chamber. By periodically removing etching byproducts from the chamber, the etchant may be more effectively delivered to the features being etched in a vertical trajectory. In the microscopic scheme of the waveform, multiple microscopic etching cycles are utilized during a portion of each macroscopic etching cycle. Each microscopic etching cycle includes a first period in which the bias power is turned on and a second period in which the bias power is substantially stopped. The duration of the second period is greater than the duration of the first period to provide time for the etching byproducts to leave the features being etched (such as holes, trenches, etc.). By periodically removing etching byproducts from the etched features, the etchant may be more effectively delivered to the bottom of the etched features in a vertical trajectory. The reduced number of collisions between the etchant and the etch byproducts enables the etchant to maintain a substantially vertical trajectory all the way to the bottom of the etched feature, thus advantageously resulting in reduced etching of the sidewalls and thus superior verticality of the sidewalls of the etched features. Enhanced verticality is particularly desirable when forming high aspect ratio features by etching.

[0059] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be conceived without departing from the basic scope thereof, and the scope of the same is determined by the following claims.

Claims

1. A method for etching a substrate in a plasma etching chamber, the method comprising: exposing the substrate disposed on a substrate supporting surface of a substrate support to a plasma within the processing chamber; as well as A voltage waveform is applied to an electrode disposed in the substrate support while exposing the substrate to the plasma during a plurality of macro-etching cycles, each macro-etching cycle comprising a first macro-etching cycle and a second macro-etching cycle, the macro-etching cycle comprising a plurality of micro-etching cycles, each micro-etching cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, the duration of the BPON period being less than the duration of the BPOFF period, and bias power is not primarily applied to the electrode during the second macro-etching cycle.

2. The method of claim 1, wherein the BPON period of one of the micro-etching cycles is less than 45% of the BPOFF period.

3. The method of claim 1, wherein the BPON period of one of the micro-etch cycles is between about 10% and about 45% of the BPOFF period.

4. The method of claim 1, wherein the multiple macro-etching cycles include a first macro-etching cycle occurring before a second macro-etching cycle, and wherein a BPON period of one of the micro-etching cycles of the first macro-etching cycle is greater than a BPON period of one of the micro-etching cycles of the second macro-etching cycle.

5. The method of claim 1, wherein a frequency of the macro-etch cycles of the plurality of macro-etch cycles decreases as the substrate is etched.

6. The method of claim 1, wherein the frequency of the macro-etch cycle is between about 2 Hz and about 100 Hz.

7. The method of claim 1, wherein the frequency of the micro-etching cycle is between about 25 kHz and about 500 kHz.

8. The method of claim 7, wherein the frequency of the macro-etch cycle is between about 2 Hz and about 100 Hz.

9. The method of claim 1, wherein each micro-etch cycle is at least an order of magnitude smaller than the macro-etch cycle.

10. The method of claim 1, further comprising: The plasma is formed from a process gas including carbon and at least one halogen. The method of claim 10 , wherein dielectric material is removed from the substrate during the BPON cycle.

12. The method of claim 11, wherein the dielectric material is an oxide material, a nitride material, or a stack of oxide and nitride layer pairs.

13. The method of claim 11, wherein the dielectric material comprises at least one oxide layer and at least one nitride layer.

14. The method of claim 11, wherein the process gas is C X F Z and C X H Y F Z One or both of , where x, y, and z are integers.

15. A method for etching a substrate in a plasma etching chamber, the method comprising: forming a plasma from a process gas comprising carbon and at least one halogen; exposing a dielectric layer disposed on the substrate to the plasma within the plasma etching chamber; as well as Applying bias power to an electrode disposed in a substrate support supporting the substrate in the plasma etching chamber while being exposed to the plasma during a plurality of macro-etching cycles until an end point is reached, each macro-etching cycle comprising a first macro-etching cycle and a second macro-etching cycle, the macro-etching cycle comprising a plurality of micro-etching cycles, each micro-etching cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, the duration of the BPON period being less than the duration of the BPOFF period, and bias power being predominantly not applied to the electrode during the second macro-etching cycle, wherein in at least the macro-etching cycle: The duration of the BPON period is at least two orders of magnitude shorter than the first macro-etching period; and The duration of the BPOFF period is at least two orders of magnitude shorter than that of the second macro-etching period.

16. The method of claim 15, wherein the BPON period of one of the micro-etch cycles is less than 45% of the BPOFF period.

17. The method of claim 15, wherein the BPON period of one of the micro-etch cycles is between about 10% and about 45% of the BPOFF period.

18. A method as claimed in claim 15, wherein the multiple macro-etching cycles include a first macro-etching cycle that occurs before a second macro-etching cycle, and wherein the BPON period of one of the micro-etching cycles of the first macro-etching cycle is greater than the BPON period of one of the micro-etching cycles of the second macro-etching cycle.

19. The method of claim 15, wherein a frequency of the macro-etch cycles of the plurality of macro-etch cycles decreases as the substrate is etched.

20. A plasma etching chamber comprising: a chamber body having an interior volume; a substrate support disposed within the interior volume of the chamber body, the substrate support configured to secure a substrate thereon during processing, the substrate support having an electrode; a bias power control system coupled to the electrode; a gas panel configured to provide a process gas to the interior volume; as well as The controller is configured as: maintaining a plasma formed from the process gas within the process chamber; as well as A voltage waveform is applied to the electrode while exposing the substrate disposed on the substrate support to the plasma during a plurality of macro-etching cycles, each macro-etching cycle comprising a first macro-etching cycle and a second macro-etching cycle, the macro-etching cycle comprising a plurality of micro-etching cycles, each micro-etching cycle having a bias power on (BPON) period and a bias power off (BPOFF) period, the duration of the BPON period being less than the duration of the BPOFF period, and bias power is not primarily applied to the electrode during the second macro-etching cycle.

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