Method for manufacturing semiconductor device, and semiconductor device

Abstract

Provided is a semiconductor device manufacturing method capable of reducing the width of a terminal region and suppressing electric field concentration in the terminal region. A method for manufacturing a semiconductor device having a termination region around an active region, the termination region having a plurality of well regions having a second conductivity type formed on a surface of a first semiconductor region having a first conductivity type, the second semiconductor region being a second semiconductor region. As a mask for forming the second semiconductor region, the second semiconductor region is formed by implanting impurities of the second conductivity type using a mask in which, when the distance from the outermost reference window is set as x, the interval S (x) between the implantation window at the position of x and the implantation window on the one active region side is substantially equal to a value defined by S (x) = Smax-(Smax-Smin) * (x / XN) 1 / 2.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In recent years, price competition has intensified in the field of power semiconductor devices, requiring cost reduction. To reduce costs, it is necessary to increase the diameter of wafers, lower the process temperature, and miniaturize chips. To this end, it is necessary to achieve shallow junctions in the terminal area, reduce the width of the terminal area, and suppress electric field concentration in the terminal area.

[0003] As a structure of the terminal region, for example, the following technology is described in Patent Document 1: a terminal structure 32 provided at the periphery of a semiconductor element comprises an N-type drift region 1 formed in a semiconductor substrate 30, and a P-type impurity region 2 formed in an upper surface portion of the N-type drift region 1. When macroscopically observed, the P-type impurity concentration of the P-type impurity region 2 decreases from the inner periphery toward the outer periphery of the terminal structure 32. When microscopically observed, the P-type impurity region 2 is composed of a plurality of P-type high-concentration regions 2b and low-concentration regions 2a surrounding the P-type impurity region 2b, and the low-concentration regions 2a have separated portions (Abstract, Figure 2 ).

[0004] In addition, the following technology is described in Patent Document 1: the aperture ratio of the injection mask 20 used in the ion implantation for forming such a P-type impurity region 2 is reduced toward the outside of the terminal structure 32 (paragraph 0042). The function for reducing the aperture ratio may be a linear function, etc., but a function with a high reduction rate such as an exponential function is desired. For example, when observed macroscopically, if a downwardly convex exponential function or a function that decreases according to a polynomial is used, the local concentration of the electric field can be alleviated (paragraph 0043).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2014 / 054319 Summary of the invention

[0008] Problems to be solved by the invention

[0009] However, Patent Document 1 describes a linear function and a downwardly convex exponential function (a) as a function for reducing the aperture ratio of the implantation mask 20. x ), according to a function that decreases according to a polynomial, but the results of simulations by the inventors of the present application have shown that the shape of the mask used to achieve the reduction in width of the terminal region and the suppression of electric field concentration in the terminal region is preferably a shape other than the shape specified by the function described in Patent Document 1.

[0010] An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of reducing the width of a termination region and suppressing electric field concentration in the termination region.

[0011] Solutions to Solve Problems

[0012] In order to solve the above-mentioned problems, a method for manufacturing a semiconductor device of the present invention is provided, for example, a method for manufacturing a semiconductor device having a terminal region around an active region, wherein a plurality of well regions having a second conductivity type, i.e., a second semiconductor region, are formed on a surface of a first semiconductor region having a first conductivity type. The method for manufacturing the semiconductor device is characterized in that:

[0013] The second semiconductor region is formed by injecting the second conductive type impurities using a mask, and the mask is a mask for forming the second semiconductor region. In a thermal equilibrium state, when the injection window corresponding to the second semiconductor region formed at the farthest position from the active region in the second semiconductor region where the depletion layer extending toward the first semiconductor region is continuous with the active region is set as a reference window, the position of the reference window on the active region side is set as X0, the distance between the position of the injection window adjacent to the active region on the active region side and the X0 is set as XN, the interval between the reference window and an injection window on the active region side thereof is set as Smax, the interval between the end of the active region and the injection window adjacent to the active region is set as Smin, and the distance from the X0 is set as x, the interval S(x) between the injection window at the position of the distance x and the injection window on the active region side thereof is equal to the interval S(x) given by

[0014] S(x)=Smax-(Smax-Smin)·(x / XN) 1 / 2

[0015] The specified values ​​are approximately equal.

[0016] In addition, the semiconductor device of the present invention has, for example, an active region and a terminal region formed around the active region, and the semiconductor device is characterized in that the terminal region has the second semiconductor region formed using the semiconductor device manufacturing method.

[0017] Effects of the Invention

[0018] According to the present invention, a method for manufacturing a semiconductor device and a semiconductor device can be realized, which can reduce the width of a termination region and suppress the electric field concentration in the termination region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional view of the semiconductor device of Example 1.

[0020] Figure 2 It is a top view explaining the shape of the mask of Example 1.

[0021] Figure 3 It is a diagram for explaining the interval between the implantation window of the mask of Example 1 and the implantation window on one active region side and the width of the implantation window.

[0022] Figure 4 This is a diagram illustrating the dose distribution of Example 1.

[0023] Figure 5 This is a diagram illustrating the dose distribution of Example 2.

[0024] Figure 6 It is a diagram for explaining the distance between the implantation window of the mask of Example 3 and the implantation window on one active region side and the width of the implantation window.

[0025] Figure 7 It is a diagram illustrating the distance between the implantation window of the mask of Example 4 and the implantation window on one active region side and the width of the implantation window.

[0026] Figure 8 It is a figure explaining the effect of this invention.

[0027] Fig. 9 It is a figure explaining the effect of this invention. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings and embodiments, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0029] Example 1

[0030] Figure 1 is a cross-sectional view of the semiconductor device of Example 1.

[0031] The semiconductor device 10 of the first embodiment has a terminal region 12 around an active region 11, and the terminal region 12 has a second semiconductor region 2 having a plurality of well regions having a second conductivity type (e.g., p-type) formed on the surface of a first semiconductor region 1 having a first conductivity type (e.g., n-type). Here, the first conductivity type is described as an n-type and the second conductivity type is described as a p-type, but the first conductivity type may be described as a p-type and the second conductivity type may be described as an n-type.

[0032] Semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and diodes are formed in the active region 11, but are not shown in the figure. As a semiconductor substrate formed with the semiconductor device 10, Si, SiC, etc. can be used, but it is not limited to this.

[0033] The first semiconductor region 1 and the second semiconductor region 2 are also formed in the active region 11 . Here, the second semiconductor region 2 in the active region 11 is referred to as a second semiconductor region 2 a .

[0034] In addition, the semiconductor device 10 has: an oxide film 4 formed to cover the first semiconductor region 1 or the second semiconductor region 2; an electrode 5 formed in the active region 11; and a channel cutoff ring 6 formed in the terminal region and having a high concentration of the first conductivity type. The electrode 5 is, for example, a gate electrode or an emitter electrode in the case of an IGBT, a gate electrode or a source electrode in the case of a MOSFET, and an anode electrode in the case of a diode. Figure 1 , only the front side of the semiconductor device 10 is shown, and the back side is omitted. The back side of the semiconductor device 10 is provided with an electrode (not shown), such as a collector electrode in the case of an IGBT, a drain electrode in the case of a MOSFET, and a cathode electrode in the case of a diode.

[0035] In the semiconductor device 10 of the first embodiment, in a thermal equilibrium state, the depletion layer 3 extending toward the first semiconductor region 1 continues from the active region 11 to each second semiconductor region 2, and each second semiconductor region 2 substantially becomes an intrinsic region. In addition, one of its characteristics is that the depletion of each second semiconductor region 2 (reduction of the intrinsic region) caused by the application of voltage starts from the second semiconductor region 2 on the peripheral side (the side away from the active region 11).

[0036] In the second semiconductor region 2 of the terminal region 12, on the side close to the active region 11, a plurality of second semiconductor regions 2 overlap to form a well region, and are also continuous with the second semiconductor region 2a of the active region 11. In the second semiconductor region 2 of the terminal region 12, on the side away from the active region 11, the second semiconductor regions 2 form well regions separated from each other.

[0037] Here, in a thermal equilibrium state, the second semiconductor region 2 formed at a position farthest from the active region 11 among the second semiconductor regions 2 where the depletion layer 3 extending toward the first semiconductor region 1 is continuous with the active region 11 is referred to as the outermost second semiconductor region 2 b where the depletion layer 3 is continuous.

[0038] Figure 2 It is a top view explaining the shape of the mask of Example 1. Figure 3 It is a diagram for explaining the interval between the implantation window of the mask of Example 1 and the implantation window on one active region side and the width of the implantation window.

[0039] Figure 3 The horizontal axis represents the position POS, the vertical axis on the left represents the interval S between the injection window 22 of the mask 20 and the injection window 22 on the side of an active area 11 (equivalent to the width of the shielding portion 21 ), and the vertical axis on the right represents the width W of the injection window 22 .

[0040] use Figure 2 The mask 20 shown is used to implant impurities of the second conductivity type to form the second semiconductor region 2. The mask 20 has a shielding portion 21 for shielding the impurities and an implantation window 22 as an opening for allowing the impurities to pass. In addition, the size of the second semiconductor region 2 becomes larger than the size of the implantation window 22 due to the diffusion of the implanted impurities.

[0041] Here, the injection window 22 corresponding to the second semiconductor region 2a of the active region 11 is called an active region injection window 22a, and the injection window 22 corresponding to the outermost second semiconductor region 2b continuous with the depletion layer 3 is called a reference window 22b.

[0042] The shape of the mask 20 of Example 1 is set to the following shape: when the position of the reference window 22b on the active area 11 side is set to X0, the distance between the position of the injection window 22 adjacent to the active area 11 on the active area 11 side and X0 is set to XN, the interval between the reference window 22b and one of the injection windows 22 on the active area 11 side is set to Smax, the interval between the end of the active area 11 and the injection window 22 adjacent to the active area 11 is set to Smin, and the distance from X0 is set to x, the interval S(x) between the injection window 22 at the position of the distance x and the injection window 22 on one of the active area 11 side is approximately equal to the value specified by the following formula (1).

[0043] S(x)=Smax-(Smax-Smin)·(x / XN) 1 / 2 ···(1)

[0044] This makes it possible to reduce the width of the terminal region in the terminal region 12 and suppress the electric field concentration in the terminal region. The details of these effects will be described later.

[0045] In addition, the shape of the mask 20 of Example 1 is set to a shape in which the width W(x) of the implantation window 22 at a position of a distance x decreases as it moves away from the active region 11 .

[0046] Thus, compared with a case where the width W(x) of the injection window 22 is constant regardless of the position at the distance x, the width of the second semiconductor region 2 can be reduced, and thus the width of the termination region 12 can be reduced.

[0047] In Example 1, Figure 3 As shown, the width W(x) of the implantation window at a distance x decreases linearly as it moves away from the active region 11 .

[0048] Figure 4 This is a diagram illustrating the dose distribution of Example 1. Figure 4 The horizontal axis represents the position POS, and the vertical axis represents the dose DO.

[0049] In Embodiment 1, when the second conductivity type impurity is implanted using the mask 20 , the dose in the second semiconductor region 2 a of the active region 11 and the dose in the second semiconductor region 2 of the termination region 12 are set to have substantially equal dose distributions.

[0050] Thus, the second semiconductor region 2 can be formed by implanting the second conductivity type impurities using one mask 20 .

[0051] Next, the effects of reducing the width of the terminal region 12 and suppressing the electric field concentration in the terminal region 12 that can be achieved by the shape of the mask 20 according to the first embodiment will be described in detail.

[0052] Figure 8 It is a figure explaining the effect of this invention. Figure 8 The horizontal axis represents the position POS, and the vertical axis represents the interval S (equivalent to the width of the shielding portion 21 ) between the implantation window 22 of the mask 20 and the implantation window 22 on one active region 11 side.

[0053] The interval S(x) between the injection window 22 at a distance x from X0 and the injection window 22 on the active region 11 side thereof can be expressed as the following equation (2).

[0054] S(x)=Smax-(Smax-Smin)·(x / Lx) α ···(2)

[0055] In the case of α=1 / 2, it is the same as formula (1). Here, when the number of injection windows 22 is set to 15, and the distance between the position of the injection window 22 adjacent to the active region 11 on the active region 11 side and X0 is set to Lx(α), the interval S(x) and Lx(1 / 4), Lx(1 / 2), Lx(1.0), Lx(2.0) are calculated for α=1 / 4, 1 / 2, 1.0, 2.0, respectively, and Figure 8 Shown in.

[0056] As a result, it can be seen that the smaller α is, the smaller Lx(α) is, that is, the width of the terminal region 12 can be reduced.

[0057] Here, α=1.0 corresponds to the case where the interval S(x) increases linearly toward the outer periphery of the terminal region 12 (x approaches 0), which is different strictly speaking, but in Patent Document 1, the aperture ratio of the implantation mask 20 is roughly equivalent to the case where it decreases according to a linear function toward the outside of the terminal structure 32. In addition, in Patent Document 1, α=2.0 is roughly equivalent to the case where the aperture ratio of the implantation mask 20 decreases according to a polynomial toward the outside of the terminal structure 32. However, in the case of α=1.0 and α=2.0, Lx(1.0) and Lx(2.0) are larger than Lx(1 / 2), which shows that it is not suitable to reduce the width of the terminal region 12.

[0058] In addition, although Figure 8 Although not shown in the figure, as an example of an exponential function, the interval S(x) also depends on e x The case of change (in Patent Document 1, it is roughly equivalent to the case where the aperture ratio of the implantation mask 20 decreases exponentially toward the outside of the terminal structure 32) is calculated and is roughly close to the case of α=2.0. Therefore, it is known that this case is not suitable for reducing the width of the terminal region 12.

[0059] In addition, the withstand voltage was investigated and it was found that the values ​​were all around 900 V when α=1 / 4, 1 / 2, 1.0, and 2.0, which is sufficient for use as a device with a withstand voltage of 750 V.

[0060] Fig. 9 It is a figure explaining the effect of this invention. Fig. 9 The horizontal axis represents α, and the vertical axis represents the maximum electric field intensity Emax (kV / cm) in the terminal region 12 when 750 V is applied.

[0061] like Fig. 9 As shown in the figure, when α=1 / 2, the maximum electric field intensity Emax becomes the smallest. A small maximum electric field intensity Emax means that the electric field concentration in the terminal region 12 can be suppressed.

[0062] Avalanche breakdown is a phenomenon in which electrons accelerated by an electric field collide with atoms and strip electrons from atoms, causing an avalanche. When the electric field intensity that causes breakdown is Ec and the electric field intensity is E, the current I increases rapidly in the form of the following formula (3).

[0063] I=I0 / [1-(E / Ec) k ]···(3)

[0064] Here, I0 and k are constants. When the electric field intensity E reaches the electric field intensity Ec at which breakdown occurs, avalanche breakdown occurs, and therefore E<Ec.

[0065] According to formula (3), the smaller the electric field strength E is, the larger the denominator of formula (3) is, and the current I becomes smaller, so it is difficult to produce avalanche breakdown, and the current becomes smaller, which is conducive to ensuring the long-term reliability of long-term voltage application. Fig. 9 As shown, when α=1 / 2, the maximum electric field intensity Emax becomes the smallest, so the electric field intensity E and the current I also become smaller, which is found to be the most optimal.

[0066] according to Figure 8 as well as Fig. 9 It can be seen that in formula (2), when α=1 / 2, formula (1) is the most suitable.

[0067] As described above, according to Example 1, by adopting a mask 20 having a shape in which the interval S(x) between the injection window 22 at a distance x and the injection window 22 on one side of an active region 11 is approximately equal to the value specified by formula (1), it is possible to reduce the width of the terminal region 12 and suppress the electric field concentration in the terminal region 12.

[0068] Example 2

[0069] Figure 5 This is a diagram illustrating the dose distribution of Example 2. Figure 5 is the same as Example 1 Figure 4 The corresponding figure.

[0070] The dose distribution of Example 2 is different from that of Example 1.

[0071] like Figure 5 As shown, the dose distribution of Example 2 is set to the following dose distribution: in the terminal region 12, the dose of the second semiconductor region 2 in the terminal region 12a on the side close to the active region 11 is larger than the dose of the second semiconductor region 2 in the terminal region 12b on the side away from the active region 11.

[0072] This has the effect of being able to suppress a decrease in withstand voltage due to positive interface charges.

[0073] However, in the second embodiment, in order to vary the dose according to the region, two masks 20 need to be used to implant the second conductivity type impurity, which is also different from the first embodiment.

[0074] The configuration other than the above is the same as that of Embodiment 1, and therefore repeated descriptions are omitted.

[0075] Example 3

[0076] Figure 6 It is a diagram for explaining the distance between the implantation window of the mask of Example 3 and the implantation window on one active region side and the width of the implantation window. Figure 6 is the same as Example 1 Figure 3 The corresponding figure.

[0077] In the third embodiment, the width W(x) of the injection window 22 at the distance x is different from that in the first embodiment.

[0078] The shape of the mask 20 in the third embodiment is set to the following shape: the width W(x) of the injection window 22 at the position of the distance x decreases linearly as it moves away from the active region 11, and the slope of the decrease on the side close to the active region 11 (x>XN') is greater than the slope of the decrease on the side far from the active region 11 (x≤XN'). Figure 6 In FIG. 1 , Wmax′ is the value of the width W(x) of the injection window 22 at a position where the distance x is XN′.

[0079] Next, the reason for changing the slope of the reduction of the width W(x) of the injection window 22 is explained. Through the heat treatment after the second conductivity type impurity is injected, the width of the second semiconductor region 2 is expanded and the peak concentration is also reduced. The narrower the width W(x) of the injection window 22, the greater the reduction in the peak concentration, and the wider the width, the less. In contrast, the width of the injection window 22 of the second semiconductor region 2a of the active region 11 is much wider than the width W(x) of the injection window of the terminal region 12, so the reduction in the peak concentration of the second semiconductor region 2a of the active region 11 is less than that of the second semiconductor region 2 in the terminal region 12. Therefore, a difference in peak concentration occurs in the active region 11 and the second semiconductor region 2 adjacent thereto. Here, in the presence of a large concentration difference, an electric field concentration occurs at the end of the active region 11, which may lead to a decrease in withstand voltage. Therefore, it is preferred that the width W(x) of the injection window 22 is expanded near the active region 11. On the other hand, if the width W(x) of the injection window 22 is expanded, the overall width of the terminal region 12 becomes larger, so it is better to make it as narrow as possible. As a countermeasure for the electric field concentration at the end of the active region 11, it is sufficient to only have it near the active region 11. Figure 6As shown in FIG. 1 , by adopting a shape in which the slope of the reduction on the side close to the active region 11 (x>XN') is larger than the slope of the reduction on the side far from the active region 11 (x≤XN'), it is possible to take measures to reduce the electric field concentration at the end of the active region 11 while achieving the desired effect. Figure 3 Compared with the case of , the width of the entire terminal region 12 can be narrowed. This is the reason for changing the slope of the reduction of the width W(x) of the injection window 22.

[0080] In addition, even if one mask 20 is used as in Example 1, Figure 4 When the second semiconductor region 2 is formed by implanting the second conductivity type impurity with the same dose profile, there is an effect similar to the second embodiment that a decrease in the breakdown voltage due to the positive interface charge can be suppressed.

[0081] The configuration other than the above is the same as that of Embodiment 1, and therefore repeated descriptions are omitted.

[0082] Example 4

[0083] Figure 7 It is a diagram illustrating the distance between the implantation window of the mask of Example 4 and the implantation window on one active region side and the width of the implantation window. Figure 7 is the same as Example 1 Figure 3 The corresponding figure.

[0084] In the fourth embodiment, the width W(x) of the injection window 22 at the distance x is different from that in the first and third embodiments.

[0085] The shape of the mask 20 in Example 4 is set to the following shape: when the width of the injection window 22 at the position of the distance XN is set to Wmax and the width of the injection window 22 of the reference window 22b is set to Wmin, the width W(x) of the injection window 22 at the position of the distance x is approximately equal to the value specified by the following formula (4).

[0086] W(x)=Wmax-(Wmax-Wmin)·(1-x / XN) 1 / 2 ···(4)

[0087] In Example 4, the width W(x) of the injection window 22 can be changed gently rather than linearly, and the decrease in withstand voltage due to positive interface charges can be suppressed.

[0088] The configuration other than the above is the same as that of Embodiment 1 and Embodiment 3, and therefore repeated descriptions are omitted.

[0089] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, part or all of the structures described in the embodiments can also be combined and applied.

[0090] Explanation of symbols

[0091] 1—first semiconductor region, 2—second semiconductor region, 3—depletion layer, 4—oxide film, 5—electrode, 6—channel truncation ring, 10—semiconductor device, 11—active region, 12, 12a, 12b—terminal region, 20—mask, 21—shielding portion, 22—injection window, 22a—active region injection window, 22b—reference window, S—interval between the injection window and the injection window on one active region side, W—width of the injection window, x—distance, DO—dose, POS—position.

Claims

1. A method for manufacturing a semiconductor device, wherein the semiconductor device has a terminal region around an active region, wherein the terminal region has a plurality of well regions of a second conductivity type formed on a surface of a first semiconductor region of a first conductivity type, i.e., a second semiconductor region, wherein the method for manufacturing the semiconductor device is characterized in that: The second semiconductor region is formed by injecting the second conductive type impurities using a mask, and the mask is a mask for forming the second semiconductor region. In a thermal equilibrium state, when the injection window corresponding to the second semiconductor region formed at the farthest position from the active region in the second semiconductor region where the depletion layer extending toward the first semiconductor region is continuous with the active region is set as a reference window, the position of the reference window on the active region side is set as X0, the distance between the position of the injection window adjacent to the active region on the active region side and the X0 is set as XN, the interval between the reference window and an injection window on the active region side thereof is set as Smax, the interval between the end of the active region and the injection window adjacent to the active region is set as Smin, and the distance from the X0 is set as x, the interval S(x) between the injection window at the position of the distance x and the injection window on the active region side thereof is equal to the interval S(x) given by S(x)=Smax-(Smax-Smin)·(x / XN) 1 / 2 The specified values ​​are approximately equal.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: In the mask, a width W(x) of the implantation window at the distance x decreases as it moves away from the active region.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: In the mask, a width W(x) of the implantation window at the distance x decreases linearly as it moves away from the active region.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: In the mask, a width W(x) of the injection window at the distance x decreases linearly as it moves away from the active region, and a decreasing slope on a side close to the active region is greater than a decreasing slope on a side far from the active region.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The mask is a mask in which, when the width of the injection window at the position of the distance xN is set to Wmax and the width of the injection window of the reference window is set to Wmin, the width W(x) of the injection window at the position of the distance x is equal to W(x)=Wmax-(Wmax-Wmin)·(1-x / XN) 1 / 2 The specified values ​​are approximately equal.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: When the second conductivity type impurity is implanted using the mask, a dose in the second semiconductor region of the active region is substantially equal to a dose in the second semiconductor region of the terminal region.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: When the second conductivity type impurity is implanted using the mask, in the terminal region, a dose of the second semiconductor region on a side close to the active region is larger than a dose of the second semiconductor region on a side far from the active region.

8. A semiconductor device comprising an active region and a termination region formed around the active region, wherein: The termination region includes the second semiconductor region formed using the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. The semiconductor device according to claim 8, wherein: In the above-mentioned second semiconductor region, from the second semiconductor region formed by the injection window adjacent to the above-mentioned active region to the region of the second semiconductor region formed by the above-mentioned reference window, in a thermal equilibrium state, the above-mentioned depletion layer extending toward the above-mentioned first semiconductor region is continuous from the above-mentioned active region, and each second semiconductor region roughly becomes an intrinsic region, and the depletion of each of the above-mentioned second semiconductor regions caused by applying voltage starts from the above-mentioned second semiconductor region formed by the above-mentioned reference window.

10. The semiconductor device according to claim 8, wherein: In the above-mentioned second semiconductor region, from the second semiconductor region formed by the injection window adjacent to the above-mentioned active region to the region of the second semiconductor region formed by the above-mentioned reference window, on the side close to the above-mentioned active region, multiple above-mentioned second semiconductor regions overlap to become the above-mentioned well region, and on the side away from the above-mentioned active region, the above-mentioned second semiconductor regions become the above-mentioned well regions separated from each other.

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