Asynchronous CIOS modular multiplication algorithm and asynchronous modular multiplication architecture

Abstract

The present invention discloses an asynchronous CIOS modular multiplication algorithm and an asynchronous modular multiplication architecture. j The three small loops are combined to eliminate the need for j The data of the first two small cycles are temporarily stored. j The calculation of the third small loop is integrated in j In the second stage of pipeline after the second small cycle calculation, a two-stage pipeline is formed. j After the first small loop of j The second small loop starts the first round of calculation and completes j The assignment of the third small loop, at the same time, j The first small loop of starts the second round of calculation, and so on; CIOS modular multiplication algorithm i The pipeline of the internal calculation of the large loop completes parallel calculation through asynchronous circuits. The asynchronous micro pipeline includes three basic structures: FIFO, Fork and Merge. The present invention merges the loops of the CIOS modular multiplication algorithm and uses asynchronous circuits to realize the pipeline parallel calculation of the internal calculation of the large loop, thereby reducing the calculation area and improving the calculation speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of encryption and decryption operations, and specifically relates to an asynchronous CIOS modular multiplication algorithm and an asynchronous modular multiplication architecture. Background Art

[0002] Cryptography is the core of data security throughout its life cycle. It can fully realize the functions of preventing information leakage, content tampering, identity counterfeiting, and behavior non-repudiation in cyberspace. Through these functions, the confidentiality and authenticity of information are ensured, while ensuring the integrity of data and the non-repudiation of behavior. Cryptographic algorithms are divided into symmetric encryption algorithms and asymmetric encryption algorithms according to the key type. Asymmetric encryption algorithms are more complex and more secure.

[0003] RSA (Rivest-Shamir-Adleman) algorithm and Elliptic Curve Cryptography (ECC) are two classic asymmetric cryptographic algorithms. The RSA encryption and decryption operations are mainly modular exponentiation operations. For example, the RSA encryption calculation process is plaintext M With the public key ( e , N )go through M e mod N After calculation, the ciphertext is obtained C . Directly performing power operations will take up a lot of resources and have low efficiency. Therefore, in actual operations, more convenient algorithms are usually used. The most common method is the famous fast power algorithm (also known as the binary power algorithm). The principle of the binary power algorithm is to convert the exponent into a binary representation, and then scan each binary bit of the exponent in turn, and perform different modular multiplication and modular square operations according to the value of the current bit. Similarly, the scalar multiplication calculation in the ECC algorithm is also based on modular multiplication. Therefore, modular multiplication calculation is the most frequently called and time-consuming module in the asymmetric encryption algorithm.

[0004] At present, the most commonly used modular multiplication algorithm is the Montgomery algorithm, which is a cryptographic algorithm for large integers. N mods N The operation is converted into an easy-to-implement integer power of 2 R mods R Operation, thus converting complex division into simple shift, achieving the effect of saving computing resources. However, cryptographic algorithms are all based on large numbers. RSA requires at least 1024 bits and ECC requires at least 256 bits. Therefore, when implementing the Montgomery modular multiplication algorithm, the operands are all integers with a large bit width, and the intermediate results are TIt is the multiplication of two large numbers, which not only affects the calculation efficiency but also wastes storage space. In order to further save resources, many methods for splitting large integers have been derived, splitting large integer operations into multiple w Operations on bit integers ( w is the width of the machine integer) to obtain a Montgomery modular multiplication algorithm that is more suitable for hardware implementation. There are currently five main implementation methods: SOS, CIOS, FIOS, FIPS and CIHS. Among them, the CIOS modular multiplication algorithm has the fastest calculation speed and the smallest calculation amount and storage space, so it is highly favored.

[0005] However, the existing CIOS modular multiplication algorithm has the following shortcomings:

[0006] 1. There are three small loops in the traditional CIOS modular multiplication algorithm, which can only be performed serially, and after each small loop is calculated, the intermediate results need to be saved in registers before the next loop is calculated. In large number calculations such as cryptographic algorithms, this serial calculation is inefficient and occupies resources;

[0007] 2. The current implementation of analog multipliers mainly adopts synchronous circuit design methods. However, as the scale of circuits continues to expand, the encryption and decryption algorithms implemented by synchronous timing circuits based on clock mechanisms will generate a huge clock network, increasing unnecessary waiting time. In addition, since the clock signal needs to be propagated throughout the circuit, some parts of the circuit design will still generate power consumption when they are not working for a period of time. Summary of the invention

[0008] In view of the problems existing in the above-mentioned background technology, the purpose of the present invention is to provide an asynchronous CIOS modular multiplication algorithm and an asynchronous modular multiplication architecture, merge the loops of the CIOS modular multiplication algorithm, and utilize the good modular characteristics of asynchronous circuits to realize pipeline parallel calculations of calculations inside large loops; reduce the calculation area while improving the calculation speed.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] An asynchronous CIOS modular multiplication algorithm comprises the following steps: j The three small loops are combined to eliminate the need for j The data of the first two small cycles are temporarily stored. j The calculation of the third small loop is integrated in j In the second stage of pipeline after the second small cycle calculation, a two-stage pipeline is formed. j After the first small loop of j The second small loop starts the first round of calculation and completes j The assignment of the third small loop, at the same time, jThe first small loop of starts the second round of calculation, and so on; CIOS modular multiplication algorithm i The pipeline of the large loop internal calculation completes parallel calculation through asynchronous circuits. i is the number of large loops of the CIOS modular multiplication algorithm, j is the number of small loops of the CIOS modular multiplication algorithm.

[0011] Furthermore, the asynchronous CIOS modular multiplication algorithm is as follows:

[0012] .

[0013] Furthermore, the asynchronous controller in the asynchronous circuit adopts a click control unit.

[0014] The present invention further provides an asynchronous modular multiplication architecture for implementing an asynchronous CIOS modular multiplication algorithm, and uses a coarse-grained asynchronous micro-pipeline design method to build an asynchronous micro-pipeline. The asynchronous micro-pipeline includes the following basic structures:

[0015] FIFO: First-in-first-out pipeline structure;

[0016] Fork: A branch structure that inputs one channel and sends it to multiple output channels according to different situations;

[0017] Merge: A merging structure where multiple inputs are arbitrated according to different situations and then sent to one output;

[0018] The Fork includes CopyFork and CondFork, and the Merge includes WaitMerge and MutexMerge;

[0019] The basic structure is used in combination in the asynchronous circuit implementation process of modular multiplication. The cyclic calculation in the asynchronous CIOS modular multiplication algorithm is realized by combining a MutexMerge, a FIFO and a CondFork, and the parallel calculation in the asynchronous CIOS modular multiplication algorithm is realized by a CopyFork combined with multiple FIFOs and WaitMerge.

[0020] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:

[0021] 1. The pipeline calculation time in the asynchronous CIOS modular multiplication algorithm provided by the present invention is reduced, and the calculation time can be shortened to about 50% of the original time. The larger the data bit width, the more obvious the improvement;

[0022] 2. The asynchronous micro-pipeline control of the present invention is simple to implement and easy to control. Since the asynchronous circuit has the unique characteristic of good modularity and is implemented based on a specific asynchronous controller, the control circuit and the data calculation module can be separated in the algorithm of the present invention, and the calculation module remains unchanged. Only a well-designed asynchronous pipeline is needed to change or maintain the clock control. This not only satisfies the simplicity of implementation and modification, but also facilitates the implementation of pipeline parallel calculation, thereby improving the calculation efficiency of the algorithm.

[0023] 3. Save resources and reduce area: In the calculation process of the present invention, the intermediate results do not need to be stored and the next round of calculation can be directly carried out, which greatly reduces the number of resources used. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a graphical schematic diagram of a conventional CIOS modular multiplication algorithm provided by an embodiment of the present invention;

[0025] Figure 2 is a graphical schematic diagram of an asynchronous CIOS modular multiplication algorithm provided by an embodiment of the present invention;

[0026] Figure 3 is a circuit structure diagram of an asynchronous controller provided by an embodiment of the present invention;

[0027] Figure 4 It is a schematic diagram of FIFO usage provided by an embodiment of the present invention;

[0028] Figure 5 It is a schematic diagram of using CondFork provided by an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of the pipeline calculation process of 256-bit modular multiplication calculation provided by an embodiment of the present invention;

[0030] Figure 7 It is a structural diagram of the asynchronous modular multiplication architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] 1. Asynchronous CIOS modular multiplication algorithm

[0033] The traditional CIOS modular multiplication algorithm is shown in Table 1:

[0034] Table 1 Traditional CIOS modular multiplication algorithm

[0035] .

[0036] In Table 1, i is the number of large loops of the CIOS modular multiplication algorithm, j is the number of small loops of the CIOS modular multiplication algorithm. i The large loop is called FOR1, and the internal j The three small loops are called FOR2, FOR3, and FOR4, where FOR2 represents the operations shown in lines 3, 4, 5, and 6. j The first small loop, FOR3 represents the 12th, 13th, 14th, and 15th lines. j The second small loop, FOR4, represents the pairing of lines 19, 20, and 21. j As can be seen from Table 1, FOR2 and FOR3 are highly symmetrical in arithmetic operations and have strong parallelism in hardware implementation. In addition, by observing FOR4, we can see that the first group of w Bit of data T [0] will be directly overwritten without register preservation. The idea of ​​the present invention to enhance the CIOS modular multiplication algorithm is to merge FOR2, FOR3 and FOR4 to save intermediate storage resources, and at the same time take advantage of the good modularity of asynchronous circuits to achieve three-cycle pipeline processing and improve the operation speed.

[0037] The asynchronous CIOS modular multiplication algorithm of the present invention combines the traditional CIOS modular multiplication algorithm with j The three small loops are combined to eliminate the need for j The data of the first two small cycles are temporarily stored. j The calculation of the third small loop is integrated in j In the second stage of pipeline after the second small cycle calculation, a two-stage pipeline is formed. j After the first small loop of j The second small loop starts the first round of calculation and completes j The assignment of the third small loop, at the same time, j The first small loop of starts the second round of calculation, and so on; CIOS modular multiplication algorithm i The pipeline of the internal calculation of the large loop completes the parallel calculation through the asynchronous circuit. The asynchronous CIOS modular multiplication algorithm is shown in Table 2:

[0038] Table 2 Asynchronous CIOS modular multiplication algorithm

[0039] .

[0040] The graphical schematic diagrams of the conventional CIOS modular multiplication algorithm and the asynchronous CIOS modular multiplication algorithm of the present invention are shown in FIG. Figure 1 and 2 As shown, Figure 1 In the example, after the drive signal drive pulse arrives, the large loop FOR1 is started. Three small loops FOR2, FOR3 and FOR4 are nested inside the large loop. The loops FOR2, FOR3 and FOR4 are executed in sequence, and data is temporarily stored after the FOR2 and FOR3 loops. After each loop is executed, the next loop starts. Figure 2 In the example, after the drive signal drive pulse arrives, the large loop FOR1 is also started first, but the original three small loops in the large loop FOR1 are no longer executed in sequence, but the original small loops FOR2, FOR3, and FOR4 are merged to form FOR2'. Figure 1 and 2 It can be seen that the most essential difference between the two algorithms is that j After all the small loops are merged, the two data storages of FOR2 and FOR3 are omitted, making the data of the three originally serial small loops T [ j ]( T [ j ] indicates the intermediate storage j +1 Group w bit data) can be immediately transferred to where it is needed for calculation without waiting; the remaining carry transfers are no different from tN calculations.

[0041] 2. Asynchronous circuit mechanism

[0042] Asynchronous circuits are also called clockless or self-timed circuits. Asynchronous controllers are the core of asynchronous micropipelines. The asynchronous controller of the present invention uses a click control unit. Its circuit structure is as follows: Figure 3 As shown, it includes two pairs of input / output terminals, the purpose of which is to cooperate with the asynchronous control units of the upper and lower levels. The input request signal in_R and the output response signal in_A are used to communicate with the upper click module, and the input response signal out_A and the output request signal out_R are connected to the lower click module. When the upper in_R rises, the signal will become high after passing through the XOR gate. At this time, the output default value of the XOR gate is a high level. The two pass through the middle AND gate together, so the result is a high level output. On the one hand, the output of the AND gate will serve as the local trigger signal fire of the circuit, and on the other hand, it will activate the trigger to work. Its output value acts on the response signal of the upper controller, the request signal of the lower controller, and the input end of the XOR gate. After completing the above working mechanism, the upper and lower click modules will reset the two signals in_A and out_R of this control unit, and cancel the local activation signal fire at the same time.

[0043] The present invention uses a coarse-grained asynchronous micro-pipeline design method to build an asynchronous micro-pipeline. The asynchronous micro-pipeline includes the following basic structures:

[0044] FIFO: First-in-first-out pipeline structure;

[0045] Fork: A branch structure that inputs one channel and sends it to multiple output channels according to different situations;

[0046] Merge: A merging structure where multiple inputs are arbitrated according to different situations and then sent to one output;

[0047] The three basic structures are used in combination in the asynchronous circuit implementation process of modular multiplication to achieve specific functions.

[0048] FIFO usage diagram is as follows Figure 4 As shown in the figure, when the input on the left side of the module is valid, the FIFO starts to work, generates three signals in sequence, drives the trigger to work, thereby controlling the timing between the combinational logic (CL), and finally generates an output signal to the next level on the right and a response signal to the previous level on the left. After the next level FIFO is completed, a response signal will be sent to the input end on the right side of the current level FIFO, and the internal signal will be reset.

[0049] Fork structures mainly include CopyFork and CondFork. CopyFork distributes one event to multiple events simultaneously and unconditionally; CondFork selects which events to distribute to based on the valid signal generated by the designer's custom combinational logic, and can start different subsequent modules according to different conditions. The schematic diagram of CondFork usage is shown in the following figure. Figure 5 As shown, before use, it is necessary to generate a valid signal according to the combinational logic (CL) configuration. In the figure, valid signals of different paths are marked with valid0 and valid1. When the module input signal is valid, the validity of the two output signals of the module is determined based on whether valid0 and valid1 are valid. At the same time, a fire signal is generated to control other sequential logics.

[0050] There are two main Merge structures: WaitMerge and MutexMerge. WaitMerge waits for all input events to arrive before sending a new event request to the next level; MutexMerge is a mutually exclusive relationship between inputs, only one input will arrive at the same time, and MutexMerge sends the input that arrives at the current moment to the next level module.

[0051] 3. Asynchronous modular multiplication architecture

[0052] It can be seen from the asynchronous CIOS modular multiplication algorithm of the present invention that after the loops are merged, there is no data dependency between the original FOR2 and FOR3 calculations in each round. At the same time, the shift operation does not need to be a separate loop. It is only necessary to save the calculation result in the corresponding position in the assignment stage after the calculation is completed. Therefore, the FOR4 calculation is integrated into the second-level pipeline after the original FOR3 calculation, so that the original three loops form a two-level pipeline. Taking the 256-bit modular multiplication calculation as an example, the pipeline calculation process is as follows: Figure 6 As shown in the figure, C 1[0], S 1[0], C 1[1] S 1[1] C 1[2]、 S 1[2]、 C 1[3]、 S 1[3] represents FOR2, C 2[0]、 S 2[0]、 C 2[1]、 S 2[1]、 C 2[2]、 S 2[2]、 C 2[3]、 S 2[3] represents FOR3, C 1[0], S 1[0] indicates that the algorithm j =0, that is, the first round of calculation, and the meanings of other numbers are the same. After the original FOR2 completes the first round of calculation, the original FOR3 starts the first round of calculation and completes the assignment of the original FOR4; at the same time, the original FOR2 starts the second round of calculation, and so on. The original FOR2 has 4 inputs for one round of calculation, and the carry C 1. The calculation result is temporarily stored in the register t and operands a and b , assuming C 1 bit width is w ,but t,a , b The bit width is w An integer multiple of t [0] Representative t according to w The first group of data is obtained after a grouping. The meanings of other numbers are the same. After a round of calculation, the output is updated. C 1 and t [0], t [0] as the original FOR3 input to support its calculation, C1 is used as the input of the next round of calculation of the original FOR2 to continue the original FOR2. The remaining three inputs of the original FOR3 n , m , C 2 represents the algorithm operand, the intermediate result of the algorithm and the carry of FOR3. This pipeline calculation can shorten the calculation time to about 50% of the original time. The larger the data bit width, the more obvious the improvement. For example, if we implement n Bitwise modular multiplication operation, the calculation window is w bits, then the asynchronous CIOS modular multiplication algorithm of the present invention can change the number of cycles from Reduce to In fact, the shift operation cycle has little effect on the speed, mainly the first two multiplication and addition operation cycles. The number of multiplication and addition calculations of the asynchronous CIOS modular multiplication algorithm of the present invention is from Reduce to , which increases the computation speed by about 50%.

[0053] Taking the asynchronous CIOS modular multiplication algorithm based on modulo 64 as an example, the asynchronous modular multiplication implementation architecture is as follows: Figure 7 As shown, combined Figure 7 The calculation process is described as follows:

[0054] When performing modular multiplication calculations, the top-level module transmits a pulse signal i_drive to start the modular multiplication module. Figure 7 The part between the two ② marking lines is the large loop, and the part between the two ① marking lines is the merged small loop. After the first level of MutexMerge that controls the large loop, the next level of MutexMerge that controls the small loop is generated. After the operands are prepared, CopyFork is used to calculate them in two ways at the same time. and T [ j ]+ C 1, a [ j ] indicates the input j +1 Group w bit data, b [ i ] indicates the first i +1 Group w bit data, T [ j ] indicates the intermediate storage j +1 Group w bit data, C 1 is the carry of FOR2. After the two paths are calculated, they are merged into one path through WaitMerge and the calculation continues. After the addition calculation is completed, CondFork determines whether the current round is the first round of the small loop, that is, j=0, if yes, then the intermediate result of the algorithm is calculated and updated through the multiplier and FIFO m If not, skip this step. The counter will also be incremented or cleared to record the current j The two events generated by CondFork are merged by MutexMerge to start the next level CondFork. The Fork structure is the key to realize pipelining. One of them unconditionally starts the next level to calculate the original FOR3, and the other one is based on the counter. j The size of determines whether the loop ends. If not, an event is generated to drive the control of the small loop MutexMerge, and the original FOR2 calculation continues. Otherwise, no event is generated. j During the round of calculation, the original FOR3 j -1 round of calculation is also in progress. After the same structural calculation , S 1 for w bit register, N [ j ] indicates input data N No. j +1 Group w bit data, C 2 is the carry of FOR3. After the calculation is completed, the number of cycles of the original FOR3 is recorded through FIFO. Then, CondFork determines whether to save the result at this time according to whether the cycle number register is 0. Then the two events generated by CondFork at this level are merged through MutexMerge to start the next level CondFork. The small cycle is determined according to the cycle number register. If it is not ended, no action is taken and the start signal of the upper pipeline is continued. If it is ended, the calculation is performed. T [ s -1] and T [ s ], T [ s -1] and T [ s ] respectively represent the s Group and s +1 Group w bit data, s The number of groups divided according to the bit width is then updated. After the update is completed, CondFork is passed. If the large loop has not ended, an event is generated and passed to MutexMerge that controls the large loop, and then the above process is calculated; if the calculation is completed, tN is calculated. After the calculation is completed, the algorithm ends. After the correct result is generated, the o_driveNext signal is valid and returned to the top-level module to inform it that the calculation has been completed.

[0055] The present invention combines the loops of the traditional CIOS modular multiplication algorithm and uses the good modular characteristics of asynchronous circuits to realize pipeline parallel calculation of the internal calculation of the large loop. In addition, the calculation speed is improved while the calculation area is reduced accordingly, successfully breaking the trade-off relationship between calculation speed and area in hardware implementation.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An asynchronous CIOS modular multiplication algorithm, characterized in that: The steps include: j The three small loops are combined to eliminate the need for j The data of the first two small cycles are temporarily stored. j The calculation of the third small loop is integrated in j In the second stage of pipeline after the second small cycle calculation, a two-stage pipeline is formed. j After the first small loop of j The second small loop starts the first round of calculation and completes j The assignment of the third small loop, at the same time, j The first small loop of starts the second round of calculation, and so on; CIOS modular multiplication algorithm i The pipeline of the large loop internal calculation completes parallel calculation through asynchronous circuits. i is the number of large loops of the CIOS modular multiplication algorithm, j is the number of small loops of the CIOS modular multiplication algorithm.

2. The asynchronous CIOS modular multiplication algorithm according to claim 1, characterized in that: The asynchronous controller in the asynchronous circuit adopts a click control unit.

3. An asynchronous modular multiplication architecture for implementing the asynchronous CIOS modular multiplication algorithm of claim 1 or 2, characterized in that: The asynchronous modular multiplication architecture uses a coarse-grained asynchronous micro-pipeline design method to build an asynchronous micro-pipeline. The asynchronous micro-pipeline includes the following basic structures: FIFO: First-in-first-out pipeline structure; Fork: A branch structure that inputs one channel and sends it to multiple output channels according to different situations; Merge: A merging structure where multiple inputs are arbitrated according to different situations and then sent to one output; The Fork includes CopyFork and CondFork, and the Merge includes WaitMerge and MutexMerge; The basic structure is used in combination in the asynchronous circuit implementation process of modular multiplication. The cyclic calculation in the asynchronous CIOS modular multiplication algorithm is realized by combining a MutexMerge, a FIFO and a CondFork, and the parallel calculation in the asynchronous CIOS modular multiplication algorithm is realized by a CopyFork combined with multiple FIFOs and WaitMerge.

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