Dormancy awakening control device, chip, chip single board and chip dormancy awakening method

Abstract

The invention discloses a dormancy awakening control device, a chip, a chip single board and a chip dormancy awakening method, and belongs to the technical field of chips. The sleep wake-up control device comprises an OR logic circuit and a latch. The output end of the OR logic circuit is connected with the first input end of the latch; the second input end of the latch is used for receiving a chip overall dormancy signal; the output end of the latch is connected with a first power supply; the first power supply is used for supplying power to the chip; under the condition that the second input end of the latch receives a chip overall dormancy signal, an output signal of the output end of the latch is in a first level state; the output signal in the first level state is used for triggering the first power supply to be powered down and switching to the second power supply to supply power to the sleep wake-up control device and the wake-up units of the physical layers of the ports included in the chip, so that the whole chip is sleep. According to the sleep wake-up control device disclosed by the invention, the overall power-off sleep of the chip can be realized, so that the power consumption of the chip is reduced.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a sleep and wake-up control device. Background Art

[0002] Generally, when one or more ports in a chip stop working, a portion of the circuits in the chip connected to the stopped ports are powered off and put into hibernation based on the TC10 protocol.

[0003] However, when all ports in the chip stop working, if only part of the circuits in the chip connected to the stopped ports are powered off and put into sleep mode, there will still be non-sleep circuits in the chip, resulting in the entire chip still generating high power consumption even if all ports in the chip have stopped working. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the related art. To this end, the present application proposes a sleep wake-up control device, which outputs an output signal that triggers the first power supply to power off, so as to put the chip into sleep mode as a whole, thereby reducing the power consumption of the chip.

[0005] In a first aspect, the present application provides a sleep-wake-up control device, the sleep-wake-up control device comprising an OR logic circuit and a latch;

[0006] The output end of the OR logic circuit is connected to the first input end of the latch; the second input end of the latch is used to receive the chip overall sleep signal; the output end of the latch is connected to the first power supply; the first power supply is used to supply power to the chip;

[0007] When the second input end of the latch receives the chip as a whole sleep signal, the output signal of the output end of the latch is in a first level state; the output signal in the first level state is used to trigger the first power supply to power off and switch to the second power supply to power the sleep and wake-up control device and the wake-up units of the physical layers of each port included in the chip, so as to put the chip as a whole into sleep mode.

[0008] According to the sleep / wake-up control device of the present application, when the second input end of the latch receives a chip-wide sleep signal, the output signal of the output end of the latch is in a first level state, and the output signal in the first level state triggers the first power supply to be powered off, so that all circuits and components in the chip except the sleep / wake-up control device and the wake-up units of the physical layers of each port included in the chip are powered off, thereby reducing the power consumption of the chip.

[0009] According to an embodiment of the present application, the first input end of the OR logic circuit is used to receive a chip wake-up signal sent by the first control device;

[0010] When the second input end of the latch does not receive the chip overall sleep signal and the first input end of the OR logic circuit receives the chip wake-up signal, the output signal of the output end of the latch is in a second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0011] According to an embodiment of the present application, each second input end of the OR logic circuit is used to receive a power-up and power-down indication signal output by the physical layer of the port;

[0012] When any of the power-on and power-off indication signals is in the first level state and the second input end of the latch has not received the chip overall sleep signal, the output signal of the output end of the latch is in the second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0013] In a second aspect, the present application provides a chip, the chip comprising the sleep and wake-up control device as described in the first aspect, a second control device and a register;

[0014] The output end of the second control device is connected to the input end of the register; the output end of the register is connected to the second input end of the latch;

[0015] The second control device is used to control the register to output a chip overall sleep signal.

[0016] According to the chip of the present application, the second control device controls the register through the connection between the output end of the second control device and the input end of the register, so that the register sends a chip-wide sleep signal to the latch in the sleep-wake-up control device. When the second input end of the latch receives the chip-wide sleep signal, the output signal of the output end of the latch is in a first level state, and the output signal in the first level state triggers the first power supply to be powered off to put the chip into sleep mode as a whole, thereby reducing the power consumption of the chip.

[0017] According to one embodiment of the present application, the chip further includes M port physical layers; wherein M is a positive integer;

[0018] The second control device is specifically used to control the register to output a chip overall sleep signal when the physical layers of the M ports all stop working.

[0019] According to an embodiment of the present application, each of the port physical layers is configured to output a power-on / power-off indication signal in a first level state upon receiving a remote wake-up instruction.

[0020] In a third aspect, the present application provides a chip board, the chip board comprising the chip as described in the second aspect, a first power supply and a second power supply;

[0021] The output port of the first power supply is connected to the chip; the voltage output port of the second power supply is connected to the chip.

[0022] According to the chip board of the present application, when the output signal of the output end of the latch is in the first level state, the output signal in the first level state triggers the first power supply on the chip board to power off so that the entire chip is in sleep mode, and only the second power supply supplies power to the sleep wake-up control device and the wake-up units of the physical layers of each port included in the chip, thereby reducing the power consumption of the chip.

[0023] According to one embodiment of the present application, the chip board includes a first control device;

[0024] The first control device is connected to a first input terminal of the OR logic circuit;

[0025] The first control device is used for sending a chip wake-up signal to the first input end of the OR logic circuit when it is determined that the chip needs to be locally woken up.

[0026] In a fourth aspect, the present application provides a chip sleep and wake-up method based on the chip described in the second aspect, the method comprising:

[0027] When determining that the physical layers of the M ports have all stopped working, the second control device controls the register to send a chip overall sleep signal to the latch in the sleep and wake-up control device;

[0028] When the latch receives the chip as a whole sleep signal at the second input end of the latch, the output signal at the output end of the latch is set to a first level state; wherein the output signal in the first level state triggers the first power supply to power off and switch to the second power supply to supply power to the sleep and wake-up control device and the wake-up units of the physical layers of each port included in the chip, so as to put the chip as a whole into sleep mode.

[0029] According to the chip sleep and wake-up method of the present application, when the second input end of the latch receives a chip sleep signal as a whole, the output signal of the output end of the latch is in a first level state, and the output signal in the first level state triggers the first power supply to be powered off, so that all the circuits and components in the chip except the sleep and wake-up control device and the wake-up units of the physical layers of each port included in the chip are powered off, so that the chip as a whole is in sleep mode, thereby reducing the power consumption of the chip.

[0030] According to an embodiment of the present application, the chip sleep and wake-up method further includes:

[0031] When the second input end of the latch does not receive the chip overall sleep signal and the first input end of the logic circuit in the sleep wake-up control device receives the chip wake-up signal, the latch sets the output signal of the output end of the latch to a second level state; the output signal of the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0032] According to an embodiment of the present application, the chip sleep and wake-up method further includes:

[0033] The OR logic circuit obtains the power-up and power-down indication signal sent by the physical layer of the port through each second input terminal;

[0034] When any of the power-on and power-off indication signals is in the first level state and the second input end of the latch has not received the chip overall sleep signal, the output signal of the output end of the latch is set to the second level state; the output signal of the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0035] In a fifth aspect, the present application provides a vehicle, comprising the sleep and wake-up control device as described in the first aspect, or the chip as described in the second aspect, or the chip board as described in the third aspect; or the vehicle executes the chip sleep and wake-up method as described in the fourth aspect.

[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0038] Figure 1 It is a structural schematic diagram of a sleep and wake-up control device provided in an embodiment of the present application;

[0039] Figure 2It is a structural schematic diagram of a sleep and wake-up control device provided in an embodiment of the present application;

[0040] Figure 3 It is a structural schematic diagram of a sleep and wake-up control device provided in an embodiment of the present application;

[0041] Figure 4 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0042] Figure 5 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0043] Figure 6 It is a schematic diagram of the structure of a chip board provided in an embodiment of the present application;

[0044] Figure 7 It is a schematic diagram of the structure of a chip board provided in an embodiment of the present application;

[0045] Figure 8 It is a structural schematic diagram of a sleep and wake-up control device provided in an embodiment of the present application;

[0046] Fig. 9 This is a schematic diagram of the principle of a chip local wake-up provided in an embodiment of the present application;

[0047] Fig.10 This is a schematic diagram of the principle of remote wake-up of a chip provided in an embodiment of the present application;

[0048] Fig.11 This is a schematic diagram of the principle of chip hibernation provided in an embodiment of the present application;

[0049] Fig.12 It is a flowchart of a chip sleep wake-up method provided in an embodiment of the present application;

[0050] Fig.13 It is a hardware schematic diagram of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0052] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0053] In conjunction with the accompanying drawings, the sleep / wake-up control device, chip, chip board, chip sleep / wake-up method and vehicle provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios.

[0054] The chip sleep awakening method can be applied to a terminal, and can be specifically executed by hardware or software in the terminal. The terminal can be arranged on a vehicle.

[0055] like Figure 1 As shown, the sleep / wake-up control device 100 includes an OR logic circuit 110 and a latch 120; wherein the output terminal 111 of the OR logic circuit 110 is connected to the first input terminal 121 of the latch 120; the second input terminal 122 of the latch 120 is used to receive the chip overall sleep signal; the output terminal 123 of the latch 120 is connected to the first power supply; the first power supply is used to supply power to the chip.

[0056] In actual implementation, the OR logic circuit 110 in the sleep / wake-up control device 100 includes a first input terminal, a second input terminal and an output terminal, the first input terminal of the OR logic circuit 110 is connected to the first control device of the chip, the second input terminal of the OR logic circuit 110 is connected to the port physical layer of the chip, and the output terminal of the OR logic circuit is connected to the first input terminal 121 of the latch 120. The latch 120 includes a first input terminal 121, a second input terminal 122 and an output terminal 123, the second input terminal 122 of the latch 120 is connected to the second control device in the chip, and the output terminal 123 of the latch 120 is connected to the first power supply.

[0057] When the second input terminal 122 of the latch 120 receives a chip-wide sleep signal, the output signal of the output terminal 123 of the latch 120 is in a first level state; the output signal in the first level state is used to trigger the first power supply to power off and switch to the second power supply to power the sleep and wake-up control device 100 and the wake-up units of the physical layers of each port included in the chip, so as to put the chip into sleep mode as a whole.

[0058] In actual execution, when the second input terminal 122 of the latch 120 receives the chip overall sleep signal, any signal received by the first input terminal 121 of the latch 120 or sent by the output terminal 111 of the logic circuit 110 will not affect the output result of the latch 120, that is, when the second input terminal 122 of the latch 120 receives the chip overall sleep signal, no matter what signal is received by the first input terminal 121 of the latch 120, the output signal of the output terminal 123 of the latch 120 is in the first level state, wherein the first level state may be a low level state.

[0059] In actual execution, when the port physical layer of the chip cannot receive a sleep instruction, the port physical layer of the chip always outputs a power-up and power-down indication signal of the first level state to the second input port of the OR logic circuit 110, and in the absence of intervention by the latch 120, the power-up and power-down indication signal of the first level state received by the OR logic circuit 110 instructs the first power supply to continue to supply power to the chip, resulting in the first power supply continuing to supply power to the chip even if all port physical layers in the chip are not working, so that the chip still generates power consumption. In one embodiment of the present application, the output terminal 111 of the OR logic circuit 110 is connected to the first input terminal 121 of the latch 120, the second input terminal 122 of the latch 120 is connected to the second control device in the chip, and the output terminal 123 of the latch 120 is connected to the first power supply. When the second control device determines that the physical layer of all ports of the chip are not working, it controls the register to send a chip overall sleep signal to the second input terminal 122 of the latch 120, so that even if the port physical layer of the chip cannot receive the sleep instruction, it still outputs the power-on and power-off indication signal of the first level state to the second input port of the OR logic circuit 110, and the output signal of the output terminal 123 of the latch 120 is changed to the first level state; the output signal in the first level state triggers the first power supply to power off and switch to the second power supply to supply power to the sleep wake-up control device 100 and the wake-up units of the physical layers of each port included in the chip, so that the chip as a whole is put into sleep.

[0060] It should also be noted here that the latch 120 can be a Set-Reset latch (SR latch) or a JK latch, etc., the first power supply can be a low-dropout regulator (LDO), such as a main low-dropout regulator (MAIN LDO), the second power supply can be a low-dropout regulator different from the first power supply, such as a sub-low-dropout regulator (SUB LDO), and the wake-up unit of the physical layer of each port can include an analog front-end circuit (Analog Front End, AFE).

[0061] According to the sleep / wake-up control device of the present application, when the second input end of the latch receives a chip-wide sleep signal, the output signal of the output end of the latch is in a first level state, and the output signal in the first level state triggers the first power supply to be powered off, so that all circuits and components in the chip except the sleep / wake-up control device and the wake-up units of the physical layers of each port included in the chip are powered off, thereby reducing the power consumption of the chip.

[0062] In some embodiments, Figure 2 As shown, the first input terminal 112 of the OR logic circuit 110 is used to receive a chip wake-up signal sent by the first control device; when the second input terminal 122 of the latch 120 does not receive the chip overall sleep signal and the first input terminal 112 of the OR logic circuit 110 receives the chip wake-up signal, the output signal of the output terminal 123 of the latch 120 is in a second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0063] It should be noted that the first control device may be a microcontroller unit (MCU). The second level state may be a high level state, and specifically, the second level state may be a level state higher than the first level state.

[0064] In some embodiments, Figure 3 As shown, each second input terminal 113-i (i is a positive integer less than or equal to N, N is a positive integer) of the OR logic circuit 110 is respectively used to receive a power-on and power-off indication signal output by a port physical layer; when any power-on and power-off indication signal is in the first level state and the second input terminal 122 of the latch 120 has not received the chip overall sleep signal, the output signal of the output terminal 123 of the latch 120 is in the second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0065] In actual implementation, the OR logic circuit 110 includes N second input terminals, which are the second input terminal 113-1, the second input terminal 113-2, the second input terminal 113-3 ... the second input terminal 113-N in sequence. Each of the N second input terminals of the OR logic circuit 110 is connected to a port physical layer of the chip, and each of the N second input terminals 113-i of the OR logic circuit 110 is used to receive a power-up and power-down indication signal output by a port physical layer. When the power-up and power-down indication signal received by any of the N second input terminals of the OR logic circuit 110 is in the first level state, and the second input terminal 122 of the latch 120 does not receive the chip overall sleep signal, the output signal of the output terminal 123 of the latch 120 is in the second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0066] It should also be noted here that the port physical layer may be a physical link layer supporting the TC10 protocol.

[0067] like Figure 4 As shown, the chip 200 includes a sleep and wake-up control device 210, a second control device 220 and a register (Register, REG) 230; the output end 221 of the second control device 220 is connected to the input end 231 of the register 230; the output end 232 of the register 230 is connected to the second input end 211-1 of the latch 211; the second control device 220 is used to control the register 230 to output the chip overall sleep signal.

[0068] It should be noted here that the second control device 220 may be a central processing unit (CPU) disposed inside the chip 200 .

[0069] According to the chip of the present application, the second control device controls the register to send a chip overall sleep signal to the latch in the sleep wake-up control device through the connection between the register and the second input end of the latch in the sleep wake-up control device. When the second input end of the latch receives the chip overall sleep signal, the output signal of the output end of the latch is in a first level state, and the output signal in the first level state triggers the first power supply to be powered off to make the chip as a whole sleep, thereby reducing the power consumption of the chip.

[0070] In some embodiments, Figure 5 As shown, the chip also includes M port physical layers 24i (i is a positive integer less than or equal to M); wherein M is a positive integer; the second control device 220 is specifically used to control the register 230 to output a chip overall sleep signal when all the M port physical layers 24i stop working.

[0071] In actual execution, when the M port physical layers 24i all stop working, the second control device 220 controls the register 230 through the connection between the output terminal 221 of the second control device 220 and the input terminal 231 of the register 230, so that the chip overall sleep signal is sent to the second input terminal 211-1 of the latch 211 through the output terminal 232 of the register 230.

[0072] In actual execution, the second control device 220 pre-configures a signal for controlling the latch 211 in the register 230, such as a chip overall sleep signal, and a signal trigger condition. When the second control device 220 sends a trigger signal to the register 230 through the connection between the output terminal 221 of the second control device 220 and the input terminal 231 of the register 230 when all the M port physical layers 24i stop working, the register 230 is triggered to send a chip overall sleep signal to the second input terminal 211-1 of the latch 211 through the output terminal 232 of the register 230. The above process is a way for the second control device 220 to indirectly control the chip to sleep as a whole through the register 230.

[0073] In some embodiments, each of the M port physical layers 24i (i is a positive integer less than or equal to M) is configured to output a power-up and power-down indication signal in a first level state upon receiving a remote wake-up instruction.

[0074] In actual implementation, the sleep and wake-up control device 210 may also include an OR logic circuit, the OR logic circuit may include N second input terminals, each of the N second input terminals of the OR logic circuit is connected to a port physical layer 24i of the chip, and each of the N second input terminals of the OR logic circuit is used to receive the power-up and power-down indication signal output by a port physical layer 24i. In the case where any port physical layer 24i of the M port physical layers 24i (i is a positive integer less than or equal to M) receives a remote wake-up instruction, the port physical layer 24i that receives the remote wake-up instruction may output a power-up and power-down indication signal of a first level state. In the case where the power-up and power-down indication signal received by any second input terminal of the N second input terminals of the OR logic circuit is in the first level state, and the second input terminal 211-1 of the latch 211 does not receive the chip overall sleep signal, the output signal of the output terminal of the latch 211 is in the second level state; the output signal of the second level state is used to switch to the first power supply to power the chip 200 and wake up the chip 200.

[0075] In actual implementation, when the chip is awakened, the second control device 220 can also be used to determine the port physical layer to be operated among the M port physical layers 24i, and supply power to the port physical layer to be operated by the first power supply.

[0076] In actual implementation, after the chip 200 is awakened, the register 230 can be used to send an output signal in a second level state to any port physical layer among the M port physical layers 24i (i is a positive integer less than M), and the output signal in the second level state is used to instruct the port physical layer to send a wake-up pulse (Wake-Up Pusle, WUP).

[0077] like Figure 6 As shown, the chip board 300 includes a chip 310 , a first power supply 320 and a second power supply 330 ; an output port 321 of the first power supply 320 is connected to the chip 310 ; and an output port 331 of the second power supply 330 is connected to the chip 310 .

[0078] In actual implementation, the chip 310 may include a sleep and wake-up control device, a register, and a second control device. The sleep and wake-up control device may include an OR logic circuit and a latch; wherein the output end of the OR logic circuit is connected to the first input end of the latch; the second input end of the latch is connected to the output end of the register, the input end of the register is connected to the output end of the second control device, and the output end of the latch is connected to the first power supply 320. The second input end of the latch can be used to receive a chip overall sleep signal; when the second control device controls the latch to send a chip overall sleep signal to the second input end of the latch, the output signal of the output end of the latch is in a first level state; the output signal in the first level state is used to trigger the first power supply 320 to power off and switch to the second power supply 330 to supply power to the sleep and wake-up control device and the wake-up units of the physical layer of each port included in the chip 310, so as to put the chip 310 into sleep mode as a whole.

[0079] According to the chip board of the present application, when the output signal of the output end of the latch is in the first level state, the output signal in the first level state triggers the first power supply on the chip board to power off so that the entire chip is in sleep mode, and only the second power supply supplies power to the sleep wake-up control device and the wake-up units of the physical layers of each port included in the chip, thereby reducing the power consumption of the chip.

[0080] In some embodiments, Figure 7 As shown, the chip board 300 also includes a first control device 340; the first control device 340 is connected to the first input terminal 311 of the OR logic circuit; the first control device 340 is used to send a chip wake-up signal to the first input terminal 311 of the OR logic circuit when it is determined that the chip 310 needs to be locally awakened.

[0081] In actual execution, after the first control device 340 sends a chip wake-up signal to the first input terminal 311 of the OR logic circuit, when the second input terminal of the latch does not receive the chip overall sleep signal and the first input terminal 311 of the OR logic circuit receives the chip wake-up signal, the output signal of the output terminal of the latch is in a second level state; the output signal in the second level state is used to switch to the first power supply 320 to power the chip 310, thereby waking up the chip 310.

[0082] In some embodiments, Figure 8 The sleep-wake control device shown includes a Set-Reset latch and an OR logic circuit (OR circuit), wherein the OR circuit includes a first input terminal (e.g., a WAKE port), N second input terminals (e.g., INH33_i, where i is a positive integer less than or equal to N) and a power-on reset (Power-on Reset, POR) port. When the chip is powered on, the OR logic circuit receives a power-on signal through the POR port, wherein the power-on signal received through the POR port is used to ensure that the signal initially outputted from the OR logic disconnect output terminal after power-on is in a low level state. The output terminal of the OR circuit is connected to the S terminal of the SR latch.

[0083] like Fig. 9 As shown, the WAKE port in the OR circuit is connected to the first control device (such as MCU) outside the chip. When the MCU determines that the chip needs to be woken up locally, it sends a chip wake-up signal to the WAKE port of the OR circuit, and the voltage of the chip wake-up signal can be 3.3V. When the second input end (such as the R end) of the latch does not receive the chip overall sleep signal and the WAKE port of the OR logic circuit receives the chip wake-up signal, the output signal of the output end (such as the INH port) of the latch is in the second level state (such as an output signal outputting a 3.3V voltage); the output signal in the second level state is used to switch to the first power supply (such as MAIN LDO) to power the chip and wake up the chip. After the chip is awakened, the register (REG) can send an output signal in the second level state (such as a WAKE_IN signal with a voltage of 1.1V) to the chip port physical layer (such as T1_PHY1), and the output signal in the second level state is used to instruct the port physical layer to send a remote wake-up instruction (such as a WUP instruction) to the outside. In addition, after the chip is awakened, the central processing unit (CPU) determines the port physical layer that needs to work in the chip, and powers on and wakes up the port physical layer that needs to work; correspondingly, the second power supply (SUB LDO) is controlled to stop supplying power, and the first power supply (MAIN LDO) is controlled to keep supplying power to the port physical layer that does not need to work.

[0084] In some embodiments, Fig.10As shown, each of the N second input terminals is connected to a port physical layer of the chip. According to the TC10 protocol, when the port physical layer receives a wake-up pulse, the port physical layer sends an output signal of a second level state (e.g., a 3.3V INH33 signal) to the second input terminal of the connected OR circuit. The output terminal of the OR circuit is connected to the first input terminal (e.g., the S terminal) of the SR latch. When any of the N second input terminals of the OR circuit and the POR port receives an output signal of a second level state, the output signal of the output terminal of the latch (e.g., the INH port) is in a second level state, and the output signal of the output terminal of the latch is in a second level state; the output signal of the second level state is used to switch to the first power supply to supply power to the chip and wake up the chip.

[0085] In some embodiments, Fig.11 As shown, the second input end (e.g., R end) of the SR latch is connected to the second control device of the chip (e.g., central processing unit). When the physical layer of any port of the chip receives a sleep instruction (e.g., LPS instruction), the physical layer of the port is powered off and put into sleep. When the physical layers of all ports of the chip are in sleep mode, the central processing unit sends a chip overall sleep signal (e.g., SW_POWER_CTRL signal) to the R end of the SR latch. When the R end of the SR latch receives the SW_POWER_CTRL signal, the output signal of the output end of the SR latch is in a first level state; the output signal in the first level state is used to trigger the MAIN LDO to power off and switch to the SUB LDO to supply power to the sleep wake-up control device and the wake-up units of the physical layers of each port included in the chip, so as to put the chip into sleep mode as a whole.

[0086] The chip sleep and wake-up method provided in the embodiment of the present application can be executed by an electronic device or a functional module or functional entity in the electronic device that can implement the chip sleep and wake-up method. The electronic devices mentioned in the embodiment of the present application include but are not limited to mobile phones, tablet computers, computers, cameras and wearable devices. The chip sleep and wake-up method provided in the embodiment of the present application is described below using the electronic device as an example of the execution subject.

[0087] like Fig.12 As shown, the chip sleep and wake-up method includes step 510 and step 520.

[0088] Step 510: When the second control device determines that the physical layers of the M ports have all stopped working, the control register sends a chip overall sleep signal to the latch in the sleep and wake-up control device.

[0089] In actual implementation, the chip may include a second control device, a register, M port physical layers, and a sleep wakeup control device, wherein the sleep wakeup control device includes a latch. The second control device is connected to the latch in the sleep wakeup control device through the register. Specifically, the output end of the second control device may be connected to the input end of the register, and the output end of the register may be connected to the second input port of the latch.

[0090] In actual implementation, the second control device may be a central processing unit provided in the chip. When determining that the physical layers of the M ports have all stopped working, the second control device may control the register by connecting the output end of the second control device with the input end of the register, so that the register sends a chip overall sleep signal to the latch in the sleep and wake-up control device.

[0091] Step 520: When the latch receives a chip-wide sleep signal at the second input end of the latch, the output signal at the output end of the latch is set to a first level state; wherein the output signal in the first level state triggers the first power supply to power off and switch to the second power supply to supply power to the sleep wake-up control device and the wake-up units of the physical layers of each port included in the chip, so as to put the chip into sleep mode as a whole.

[0092] In actual execution, the output end of the latch is connected to the first power supply, and the output end of the first power supply is connected to the chip. When the latch receives a chip sleep signal at the second input end of the latch, the output signal of the output end of the latch is set to the first level state. At this time, after the first power supply receives the output signal of the first level, the power supply to the chip is cut off to put the chip into sleep mode.

[0093] According to the chip sleep and wake-up method of the present application, when the second input end of the latch receives a chip sleep signal as a whole, the output signal of the output end of the latch is in a first level state, and the output signal in the first level state triggers the first power supply to be powered off, so that all the circuits and components in the chip except the sleep and wake-up control device and the wake-up units of the physical layers of each port included in the chip are powered off, so that the chip as a whole is in sleep mode, thereby reducing the power consumption of the chip.

[0094] In some embodiments, when the second input end of the latch does not receive a chip overall sleep signal and the first input end of the or logic circuit in the sleep wake-up control device receives a chip wake-up signal, the output signal of the output end of the latch is set to a second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0095] It should be noted here that the sleep and wake-up control device may also include an OR logic circuit, wherein the output end of the OR logic circuit is connected to the first input end of the latch, or the first input end of the logic circuit is connected to the first control device. When the second input end of the latch does not receive the chip overall sleep signal and the first input end of the OR logic circuit receives the chip wake-up signal, the output signal of the output end of the latch is in the second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0096] In some embodiments, the logic circuit obtains the power-on and power-off indication signals sent by the physical layer of the port through each second input terminal; when any power-on and power-off indication signal is in the first level state and the second input terminal of the latch has not received the chip overall sleep signal, the output signal of the output terminal of the latch is set to the second level state; the output signal in the second level state is used to switch to the first power supply to power the chip and wake up the chip.

[0097] It should be noted here that each of the N second input terminals of the OR logic circuit is connected to a port physical layer. After each second input terminal of the OR logic circuit obtains the power-up and power-down indication signal sent by the port physical layer, when any power-up and power-down indication signal is in the first level state and the second input terminal of the latch does not receive the chip overall sleep signal, the output signal of the output terminal of the latch is set to the second level state.

[0098] It should also be noted here that after the chip is awakened, the register can send an output signal in a second level state to any port physical layer among the M port physical layers 23i (i is a positive integer less than or equal to M), and the output signal in the second level state is used to instruct the port physical layer to send a wake-up pulse.

[0099] In some embodiments, the embodiments of the present application also provide a vehicle having a sleep-wake-up control device, or a chip, or a chip board; the vehicle executes a method that can be used for chip sleep-wake-up.

[0100] The sleep and wake-up control device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0101] The sleep / wake-up control device in the embodiment of the present application may be a device having an operating system. The operating system may be a Microsoft (Windows) operating system, an Android (Android) operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0102] In some embodiments, Fig.13 As shown, an embodiment of the present application also provides an electronic device 600, including a processor 601, a memory 602, and a computer program stored in the memory 602 and executable on the processor 601. When the program is executed by the processor 601, each process of the above-mentioned chip sleep and wake-up method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0103] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0104] An embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned chip sleep and wake-up method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0105] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0106] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned chip sleep and wake-up method when executed by a processor.

[0107] The processor is the processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0108] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned chip sleep and wake-up method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0109] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0110] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0111] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0112] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

[0113] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0114] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A sleep and wake-up control device, characterized in that: The sleep-wake-up control device comprises an OR logic circuit and a latch; The output end of the OR logic circuit is connected to the first input end of the latch; the second input end of the latch is used to receive the chip overall sleep signal; the output end of the latch is connected to the first power supply; the first power supply is used to supply power to the chip; When the second input end of the latch receives the chip as a whole sleep signal, the output signal of the output end of the latch is in a first level state; the output signal in the first level state is used to trigger the first power supply to power off and switch to the second power supply to power the sleep and wake-up control device and the wake-up units of the physical layers of each port included in the chip, so as to put the chip as a whole into sleep mode.

2. The sleep and wake-up control device according to claim 1, characterized in that: The first input end of the OR logic circuit is used to receive a chip wake-up signal sent by the first control device; When the second input end of the latch does not receive the chip overall sleep signal and the first input end of the OR logic circuit receives the chip wake-up signal, the output signal of the output end of the latch is in a second level state; The output signal in the second level state is used to switch to the first power supply to supply power to the chip, so as to wake up the chip.

3. The sleep / wake-up control device according to claim 1 or 2, characterized in that: Each second input end of the OR logic circuit is used to receive a power-up and power-down indication signal output by the physical layer of the port; When any of the power-on and power-off indication signals is in the first level state and the second input end of the latch does not receive the chip overall sleep signal, the output signal of the output end of the latch is in the second level state; The output signal in the second level state is used to switch to the first power supply to supply power to the chip, so as to wake up the chip.

4. A chip, characterized in that: The device comprises a sleep / wake-up control device as claimed in any one of claims 1 to 3, and a second control device and a register; The output end of the second control device is connected to the input end of the register; the output end of the register is connected to the second input end of the latch; The second control device is used to control the register to output a chip overall sleep signal.

5. The chip according to claim 4, characterized in that: The chip also includes M port physical layers; wherein M is a positive integer; The second control device is specifically used to control the register to output a chip overall sleep signal when the physical layers of the M ports all stop working.

6. The chip according to claim 5, characterized in that: Each of the port physical layers is used to output a power-on / power-off indication signal in a first level state when receiving a remote wake-up instruction.

7. A chip single board, characterized in that: The chip board comprises the chip according to any one of claims 4 to 6, a first power supply and a second power supply; The output port of the first power supply is connected to the chip; the voltage output port of the second power supply is connected to the chip.

8. The chip board according to claim 7, characterized in that: The chip board includes a first control device; The first control device is connected to a first input terminal of the OR logic circuit; The first control device is used for sending a chip wake-up signal to the first input end of the OR logic circuit when it is determined that the chip needs to be locally woken up.

9. A chip sleep wakeup method based on the chip according to any one of claims 4 to 6, characterized in that: include: When the second control device determines that the physical layers of the M ports have all stopped working, the control register sends a chip overall sleep signal to the latch in the sleep wake-up control device; When the latch receives the chip as a whole sleep signal at the second input end of the latch, the output signal at the output end of the latch is set to a first level state; wherein the output signal in the first level state triggers the first power supply to power off and switch to the second power supply to supply power to the sleep and wake-up control device and the wake-up units of the physical layers of each port included in the chip, so as to put the chip as a whole into sleep mode.

10. The chip sleep awakening method according to claim 9, characterized in that: The method further comprises: When the second input end of the latch does not receive the chip overall sleep signal and the first input end of the logic circuit in the sleep wake-up control device receives the chip wake-up signal, the latch sets the output signal of the output end of the latch to a second level state; the output signal of the second level state is used to switch to the first power supply to power the chip and wake up the chip.

11. The chip sleep awakening method according to claim 9 or 10, characterized in that: The method further comprises: The OR logic circuit obtains the power-up and power-down indication signal sent by the physical layer of the port through each second input terminal; When any power-on or power-off indication signal is in the first level state and the second input end of the latch has not received the chip overall sleep signal, the output signal of the output end of the latch is set to the second level state; the output signal of the second level state is used to switch to the first power supply to power the chip and wake up the chip.

12. A vehicle, characterized in that: The vehicle has the sleep-wake-up control device described in any one of claims 1-3, or the chip described in any one of claims 4-6, or the chip board described in any one of claims 7-8; or the vehicle executes the chip sleep-wake-up method described in any one of claims 9-11.

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