Security assessment method and system for logic locking encryption circuit

Abstract

The invention relates to the technical field of circuit safety, and provides a safety evaluation method and system for a logic locking encryption circuit, and the method comprises the steps: extracting a key bit, a logic gate and a logic cone set in the logic locking encryption circuit; finding a key bit capable of being logically blocked in the key bits; obtaining an X state filling object in an automatic test vector generation algorithm based on the logically blocked key bit; traversing the logic cone set, and generating a first test vector for the key bit in the logic cone based on an automatic test vector generation algorithm to obtain an ideal response; assuming a fixed fault for the current key bit, and generating a second test vector again based on the automatic test vector generation algorithm to obtain an actual response; comparing the actual response with the ideal response to obtain a deducable key; and calculating the proportion of the inferred key bit in the key bit, and comparing the proportion with a preset threshold value to obtain a security evaluation result. According to the invention, the safety evaluation efficiency of the logic locking circuit is obviously improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit safety technology, and in particular to a safety assessment method and system for a logic locking encryption circuit. Background Art

[0002] The globalization of integrated circuit (IC) design and manufacturing processes has promoted the rapid development of electronic products, but at the same time, it has also brought major challenges in intellectual property protection. In this global supply chain environment, the design and manufacturing of integrated circuits often involve multiple different manufacturers, which increases the risk of design leakage and intellectual property theft. In order to meet these challenges, logic locking technology has emerged. This technology embeds key-controlled logic gates in IC circuits so that the circuit can only work normally after the correct key is input, thereby encrypting and protecting the chip functions. However, with the continuous advancement of attack methods, the existing logic locking technology faces severe security threats. Attackers can crack the locking mechanism in a variety of ways, including path sensitization attacks, SAT attacks, and fault injection attacks based on automatic test vector generation (ATPG). These attack methods often bypass the locking mechanism by obtaining circuit keys or using injected faults, thereby endangering the overall security of the circuit and posing severe challenges to the intellectual property protection of chips.

[0003] The existing evaluation methods for logic-locked encryption circuits are difficult to adapt to the trend of increasing number of keys and complicated locking logic when facing complex and high-security locking circuits, resulting in inefficient evaluation of encryption circuit security. For example, if you want to evaluate the risk of attacks based on fault injection, you need a lot of computing resources to simulate and implement it. During the evaluation process, you may need to introduce a large number of fault injection assumptions and variables, especially when facing multiple key quantities and multi-level locking logic. This not only increases the difficulty of execution and makes the evaluation inefficient, but may also affect the accuracy and reliability of the evaluation results. Summary of the invention

[0004] In order to overcome the defect of low efficiency of security assessment of logic lock circuit in the above-mentioned prior art, the present invention provides a security assessment method and system for logic lock encryption circuit.

[0005] In order to achieve the above technical effects, the technical solution of the present invention is as follows:

[0006] A security assessment method for a logic-locked encryption circuit comprises the following steps:

[0007] S1, extracting key bits and logic gates in the logic lock encryption circuit; dividing the logic cone based on the output nodes in the logic lock encryption circuit to obtain a logic cone set;

[0008] S2, dividing the key bits into logically blockable key bits and non-logically blockable key bits; obtaining an X-state filling object in an automatic test vector generation algorithm based on the logically blockable key bits;

[0009] S3, searching the logical cone containing the least key bits in the logical cone set;

[0010] S4, traversing the key bit set in the current logic cone, finding the key bit with the most X-state filling objects, generating a first test vector for the key bit based on an automatic test vector generation algorithm, inputting the first test vector into the logic lock encryption circuit to obtain an ideal response; assuming that a stuck-at fault exists for the key bit, regenerating a second test vector based on the automatic test vector generation algorithm, inputting the second test vector into the logic lock encryption circuit to obtain an actual response; and deleting the key bit from the key bit set;

[0011] S5, comparing the actual response with the ideal response to obtain an inferred value of the key bit; taking the key bit whose inferred value is the same as the correct value of the key bit as the inferred key bit, and repeating steps S4 to S5 until the key bit set is empty;

[0012] S6, deleting the current logic cone from the logic cone set, and repeating steps S3 to S6 until the logic cone set is empty;

[0013] S7. Calculate the proportion of the inferable key bits in the key bits, and compare it with a preset threshold to obtain a security assessment result.

[0014] The present invention also provides a security assessment system for a logic-locked encryption circuit, the system comprising:

[0015] Key bit division module: used to extract key bits and logic gates in the logic lock encryption circuit; divide the key bits into logically blockable key bits and non-logically blockable key bits;

[0016] The automatic test vector generation test module: uses the logically blockable key bit as an X-state filling object in the automatic test vector generation algorithm; for any key bit, generates a first test vector based on the automatic test vector generation algorithm, and inputs the first test vector into the logic lock encryption circuit to obtain an ideal response; embeds a fixed-type fault in the current key bit, regenerates a second test vector based on the automatic test vector generation algorithm, and inputs the second test vector into the logic lock encryption circuit to obtain an actual response;

[0017] Key bit inference module: compares the actual response with the ideal response to obtain an inferred value of any key bit, and makes a judgment based on the inferred value and the real value of the key bit. If the comparison results are the same, the key bit is regarded as an inferred key, otherwise, the next key bit is judged until all key bits are traversed;

[0018] Logical lock encryption circuit security assessment module: calculates the proportion of inferable key bits in the key bits, and compares it with a preset threshold to obtain a security assessment result.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention improves the automatic test vector generation algorithm based on key invalidation, and induces the X state of an unspecified bit to occur in a logically blocked key bit when using the automatic test vector generation algorithm to generate a test vector; the number of fault injection points is greatly reduced, unnecessary global scanning is avoided, and evaluation efficiency is improved; then a hypothetical fault sensitization attack is implemented, and an actual response is obtained by assuming that a fault exists at each key bit, and an inferred value is obtained by comparing it with an ideal response. If the inferred value is the same as the real key value, it is considered that the key bit has a high risk; unnecessary fault location is reduced by injecting hypothetical faults, and potential high-risk key bits can be quickly screened out, redundant calculation steps are avoided, and the speed of overall test vector generation and analysis is improved, and the security analysis of the entire encryption system is made more complete and targeted. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a security assessment method for a logic locked encryption circuit according to Example 1.

[0022] Figure 2 This is the logic blocking schematic diagram of the AND gate.

[0023] Figure 3 This is the logical blocking schematic diagram of the OR gate.

[0024] Figure 4 This is the logic blocking schematic diagram of the NAND gate.

[0025] Figure 5 This is the logic blocking schematic diagram of the NOR gate.

[0026] Figure 6 This is a flow chart of a security assessment system for a logic locking encryption circuit according to Example 2. DETAILED DESCRIPTION

[0027] The accompanying drawings are only used for illustrative purposes and are not to be construed as limiting the present invention;

[0028] It is understandable to those skilled in the art that some well-known descriptions may be omitted in the drawings.

[0029] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0030] Example 1

[0031] This embodiment provides a security assessment method for a logic lock encryption circuit, comprising the following steps:

[0032] S1, extracting key bits and logic gates in the logic lock encryption circuit; dividing the logic cone based on the output nodes in the logic lock encryption circuit to obtain a logic cone set;

[0033] S2, dividing the key bits into logically blockable key bits and non-logically blockable key bits; obtaining an X-state filling object in an automatic test vector generation algorithm based on the logically blockable key bits;

[0034] S3, searching the logical cone containing the least key bits in the logical cone set;

[0035] S4, traversing the key bit set in the current logic cone, finding the key bit with the most X-state filling objects, generating a first test vector for the key bit based on an automatic test vector generation algorithm, inputting the first test vector into the logic lock encryption circuit to obtain an ideal response; assuming that a stuck-at fault exists for the key bit, regenerating a second test vector based on the automatic test vector generation algorithm, inputting the second test vector into the logic lock encryption circuit to obtain an actual response; and deleting the key bit from the key bit set;

[0036] S5, comparing the actual response with the ideal response to obtain an inferred value of the key bit; taking the key bit whose inferred value is the same as the correct value of the key bit as the inferred key bit, and repeating steps S4 to S5 until the key bit set is empty;

[0037] S6, deleting the current logic cone from the logic cone set, and repeating steps S3 to S6 until the logic cone set is empty;

[0038] S7. Calculate the proportion of the inferable key bits in the key bits, and compare it with a preset threshold to obtain a security assessment result.

[0039] In this embodiment, by dividing the key bits into logically blockable key bits and non-logically blockable key bits, the efficiency of key analysis is improved, and the filling strategy of the X state of the subsequent test vector generation algorithm is optimized, and the automatic test vector generation algorithm based on key nullification (Key-nullification ATPG Algorithm, KN-ATPG) is realized. By logically blocking the logically blockable key bits, the proportion of uncertain bits in the circuit is reduced, thereby reducing the number of test vectors and generation time, and improving the efficiency of the overall test process; then, the ideal response of any key and the actual response obtained by the pseudo fault are compared to realize the pseudo fault sensitization attack (Pseudo Fault Sensitization Attack, PFSA) to judge the inferability of each key bit, identify the weak key bit, and accurately evaluate the security of each key bit; finally, by counting the proportion of the number of inferable key bits to the total number of key bits, the security of the logic locked encryption circuit can be objectively quantified, and the protection of the circuit can be strengthened in a targeted manner. In addition, the physical damage to the device is reduced due to the significant reduction of the fault injection demand.

[0040] As an exemplary illustration, a graph analysis is performed on the logic lock encryption circuit to obtain the logic gates and key bits in the logic lock encryption circuit.

[0041] In an optional embodiment, the step of dividing the key bits into logically blockable key bits and logically non-blockable key bits includes:

[0042] Find a logic gate directly connected to the output node of the logic lock encryption circuit in the output path of any key bit as the final logic gate, and use the node connected to the output path of the current key bit and the final logic gate as the key bit node, and the remaining input nodes of the final logic gate as the blocking enable nodes;

[0043] Determine the original input with the blocking enable node as the cone top of the logic cone;

[0044] If the original input does not contain other key bits, then the key bit is a logically blockable key bit, otherwise it is a non-logically blockable key bit.

[0045] In this embodiment, by combining the logical properties of the key bit with the circuit structure, by determining the blocking enable node and its original input, and searching for other key bits in the original input to determine whether it is a logically blockable key bit, this hierarchical analysis method makes the classification of key bits more detailed and accurate, and improves the reliability of subsequent analysis and testing.

[0046] In an optional embodiment, the step of obtaining a set of X-state filling objects in an automatic test vector generation algorithm based on the logically blockable key bit comprises:

[0047] For any key bit node in the final logic gate that can logically block the key bit, an original input is determined as the cone top of the logic cone, and the original input is used as an X-state filling object in an automatic test vector generation algorithm.

[0048] In this embodiment, the original input under the same final logic gate as the key bit is also used as an X state filling object, which expands the scope of X filling and reduces the number of subsequent fault injections.

[0049] In an optional embodiment, the stuck-at fault includes a set-0 fault and a set-1 fault.

[0050] In this embodiment, by performing fault injection on the current key bit by setting a fault to 0 or setting a fault to 1 before generating the second test vector, the response change caused by the fault can be detected in a targeted manner during the process of generating the second test vector.

[0051] In an optional embodiment, the step of inputting the first test vector into the logic lock encryption circuit to obtain an ideal response includes:

[0052] Forcing constraints on the key bits that cannot be logically blocked in the first test vector by changing the value of the key bits; logically blocking the key bits of the X state filling bits; and then inputting the first test vector into the logic locking encryption circuit to obtain an ideal response;

[0053] The step of inputting the second test vector into the logic lock encryption circuit to obtain an actual response comprises:

[0054] The key bits in the second test vector that cannot be logically blocked are constrained by changing the values ​​of the key bits; the key bits of the X state filling bits are logically blocked; and the second test vector is input into the logic locking encryption circuit to obtain an ideal response.

[0055] As an exemplary embodiment, the step of enforcing the constraint includes changing the value of the key bit using laser injection.

[0056] In this embodiment, by forcibly constraining the key bits that cannot be logically blocked, it is ensured that the test vector can accurately reflect the true logic state of the circuit, eliminate unnecessary variable interference, and improve the effectiveness of the test results; by logically blocking the X state fill bit, the uncertainty of the input state is reduced, and the complexity of the calculation is reduced. In addition, laser injection is a high-precision operation that can ensure that the value of the key bit is accurately manipulated during the test process, thereby avoiding errors caused by randomness or uncontrollable factors and improving the accuracy and reliability of the test.

[0057] In an optional embodiment, the step of logic blocking includes:

[0058] According to the type of the second logic gate, the original input of the blocking enable node is changed.

[0059] Further optionally, the step of changing the original input of the blocking enable node according to the type of the second logic gate includes:

[0060] If the second logic gate is an AND gate, adjusting the original input to set the blocking enable node value to 0;

[0061] If the second logic gate is an OR gate, adjusting the original input to set the blocking enable node value to 1;

[0062] If the second logic gate is a NAND gate, adjusting the original input to set the blocking enable node value to 0;

[0063] If the second logic gate is a NOR gate, the original input is adjusted to set the blocking enable node value to 1.

[0064] Specifically, Figure 2 As shown in FIG. 1 , it is a logic blocking schematic diagram of the AND gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 0, so that the blocking enable node value is 0, the output of the G3 logic gate is 0, and the key bit is logically blocked.

[0065] like Figure 3 As shown, it is the logic blocking principle diagram of the OR gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 1, so that the blocking enable node value is 1, the output of the G3 logic gate is 1, and the key bit is logically blocked.

[0066] like Figure 4 As shown in FIG. 1 , it is a logic blocking schematic diagram of the NAND gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 0, so that the blocking enable node value is 0, the output of the G3 logic gate is 1, and the key bit is logically blocked.

[0067] like Figure 5 As shown in FIG. 1 , it is a logic blocking schematic diagram of the AND gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 0, so that the blocking enable node value is 0, the output of the G3 logic gate is 1, and the key bit is logically blocked.

[0068] In this embodiment, a logic blocking method is used to make the input of the key bit invalid in the subsequent automatic test vector generation test process, thereby simplifying the complexity of the security test, reducing the dependence on the key bit, and improving the test efficiency.

[0069] In an optional embodiment, the step of comparing the actual response with the ideal response to obtain the inferred value of the key bit includes: if the actual response is different from the ideal response, then the value of the fixed-type fault is used as the inferred value of the key bit; otherwise, the complementary value of the value of the fixed-type fault is used as the inferred value of the key bit.

[0070] In this embodiment, the actual response is compared with the ideal response. If there is a difference between the actual response and the ideal response, it means that the assumed stuck-at fault is successfully transmitted, and the fault value is used as the inferred value of the key bit. Otherwise, it means that the assumed stuck-at fault is not successfully transmitted, and the complementary value of the fault value is used as the inferred value of the key bit. Directly inferring the key based on the actual response change caused by the fault can infer the key information faster and reduce the time and resources required.

[0071] In an optional embodiment, the step of calculating the proportion of inferable key bits in the key bits and comparing it with a preset threshold to obtain a security assessment result includes: if the proportion of inferable key bits in the key bits is greater than the preset threshold, then the security assessment result of the logic-locked encryption circuit is determined to be high risk; otherwise, the security assessment result of the logic-locked encryption circuit is determined to be low risk.

[0072] In this embodiment, a quantitative standard is provided for security evaluation by setting a threshold value, making the evaluation process more objective and standardized. In addition, by inferring the key bits, the encryption algorithm can be optimized or adjusted for these specific key bits.

[0073] Example 2

[0074] This embodiment proposes a security assessment system for a logic-locked encryption circuit, and applies a security assessment method for a logic-locked encryption circuit proposed in Embodiment 1. Figure 6 , which is an architecture diagram of the security assessment system of the logic locking encryption circuit of this embodiment.

[0075] This embodiment provides a security assessment system for a logic locking encryption circuit, including:

[0076] Key bit division module: used to extract key bits and logic gates in the logic lock encryption circuit; divide the key bits into logically blockable key bits and non-logically blockable key bits;

[0077] The automatic test vector generation test module: uses the logically blockable key bit as an X-state filling object in the automatic test vector generation algorithm; for any key bit, generates a first test vector based on the automatic test vector generation algorithm, and inputs the first test vector into the logic lock encryption circuit to obtain an ideal response; embeds a fixed-type fault in the current key bit, regenerates a second test vector based on the automatic test vector generation algorithm, and inputs the second test vector into the logic lock encryption circuit to obtain an actual response;

[0078] Key bit inference module: compares the actual response with the ideal response to obtain an inferred value of any key bit, and makes a judgment based on the inferred value and the real value of the key bit. If the comparison results are the same, the key bit is regarded as an inferred key, otherwise, the next key bit is judged until all key bits are traversed;

[0079] Logical lock encryption circuit security assessment module: calculates the proportion of inferable key bits in the key bits, and compares it with a preset threshold to obtain a security assessment result.

[0080] It can be understood that the system of this embodiment corresponds to the method of the above-mentioned embodiment 1, and the options in the above-mentioned embodiment 1 are also applicable to this embodiment, so they will not be described repeatedly here.

[0081] The terms in the drawings are for illustrative purposes only and should not be construed as limiting this patent;

[0082] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A security assessment method for a logic-locked encryption circuit, characterized in that: The following steps are involved: S1, extracting key bits and logic gates in the logic lock encryption circuit; dividing the logic cone based on the output nodes in the logic lock encryption circuit to obtain a logic cone set; S2, dividing the key bits into logically blockable key bits and non-logically blockable key bits; obtaining an X-state filling object in an automatic test vector generation algorithm based on the logically blockable key bits; S3, searching the logical cone containing the least key bits in the logical cone set; S4, traversing the key bit set in the current logic cone, finding the key bit with the most X-state filling objects, generating a first test vector for the key bit based on an automatic test vector generation algorithm, inputting the first test vector into the logic lock encryption circuit to obtain an ideal response; assuming that a fixed-type fault exists in the key bit embedding, regenerating a second test vector based on the automatic test vector generation algorithm, inputting the second test vector into the logic lock encryption circuit to obtain an actual response; and deleting the key bit from the key bit set; S5, comparing the actual response with the ideal response to obtain an inferred value of the key bit; taking the key bit whose inferred value is the same as the correct value of the key bit as the inferred key bit, and repeating steps S4 to S5 until the key bit set is empty; S6, deleting the current logic cone from the logic cone set, and repeating steps S3 to S6 until the logic cone set is empty; S7. Calculate the proportion of the inferable key bits in the key bits, and compare it with a preset threshold to obtain a security assessment result.

2. The security assessment method for a logic lock encryption circuit according to claim 1, characterized in that: The step of dividing the key bits into logically blockable key bits and non-logically blockable key bits comprises: Find a logic gate directly connected to the output node of the logic lock encryption circuit in the output path of any key bit as the final logic gate, and use the node connected to the output path of the current key bit and the final logic gate as the key bit node, and the remaining input nodes of the final logic gate as the blocking enable nodes; Determine the original input with the blocking enable node as the cone top of the logic cone; If the original input does not contain other key bits, then the key bit is a logically blockable key bit, otherwise it is a non-logically blockable key bit.

3. The security assessment method for a logic lock encryption circuit according to claim 2, characterized in that: The step of obtaining a set of X-state filling objects in an automatic test vector generation algorithm based on the logically blockable key bit comprises: For any key bit node in the final logic gate that can logically block the key bit, an original input is determined as the cone top of the logic cone, and the original input is used as an X-state filling object in an automatic test vector generation algorithm.

4. The security assessment method for a logic lock encryption circuit according to claim 1, characterized in that: The stuck-at fault includes a set-0 fault and a set-1 fault.

5. The security assessment method for a logic lock encryption circuit according to claim 1, characterized in that: The step of inputting the first test vector into the logic lock encryption circuit to obtain an ideal response comprises: Forcing constraints on the key bits that cannot be logically blocked in the first test vector by changing the value of the key bits; logically blocking the key bits of the X state filling bits; and then inputting the first test vector into the logic locking encryption circuit to obtain an ideal response; The step of inputting the second test vector into the logic lock encryption circuit to obtain an actual response comprises: The key bits in the second test vector that cannot be logically blocked are constrained by changing the values ​​of the key bits; the key bits of the X state filling bits are logically blocked; and the second test vector is input into the logic locking encryption circuit to obtain an ideal response.

6. The security assessment method for a logic lock encryption circuit according to claim 5, characterized in that: The steps of logic blocking include: According to the type of the second logic gate, the original input of the blocking enable node is changed.

7. The security assessment method for a logic lock encryption circuit according to claim 6, characterized in that: The step of changing the original input of the blocking enable node according to the type of the second logic gate comprises: If the second logic gate is an AND gate, adjusting the original input to set the blocking enable node value to 0; If the second logic gate is an OR gate, adjusting the original input to set the blocking enable node value to 1; If the second logic gate is a NAND gate, adjusting the original input to set the blocking enable node value to 0; If the second logic gate is a NOR gate, the original input is adjusted to set the blocking enable node value to 1.

8. The security assessment method for a logic lock encryption circuit according to claim 1, characterized in that: The step of comparing the actual response with the ideal response to obtain the inferred value of the key bit includes: if the actual response is different from the ideal response, then the value of the fixed-type fault is used as the inferred value of the key bit; otherwise, the complementary value of the value of the fixed-type fault is used as the inferred value of the key bit.

9. The security assessment method for a logic lock encryption circuit according to claim 1, characterized in that: The step of calculating the proportion of the inferable key bits in the key bits and comparing it with a preset threshold to obtain a security assessment result includes: if the proportion of the inferable key bits in the key bits is greater than the preset threshold, the security assessment result of the logic-locked encryption circuit is determined to be high risk; otherwise, the security assessment result of the logic-locked encryption circuit is determined to be low risk.

10. A security assessment system for a logic-locked encryption circuit, applied to the security assessment method for a logic-locked encryption circuit according to any one of claims 1 to 9, characterized in that: The system comprises: Key bit division module: used to extract key bits and logic gates in the logic lock encryption circuit; divide the key bits into logically blockable key bits and non-logically blockable key bits; The automatic test vector generation test module: uses the logically blockable key bit as an X-state filling object in the automatic test vector generation algorithm; for any key bit, generates a first test vector based on the automatic test vector generation algorithm, and inputs the first test vector into the logic lock encryption circuit to obtain an ideal response; embeds a fixed-type fault in the current key bit, regenerates a second test vector based on the automatic test vector generation algorithm, and inputs the second test vector into the logic lock encryption circuit to obtain an actual response; Key bit inference module: compares the actual response with the ideal response to obtain an inferred value of any key bit, and makes a judgment based on the inferred value and the real value of the key bit. If the comparison results are the same, the key bit is regarded as an inferred key, otherwise, the next key bit is judged until all key bits are traversed; Logical lock encryption circuit security assessment module: calculates the proportion of inferable key bits in the key bits, and compares it with a preset threshold to obtain a security assessment result.

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