Method and device for establishing connection relationship, storage medium and electronic device

Abstract

This application provides a method and apparatus for establishing connection relationships, a storage medium, and an electronic device. The method includes: determining a target combinational logic whose fan-out number meets a preset condition; determining a start register, a first end register set, and logic gates in the combinational logic path corresponding to the target combinational logic; copying the start register and the logic gates to obtain a first copy register and a first copy logic gate; establishing a first connection relationship between the first copy register and the first copy logic gates; and establishing a second connection relationship between the first copy logic gates and a first end register of the first end register set.

Description

Technical Field

[0001] This application relates to the field of chip design, and more specifically, to a method and apparatus for establishing a connection relationship, a storage medium, and an electronic device. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, the feature size of semiconductor manufacturing processes is gradually decreasing, chip integration density is increasing significantly, and chip structures are becoming increasingly complex. In current chip design, the increase in the number of logic gates and the reduction in chip size force chip designers to save area and maximize the number of logic gates within a limited area. If appropriate planning and measures are not taken in advance from the initial design stage, many intractable problems may arise in the back-end design of the chip, such as timing violations caused by scattered register placement or the problem of over-insertion of buffers to fix register-to-register / ICGs enable timing. High fan-out is a common problem in IC design; an excessively high fan-out is a common cause of timing violations. Excessive fan-out significantly worsens the transitions at connection points, especially when handling clock and reset signals. These signals typically drive multiple logic gates, resulting in a high fan-out. This can lead to degraded signal quality, increased latency, skew violations, and affect the normal operation of the chip.

[0003] Regarding the relevant technologies, in integrated circuit design, high fan-out combinational logic causes timing violations, and no effective solution has yet been proposed.

[0004] Therefore, it is necessary to improve the relevant technology to overcome the aforementioned defects. Summary of the Invention

[0005] This application provides a method and apparatus for establishing connection relationships, a storage medium, and an electronic device, to at least solve the problem of timing violations caused by high fan-out combinational logic in integrated circuit design in related technologies.

[0006] According to one embodiment of this application, a method for establishing a connection relationship is provided, comprising: determining a target combinational logic whose fan-out number meets a preset condition, and determining a start register, a first end register set, and logic gates in the combinational logic path corresponding to the target combinational logic; copying the start register and the logic gates to obtain a first copy register and a first copy logic gate; establishing a first connection relationship between the first copy register and the first copy logic gates, and establishing a second connection relationship between the first copy logic gates and a first end register of the first end register set.

[0007] In an exemplary embodiment, establishing a first connection relationship between the first copy register and the first copy logic gate includes: determining a third connection relationship between the start register and the logic gate; and establishing a first connection relationship between the first copy register and the first copy logic gate based on the third connection relationship.

[0008] In an exemplary embodiment, after establishing a first connection relationship between the first copy register and the first copy logic gate based on the third connection relationship, the method further includes: determining whether there are other logic gates in the combinational logic path, wherein the other logic gates are logic gates preceding the first logic gate and the other logic gates have not been copied; if it is determined that there are other logic gates in the combinational logic path, determining a fourth connection relationship between the first logic gate and other logic gates; and establishing a fifth connection relationship between the first copy logic gate and the other logic gates based on the fourth connection relationship.

[0009] In an exemplary embodiment, before or after establishing a second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the method further includes: when there are multiple first replication logic gates, determining a sixth connection relationship between the pairs of logic gates; and establishing a seventh connection relationship between the pairs of first replication logic gates based on the sixth connection relationship between the pairs of logic gates, wherein the pairs of logic gates correspond to the pairs of first replication logic gates.

[0010] In an exemplary embodiment, before establishing a second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the method further includes: determining the number of registers in the first endpoint register set; and determining the first endpoint register in the first endpoint register set according to a preset ratio and the number.

[0011] In an exemplary embodiment, determining the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic includes: determining the area of ​​the chip corresponding to the target combinational logic; if the area is greater than or equal to a preset area, determining the first N levels of logic gates in the first end register set, and determining the start registers connected to the first N levels of logic gates, where N is a positive integer; if the area is less than the preset area, determining the first M levels of logic gates in the first end register set, and determining the start registers connected to the first M levels of logic gates, where M is a positive integer less than or equal to N.

[0012] In an exemplary embodiment, after establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set, the method further includes: determining whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; if the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition, determining the start register, the second endpoint register set, and the logic gate in the updated combinational logic path; copying the start register and the logic gate in the updated combinational logic path to obtain a second copy register and a second copy logic gate; establishing a connection relationship between the second copy register and the second copy logic gate, and establishing a connection relationship between the second copy logic gate and the second endpoint register of the second endpoint register set; if the fan-out number of the combinational logic in the updated combinational logic path does not meet the preset condition, stopping the updating of the combinational logic path.

[0013] According to another embodiment of this application, a connection relationship establishment apparatus is provided, comprising: a determining module, configured to determine a target combinational logic whose fan-out number meets a preset condition, and to determine a start register, a first end register set, and logic gates in the combinational logic path corresponding to the target combinational logic; a copying module, configured to copy the start register and the logic gates to obtain a first copied register and a first copied logic gate; and an establishing module, configured to establish a first connection relationship between the first copied register and the first copied logic gates, and to establish a second connection relationship between the first copied logic gates and a first end register of the first end register set.

[0014] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0015] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0016] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0017] This application identifies a target combinational logic with a fan-out number that meets preset conditions, and determines the start register, first end register set, and logic gates in the combinational logic path corresponding to the target combinational logic. The start register and logic gates are copied to obtain a first copied register and a first copied logic gate. A first connection relationship is established between the first copied register and the first copied logic gate, and a second connection relationship is established between the first copied logic gate and the first end register of the first end register set. In other words, in this embodiment, by copying the start register and logic gates in a high fan-out logic combination, and establishing the copied registers, logic gates, and target end registers, the fan-out number in the original logic combination is reduced, thereby alleviating the timing violation problem. Therefore, the problem of timing violations caused by high fan-out combinational logic in integrated circuit design can be solved. Attached Figure Description

[0018] Figure 1 This is a hardware structure block diagram of a computer device for a method of establishing a connection relationship according to an embodiment of this application;

[0019] Figure 2 This is a flowchart of a method for establishing a connection relationship according to an embodiment of this application;

[0020] Figure 3 This is a flowchart of a method for establishing a connection relationship according to an optional embodiment of this application;

[0021] Figure 4 This is a schematic diagram of a method for establishing connection relationships according to an embodiment of this application;

[0022] Figure 5 This is a structural block diagram of a connection relationship establishment device according to an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device for a method of establishing a connection relationship according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1Only one is shown. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0026] Memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the connection relationship establishment method in this embodiment. Processor 102 executes various functional applications and data processing by running the computer programs stored in memory 104, thus implementing the aforementioned method. Memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, memory 104 may further include memories remotely located relative to processor 102, which can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0027] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0028] This embodiment provides a method for establishing connection relationships. Figure 2 This is a flowchart of a method for establishing connection relationships according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0029] Step S202: Determine the target combinational logic whose fan-out number meets the preset conditions, and determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic;

[0030] Step S204: Copy the start register and the logic gate to obtain a first copy register and a first copy logic gate;

[0031] Step S206: Establish a first connection relationship between the first copy register and the first copy logic gate, and establish a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set.

[0032] It should be noted that "first copied logic gate" refers to the logic gate copied from the original high fan-out logic gate; "first copied register" refers to the register copied from the original high fan-out register.

[0033] Through the above steps, a target combinational logic with a fan-out number meeting preset conditions is determined, and the start register, first end register set, and logic gate in the combinational logic path corresponding to the target combinational logic are determined. The start register and the logic gate are copied to obtain a first copied register and a first copied logic gate. A first connection relationship is established between the first copied register and the first copied logic gate, and a second connection relationship is established between the first copied logic gate and the first end register of the first end register set. That is, in this embodiment, by copying the start register and logic gate in the high fan-out logic combination, and establishing the copied register, logic gate, and target end register, the fan-out number in the original logic combination is reduced, thereby alleviating the timing violation problem. Therefore, the problem of timing violations caused by high fan-out combinational logic in integrated circuit design can be solved.

[0034] The entity performing the above steps may be a computer terminal, but is not limited to this.

[0035] Optionally, the "establishing a first connection relationship between the first copy register and the first copy logic gate" in step S206 above can be achieved by: determining a third connection relationship between the start register and the logic gate; and establishing a first connection relationship between the first copy register and the first copy logic gate based on the third connection relationship.

[0036] In other words, in this embodiment of the application, the connection between the first copy register and the first copy logic gate is established by copying the connection between the start register and the logic gate. For example, when the start register 1 is directly connected to the logic gate 1, a direct connection between the copy register 1 and the copy logic gate 1 is established; when the start register 1 and the logic gate 1 are connected based on the logic gate 2, a connection between the copy register 1 and the copy logic gate 2, as well as a connection between the copy logic gate 2 and the copy logic gate 1, are established; however, when the copy logic gate 2 is not present, a connection between the copy register 1 and the logic gate 2, as well as a connection between the logic gate 2 and the copy logic gate 1, are established.

[0037] This application's embodiments analyze and understand the signal propagation in the original design, particularly the signal load and delay issues under high fan-out conditions. Then, registers and logic gates are specifically copied, and their connections are re-established to distribute the load, reduce delay, improve signal quality, and enhance timing performance. This method not only solves the direct problems caused by high fan-out, such as timing violations and congestion, but also optimizes the overall circuit layout and performance to a certain extent, reducing the difficulty and time of subsequent placement and routing, and improving the efficiency and reliability of chip design.

[0038] Optionally, after establishing the first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship, the following steps are also required: determining whether there are other logic gates in the combinational logic path, wherein the other logic gates are logic gates preceding the first logic gate and the other logic gates have not been copied; if it is determined that there are other logic gates in the combinational logic path, determining the fourth connection relationship between the logic gate and other logic gates; and establishing the fifth connection relationship between the first copy logic gate and the other logic gates according to the fourth connection relationship.

[0039] In this embodiment, it is also necessary to identify whether there are any un-copied preceding logic gates on the original combinational logic path, in addition to the logic gates that have already been identified and are planned to be copied. Once un-copied preceding logic gates are identified, it is necessary to analyze the connection relationship between the other logic gates and the target logic gate. Since the connection relationship between the other logic gates and the target logic gate involves the direction of signal flow, the conditions for data transmission, etc., it is essential to accurately copy the connection relationship when copying it.

[0040] Based on the original logical relationships, a new connection relationship is established between the copied logic gates and the uncopied logic gates. This new relationship should fully reflect and maintain the original logical functions and data flow, ensuring that the copied path is functionally equivalent to the original path, while also solving the high fan-out problem.

[0041] In other words, in this embodiment, when copying registers and logic gates, the entire logic path can be comprehensively processed, including identifying and optimizing all relevant logic gates to achieve timing convergence, reduce congestion, and improve signal integrity. This method improves the accuracy and efficiency of timing problem solving during the synthesis stage and avoids the additional area consumption and debugging work caused by blindly copying logic units. By combining algorithm analysis and manual instructions, designers can optimize the design more flexibly and controllably, especially when dealing with high fan-out problems, where this method provides a more refined solution.

[0042] Optionally, before or after establishing the second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the following scheme needs to be executed: when there are multiple first replication logic gates, determine the sixth connection relationship between the pairs of logic gates; establish the seventh connection relationship between the pairs of first replication logic gates based on the sixth connection relationship between the pairs of logic gates, wherein the pairs of logic gates correspond to the pairs of first replication logic gates.

[0043] In this embodiment, for logic gates with high fan-out, it may be necessary to duplicate multiple logic gates to distribute the load, thereby reducing the fan-out of each logic gate and improving signal driving capability and timing performance. The "sixth connection relationship" indicates the connection method between the original logic gates. After duplicating the logic gates, it is first necessary to determine the connection relationship between the original logic gates, such as how they are connected through signal lines (nets), the order and direction of the connections, and any possible combinational logic relationships. The "seventh connection relationship" refers to the new connection relationship established between the duplicated logic gates. Determining the seventh connection relationship based on the sixth connection relationship means determining how to connect the duplicated logic gates based on the connection relationship between the original logic gates to maintain the consistency of circuit function while optimizing timing paths and fan-out.

[0044] In this embodiment, for each logic gate in the original circuit, there are one or more copied logic gates corresponding to it, and the connection relationship between them is kept consistent through the conversion from "sixth connection relationship" to "seventh connection relationship". This correspondence helps ensure that the copying operation does not change the basic function of the circuit, while effectively distributing the load and optimizing timing. That is, by intelligently copying logic gates and re-establishing their connections, circuit performance is optimized. This method not only solves the high fan-out problem but also maintains the integrity of the circuit function, making it an effective means of improving reliability and performance in design. In practice, specific functions of EDA tools, such as logic copying, fan-out analysis, and timing checks, can also be used in conjunction with Design Rule Check (DRC) and placement and routing strategies to optimize circuit design.

[0045] In an exemplary embodiment, before establishing a second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the method further includes: determining the number of registers in the first endpoint register set; and determining the first endpoint register in the first endpoint register set according to a preset ratio and the number.

[0046] It should be noted that the "first endpoint register set" mentioned above includes all target registers in high fan-out problems, i.e., those registers that need optimization or may cause timing issues. The "preset ratio" mentioned above can be an empirical value or may be based on specific design rules or objectives (e.g., one-half).

[0047] Based on this preset ratio and the previously calculated number of registers, the algorithm will select a certain number of registers for optimization operations, such as copying or reconfiguring. The number of registers selected is based on a certain proportion of the total number of registers in the set to ensure that the optimization is both effective and not excessive, avoiding unnecessary increases in area and power consumption.

[0048] This application's embodiments address high fan-out timing issues through quantitative analysis (determining the number of registers) and intelligent decision-making (selecting registers to be optimized based on a preset ratio). It combines automation and empirical rules, enabling improved design efficiency and reduced manual intervention while ensuring design quality, thereby achieving optimal design results within limited resources and time.

[0049] By using the "preset ratio" parameter, the scope and effect of optimization are balanced, avoiding the waste of resources caused by blind replication. Instead, the registers on the critical path are processed in a targeted manner, thereby achieving the goal of solving the problem while controlling costs.

[0050] In an exemplary embodiment, determining the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic includes: determining the area of ​​the chip corresponding to the target combinational logic; if the area is greater than or equal to a preset area, determining the first N levels of logic gates in the first end register set, and determining the start registers connected to the first N levels of logic gates, where N is a positive integer; if the area is less than the preset area, determining the first M levels of logic gates in the first end register set, and determining the start registers connected to the first M levels of logic gates, where M is a positive integer less than or equal to N.

[0051] This means dynamically adjusting the depth of analysis on the target combinational logic path based on the chip area to optimize the handling of registers and logic gates in the design. Specifically:

[0052] The depth of the register to be copied is determined based on whether the chip area exceeds a preset threshold (preset area). The preset area is usually set based on empirical data from chip design, reflecting that the optimization strategy for the logic path may need to be adjusted under different area conditions.

[0053] If the area is greater than or equal to the preset area, more area can be used to accommodate the copied logic gates. Therefore, the algorithm determines the first N levels of logic gates in the first endpoint register set, as well as the starting registers associated with these logic gates. Here, N is a positive integer.

[0054] When the chip area is smaller than a preset limit, it may mean a more compact design, thus limiting the area available for replicating logic gates. In this case, the algorithm will determine the first M levels of logic gates in the first endpoint register set, along with their corresponding starting registers, where M ≤ N. This means that with a smaller area, the optimization strategy may focus more on local optimization to avoid unnecessary resource consumption.

[0055] This application demonstrates flexibility and intelligence in chip design by differentiating between different chip areas and employing analysis and optimization strategies at varying depths. When the chip area is large, in-depth analysis can more comprehensively identify and optimize potential problems, such as high fan-out, congestion, or timing violations. When the chip area is small, more emphasis is placed on local optimization to avoid unnecessary resource consumption.

[0056] In an exemplary embodiment, after establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set, the method further includes: determining whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; if the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition, determining the start register, the second endpoint register set, and the logic gate in the updated combinational logic path; copying the start register and the logic gate in the updated combinational logic path to obtain a second copy register and a second copy logic gate; establishing a connection relationship between the second copy register and the second copy logic gate, and establishing a connection relationship between the second copy logic gate and the second endpoint register of the second endpoint register set; if the fan-out number of the combinational logic in the updated combinational logic path does not meet the preset condition, stopping the updating of the combinational logic path.

[0057] In other words, after establishing the initial connection between the first copied register and the first copied logic gate, the method further checks whether the fan-out number of the combinational logic in the updated path meets a preset condition. This preset condition refers to a threshold for the fan-out number to ensure signal driving capability and integrity. If the fan-out number in the updated combinational logic path meets the preset condition, then the starting register, the second ending register set, and the logic gates in the path need to be determined again. The "second ending register set" refers to the objects to be processed in the next round after the first round of optimization. The determined starting register and logic gate are copied to obtain the second copied register and the second copied logic gate, and the connection between them, as well as their connection with the second ending register set, are established. This copying and connection process is carried out while ensuring that the fan-out number is controlled within a reasonable range, in order to gradually optimize the entire chip design.

[0058] If, after a certain update, the fan-out number in a combinational logic path does not meet the preset conditions, then further updates to that path should be stopped. This avoids unnecessary resource consumption and increased design complexity.

[0059] By using the iterative approach described in this application, the impact of high fan-out on chip design can be gradually reduced, signal quality can be improved, timing violations can be reduced, and power consumption and area can be controlled at the same time.

[0060] Obviously, the embodiments described above are merely some embodiments of the present invention, and not all embodiments. To better understand the method for establishing the above connection relationship, the following description, in conjunction with embodiments, illustrates the process, but is not intended to limit the technical solutions of the embodiments of the present invention. Specifically:

[0061] In an optional embodiment, Figure 3 This is a flowchart of a method for establishing a connection relationship according to an optional embodiment of the present invention, and the specific steps are as follows:

[0062] Step S301: Write RTL code;

[0063] Step S302: Compile the RTL code;

[0064] Step S303: Use the PT / DC tool to find the combinational logic with an excessively large fan-out number (fan-out number is >= n, where n is an engineer's experience value), and find the starting point of all paths through this combinational logic.

[0065] like Figure 4 Registers A, B, and C in the database.

[0066] Step S304: Copy the found starting point register.

[0067] And connect all relevant nets to the starting point, such as Figure 4 The registers A_rep and C_rep are defined in the database, and the points related to A_rep / C_rep are connected by lines;

[0068] Step S305: Inspect and copy the intermediate logic.

[0069] Examine the combinational logic between the start and end points, and copy any combinational logic with excessively large fanouts; for example... Figure 4 The combinational logic F / G in the middle, and the combinational logic F_rep / G_rep for copying.

[0070] Step S306: Locate the intermediate logic of the replication and reconnect it to the starting point of the replication.

[0071] like Figure 4 Connect the points related to F_rep / G_rep with lines.

[0072] Step S307: Insert chip test (Design for Testability, or DFT for short);

[0073] Step S308: Incremental compilation;

[0074] Step S309: Complete.

[0075] This application, based on existing EDA tools, utilizes register copying and logic copying to fundamentally solve the high fan-out problem commonly encountered in chip design. Compared to traditional methods that address high fan-out by modifying code or inserting buffers, this method significantly improves reliability and controllability. Furthermore, by attempting to copy critical registers reasonably, it avoids excessive register copying and area increase caused by too much logic copying. This application also greatly assists in timing convergence caused by high fan-out, while resolving potential congestion issues, saving area and routing resources, and reducing the debugging time for backend engineers using EDA tools.

[0076] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0077] This embodiment also provides a connection establishment device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0078] Figure 5 This is a structural block diagram of a connection relationship establishment device according to an embodiment of this application, such as... Figure 5 As shown, the device includes:

[0079] The determination module 52 is used to determine the target combinational logic whose fan-out number meets the preset conditions, and to determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic;

[0080] The copy module 54 is used to copy the start register and the logic gate to obtain a first copy register and a first copy logic gate;

[0081] Module 56 is used to establish a first connection relationship between the first copy register and the first copy logic gate, and to establish a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set.

[0082] The aforementioned apparatus determines a target combinational logic whose fan-out number meets preset conditions, and identifies the start register, first end register set, and logic gates in the combinational logic path corresponding to the target combinational logic. The start register and logic gates are copied to obtain a first copied register and a first copied logic gate. A first connection relationship is established between the first copied register and the first copied logic gate, and a second connection relationship is established between the first copied logic gate and the first end register of the first end register set. In this embodiment, by copying the start register and logic gates in a high fan-out logic combination, and establishing the copied registers, logic gates, and target end registers, the fan-out number in the original logic combination is reduced, thereby mitigating timing violations. Therefore, the problem of timing violations caused by high fan-out combinational logic in integrated circuit design can be solved.

[0083] In an exemplary embodiment, a setup module 56 is configured to determine a third connection relationship between the start register and the logic gate; and establish a first connection relationship between the first copy register and the first copy logic gate based on the third connection relationship.

[0084] In an exemplary embodiment, a module 56 is configured to determine whether other logic gates exist in the combinational logic path, wherein the other logic gates are logic gates preceding the first logic gate and the other logic gates are not copied; if it is determined that the other logic gates exist in the combinational logic path, a fourth connection relationship between the first copied logic gate and the other logic gates is determined; and a fifth connection relationship between the first copied logic gate and the other logic gates is established based on the fourth connection relationship.

[0085] In an exemplary embodiment, the establishment module 56 is configured to determine a sixth connection relationship between the pairs of logic gates when there are multiple first replication logic gates; and establish a seventh connection relationship between the pairs of first replication logic gates based on the sixth connection relationship between the pairs of logic gates, wherein the pairs of logic gates correspond to the pairs of first replication logic gates.

[0086] In an exemplary embodiment, the determining module 52 is configured to determine the number of registers in the first endpoint register set; and to determine the first endpoint register in the first endpoint register set according to a preset ratio and the number.

[0087] In an exemplary embodiment, the determining module 52 is configured to determine the area of ​​the chip corresponding to the target combinational logic; if the area is greater than or equal to a preset area, determine the first N levels of logic gates of the first endpoint register set, and determine the starting registers connected to the first N levels of logic gates, where N is a positive integer; if the area is less than the preset area, determine the first M levels of logic gates of the first endpoint register set, and determine the starting registers connected to the first M levels of logic gates, where M is a positive integer less than or equal to N.

[0088] In an exemplary embodiment, the determining module 52 is configured to determine whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; if the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition, determine the start register, the second end register set, and the logic gate in the updated combinational logic path; copy the start register and the logic gate in the updated combinational logic path to obtain a second copy register and a second copy logic gate; establish the connection relationship between the second copy register and the second copy logic gate, and establish the connection relationship between the second copy logic gate and the second end register of the second end register set; if the fan-out number of the combinational logic in the updated combinational logic path does not meet the preset condition, stop updating the combinational logic path.

[0089] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0090] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0091] Optionally, the computer-readable storage medium is configured to perform the following steps at runtime:

[0092] Step S1: Determine the target combinational logic whose fan-out number meets the preset conditions, and determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic;

[0093] Step S2: Copy the start register and the logic gate to obtain a first copied register and a first copied logic gate;

[0094] Step S3: Establish a first connection relationship between the first copy register and the first copy logic gate, and establish a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set.

[0095] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0096] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0097] Optionally, the electronic device is configured to perform the following steps at runtime:

[0098] Step S1: Determine the target combinational logic whose fan-out number meets the preset conditions, and determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic;

[0099] Step S2: Copy the start register and the logic gate to obtain a first copied register and a first copied logic gate;

[0100] Step S3: Establish a first connection relationship between the first copy register and the first copy logic gate, and establish a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set.

[0101] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0102] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0103] Optionally, the computer program product is configured to perform the following steps at runtime:

[0104] Step S1: Determine the target combinational logic whose fan-out number meets the preset conditions, and determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic;

[0105] Step S2: Copy the start register and the logic gate to obtain a first copied register and a first copied logic gate;

[0106] Step S3: Establish a first connection relationship between the first copy register and the first copy logic gate, and establish a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set.

[0107] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0108] Embodiments of this application also provide a computer program that includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in any of the above method embodiments.

[0109] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0110] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0111] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for establishing a connection relationship, characterized in that, include: Determine the target combinational logic whose fan-out number meets the preset conditions, and determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic; The start register and the logic gate are copied to obtain a first copied register and a first copied logic gate; Establish a first connection relationship between the first replication register and the first replication logic gate, and establish a second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set; The determination of the starting register, the first ending register set, and the logic gates in the combinational logic path corresponding to the target combinational logic includes: determining the area of ​​the chip corresponding to the target combinational logic; if the area is greater than or equal to a preset area, determining the first N levels of logic gates in the first ending register set, and determining the starting registers connected to the first N levels of logic gates, where N is a positive integer; if the area is less than the preset area, determining the first M levels of logic gates in the first ending register set, and determining the starting registers connected to the first M levels of logic gates, where M is a positive integer less than or equal to N.

2. The method according to claim 1, characterized in that, Establishing a first connection between the first copy register and the first copy logic gate includes: Determine the third connection relationship between the start register and the logic gate; A first connection relationship is established between the first copy register and the first copy logic gate based on the third connection relationship.

3. The method according to claim 2, characterized in that, After establishing the first connection relationship between the first copy register and the first copy logic gate based on the third connection relationship, the method further includes: Determine whether there are other logic gates in the combinational logic path, wherein the other logic gates are the preceding logic gates of the current logic gate, and the other logic gates are not copied; If it is determined that there are other logic gates in the combinational logic path, determine the fourth connection relationship between the logic gates and other logic gates; Based on the fourth connection relationship, a fifth connection relationship is established between the first replication logic gate and the other logic gates.

4. The method according to claim 1, characterized in that, Before or after establishing the second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the method further includes: When there are multiple first replication logic gates, determine the sixth connection relationship between each pair of logic gates; A seventh connection relationship is established between the pairwise first replication logic gates based on the sixth connection relationship between the pairwise logic gates, wherein the pairwise logic gates correspond to the pairwise first replication logic gates.

5. The method according to claim 1, characterized in that, Before establishing the second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the method further includes: Determine the number of registers in the first endpoint register set; The first endpoint register is determined from the first endpoint register set according to the preset ratio and the quantity.

6. The method according to claim 1, characterized in that, After establishing a first connection relationship between the first replication register and the first replication logic gate, and establishing a second connection relationship between the first replication logic gate and the first endpoint register of the first endpoint register set, the method further includes: Determine whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; If the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition, determine the start register, the second end register set, and the logic gates in the updated combinational logic path. The start register and the logic gate in the updated combinational logic path are copied to obtain a second copied register and a second copied logic gate; Establish the connection relationship between the second copy register and the second copy logic gate, and establish the connection relationship between the second copy logic gate and the second endpoint register of the second endpoint register set; If the fan-out number of the combinational logic in the updated combinational logic path does not meet the preset condition, the update of the combinational logic path shall be stopped.

7. A device for establishing a connection relationship, characterized in that, include: The determination module is used to determine the target combinational logic whose fan-out number meets the preset conditions, and to determine the start register, the first end register set, and the logic gates in the combinational logic path corresponding to the target combinational logic; A copying module is used to copy the start register and the logic gate to obtain a first copy register and a first copy logic gate; A module is established to establish a first connection relationship between the first copy register and the first copy logic gate, and to establish a second connection relationship between the first copy logic gate and the first endpoint register of the first endpoint register set. The determining module is further configured to: determine the area of ​​the chip corresponding to the target combinational logic; if the area is greater than or equal to a preset area, determine the first N levels of logic gates in the first endpoint register set, and determine the starting registers connected to the first N levels of logic gates, where N is a positive integer; if the area is less than the preset area, determine the first M levels of logic gates in the first endpoint register set, and determine the starting registers connected to the first M levels of logic gates, where M is a positive integer less than or equal to N.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 6.

Images