Multi-channel power supply priority gating circuit and control method thereof

Abstract

The invention relates to the technical field of circuits, in particular to a multipath power supply priority gating circuit and a control method thereof, and the circuit comprises M input connectors, a switching circuit, M-1 gating circuits and an output power connector, the ith input joint is connected with the second power supply input end of the (i-1) th gating circuit, and is respectively connected with the first power supply input ends of the (i-1) th to (M-1) th gating circuits; wherein i is less than or equal to M-1, and M is an integer greater than 1; the first input connector is also connected with the output power supply connector through the switching circuit; the Mth input connector is connected with the second power supply input end of the (M-1) th gating circuit; preferentially conducting a path between the first power supply input end and the power supply output end through the gating circuit, wherein the voltage value of the power supply output end is the voltage value output by the front input connector; according to the invention, priority gating of multiple paths of power supplies can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of circuits, and in particular to a multi-channel power supply priority gating circuit and a control method thereof. Background Art

[0002] In a multi-way power supply system, in order to ensure that a stable and high-priority power supply is selected from multiple power supply inputs, the existing technology usually adopts complex control circuits and algorithms. However, these methods often have problems such as high cost, long response time, and high circuit complexity. Therefore, the present invention proposes a simple, efficient and low-cost multi-way power supply priority selection circuit and control method thereof to solve the problems existing in the prior art. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a multi-channel power supply priority gating circuit and a control method thereof, which can realize the multi-channel power supply priority gating circuit.

[0004] In order to achieve the above object, the present invention provides the following technical solutions: In one aspect, the present invention provides a multi-channel power priority gating circuit, comprising: M input connectors, (M-1) gating circuits, a switch circuit and an output power connector; The gating circuit comprises a first power input terminal, a second power input terminal and a power output terminal; the i-th input connector is connected to the second power input terminal of the (i-1)th gating circuit, and is respectively connected to the first power input terminals of the (i-1)th to (M-1)th gating circuits; wherein i≤M-1, and M is an integer greater than 1; The first input connector is also connected to the output power connector through the switch circuit; the Mth input connector is connected to the second power input terminal of the (M-1)th selection circuit; The gating circuit preferentially conducts the path between the first power input terminal and the power output terminal, and the voltage value of the power output terminal is the voltage value output by the input connector with the highest ranking.

[0005] Furthermore, the gating circuit further comprises: a first resistor, a first triode, a second triode, a first MOS transistor and a second MOS transistor; The first power input terminal is connected to the power output terminal via a first switch; The second power input terminal is respectively connected to one end of the first resistor and the source of the first MOS tube; The other end of the first resistor is connected to the collector of the first transistor and the base of the second transistor respectively. The emitter of the first transistor is grounded, and the base is connected to the first power input terminal; The emitter of the second triode is grounded, and the collector is connected to the gate of the first MOS tube and the gate of the second MOS tube respectively; The drain of the first MOS tube is connected to the drain of the second MOS tube, and the source of the second MOS tube is connected to the power output end.

[0006] Furthermore, a diode is connected one-to-one between the 1st to (M-1)th input connectors and the first power input terminal of each of the selection circuits, the input connector is connected to the anode of the diode, and the cathode of the diode is connected to the first power input terminal.

[0007] Furthermore, the gating circuit further includes a second resistor, the base of the first transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the first power input end.

[0008] Furthermore, the first transistor and the second transistor are both NPN transistors.

[0009] Furthermore, the first MOS tube and the second MOS tube are both PMOS tubes.

[0010] Further, the switching circuit includes a third power supply input terminal, a third resistor, a third MOS tube and a third triode, the third power supply input terminal is respectively connected to one end of the third resistor and the drain of the third MOS tube, the other end of the third resistor is connected to the base of the third triode, the gate of the third MOS tube is connected to the collector of the third triode, the source of the third MOS tube is connected to the power supply output terminal, and the emitter of the third triode is grounded.

[0011] Furthermore, the third transistor is an NPN transistor.

[0012] Furthermore, the third MOS tube is a PMOS tube.

[0013] On the other hand, the present invention further provides a control method for a multi-channel power supply priority gating circuit, which is applied to any of the multi-channel power supply priority gating circuits described above, and the method comprises the following steps: When M-1 of the gating circuits are connected to input connectors, the order of the input connectors is determined, and the input connectors with the highest order are preferentially turned on.

[0014] The beneficial effects of the present invention are as follows: the present invention provides a multi-way power priority gating circuit and a control method thereof, wherein the gating circuit preferentially conducts the path between the first power input terminal and the power output terminal, and the voltage value of the power output terminal is the voltage value output by the input connector with the highest ranking. The present invention can selectively conduct input power connected to multiple input connectors, and realize the multi-way power priority gating in a pure hardware manner, which has the advantage of low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 is a circuit schematic diagram of a gating circuit in an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a switch circuit in an embodiment of the present invention; Figure 3 The invention is a circuit schematic diagram of a multi-channel power supply priority gating circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0018] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0019] In the description of the present invention, if there are words such as "several", it means one or more, "more" means more than two, greater than, less than, exceed, etc. are understood as not including the number, and above, below, within, etc. are understood as including the number.

[0020] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0021] refer to Figure 1 and Figure 2 The embodiment of the present invention provides a multi-channel power priority gating circuit, comprising: M input connectors J, (M-1) gating circuits 100, a switch circuit 200 and an output power connector Jout; The gating circuit 100 includes a first power input terminal VCC1_IN, a second power input terminal VCC2_IN and a power output terminal VCC_OUT; the i-th input connector J is connected to the second power input terminal VCC2_IN of the (i-1)th gating circuit 100, and is respectively connected to the first power input terminals VCC1_IN of the (i-1)th to (M-1)th gating circuits 100; wherein i≤M-1, and M is an integer greater than 1; The first input connector J is also connected to the output power connector Jout through the switch circuit 200; the Mth input connector J is connected to the first power input terminal VCC1_IN of the (M-1)th gating circuit 100; The gating circuit 100 preferentially turns on the path between the first power input terminal VCC1_IN and the power output terminal VCC_OUT, and the voltage value of the power output terminal VCC_OUT is the voltage value output by the input connector J with the highest ranking.

[0022] It should be noted that in the embodiment provided by the present invention, it is possible to selectively conduct the power supply connected to the power input terminal, and implement the priority gating of multiple power supplies in a pure hardware manner, which has the advantage of low cost.

[0023] As a preferred embodiment of the above, the gating circuit 100 further includes: a first resistor R1, a first transistor Q1, a second transistor Q2, a first MOS transistor Q3 and a second MOS transistor Q4; The first power input terminal VCC1_IN is connected to the power output terminal VCC_OUT through a first switch; The second power input terminal VCC2_IN is respectively connected to one end of the first resistor R1 and the source of the first MOS transistor Q3; The other end of the first resistor R1 is connected to the collector of the first transistor Q1 and the base of the second transistor Q2 respectively. The emitter of the first transistor Q1 is grounded, and the base is connected to the first power input terminal VCC1_IN; The emitter of the second triode Q2 is grounded, and the collector is connected to the gate of the first MOS transistor Q3 and the gate of the second MOS transistor Q4 respectively; The drain of the first MOS transistor Q3 is connected to the drain of the second MOS transistor Q4 , and the source of the second MOS transistor Q4 is connected to the power output terminal VCC_OUT.

[0024] As a preferred embodiment of the above embodiment, a diode D is connected one-to-one between the 1st to the (M-1)th input connectors J and the first power input terminal VCC1_IN of each of the selection circuits, the input connector J is connected to the anode of the diode D, and the cathode of the diode D is connected to the first power input terminal VCC1_IN.

[0025] As a preferred embodiment of the above embodiment, the gating circuit 100 further includes a second resistor R2, the base of the first transistor Q1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the first power input terminal VCC1_IN.

[0026] As a preference of the above embodiment, both the first transistor Q1 and the second transistor Q2 are NPN transistors.

[0027] As a preference of the above embodiment, both the first MOS transistor Q3 and the second MOS transistor Q4 are PMOS transistors.

[0028] As a preferred embodiment of the above embodiment, the switch circuit 200 includes a third power input terminal VCC3_IN, a third resistor R3, a third MOS transistor Q6 and a third triode Q5, the third power input terminal VCC3_IN is respectively connected to one end of the third resistor R3 and the drain of the third MOS transistor Q6, the other end of the third resistor R3 is connected to the base of the third triode Q5, the gate of the third MOS transistor Q6 is connected to the collector of the third triode Q5, the source of the third MOS transistor Q6 is connected to the power output terminal VCC_OUT, and the emitter of the third triode Q5 is grounded.

[0029] As a preference of the above embodiment, the third transistor Q5 is an NPN transistor.

[0030] As a preference of the above embodiment, the third MOS tube Q6 is a PMOS tube.

[0031] The working principle of the present invention is as follows: refer to Figure 3, setting M=4, the present invention mainly realizes the priority of the power supply: the voltage VCC1 of the first input connector J1> the voltage VCC2 of the second input connector J2> the voltage VCC3 of the third input connector J3> the voltage VCC4 of the fourth input connector J4. That is, when any one or more of the voltages VCC1 of the first input connector J1, VCC2 of the second input connector J2, VCC3 of the third input connector J3, and VCC4 of the fourth input connector J4 are input simultaneously, the power supply output VCC_OUT is selected and outputted according to the priority: the voltage VCC1 of the first input connector J1> the voltage VCC2 of the second input connector J2> the voltage VCC3 of the third input connector J3> the voltage VCC4 of the fourth input connector J4.

[0032] The specific principles are as follows: 1: When the first input connector J1 has input voltage VCC1; 1) The voltage VCC1 of the first input terminal J1 turns on the third transistor Q5 in the switch circuit 200 and the first transistor Q1 in each gate circuit 100, so that the voltage VCC_OUT of the power output terminal VCC_OUT=VCC1.

[0033] 2) The voltage VCC1 of the first input connector J1 turns on the diode D connected thereto, thereby turning on the first transistor Q1 in each gating circuit 100, and then turning off the second transistor Q2, and finally turning off the first MOS transistor Q3 and the second MOS transistor Q4.

[0034] 3) Even if the voltage VCC2 of the second input connector J2, the voltage VCC3 of the third input connector J3, and the voltage VCC4 of the fourth input connector J4 are input, the first MOS transistor Q3 and the second MOS transistor Q4 are both in the cut-off state.

[0035] 4) In general, as long as the voltage VCC1 of the first input connector J1 is input, only the third MOS transistor Q6 of the switch circuit 200 will be turned on, and the first MOS transistor Q3 will not be turned on. Voltage VCC_OUT = voltage VCC1 of the first input connector J1.

[0036] 2: When the voltage VCC1 of the first input connector J1 and the voltage VCC2 of the second input connector J2 are input; Since the voltage VCC1 of the first input connector J1 is not input, the third MOS transistor Q6 will not be turned on.

[0037] Since the voltage VCC1 of the first input connector J1 is not input, and the voltage VCC2 of the second input connector J2 is input, the first transistor Q1 of the first selection circuit 100 is turned off, and the first transistors Q1 of the other (second, third, and fourth) selection circuits 100 are turned on, so that the second transistor Q2 of the first selection circuit 100 is turned on, and the second transistors Q2 of the other selection circuits 100 are turned off. Finally, the first MOS transistor Q3 of the first selection circuit 100 is turned on, and the second MOS transistors Q4 of the other selection circuits 100 are turned off.

[0038] 3) Even if the voltage VCC3 of the third input connector J3 and the voltage VCC4 of the fourth input connector J4 are input, the second MOS transistors Q4 of the remaining gating circuits 100 are in the cut-off state.

[0039] 4) In general, when the voltage VCC1 of the first input connector J1 is not input, and the voltage VCC2 of the second input connector J2 is input, only the first transistor Q1 of the first selection circuit 100 and the third transistor Q5 of the switch circuit 200 will be turned on, and the second transistors Q2 of the other selection circuits 100 will not be turned on. The voltage VCC_OUT = the voltage VCC2 of the second input connector J2.

[0040] 3: When the voltage VCC1 of the first input connector J1 and the voltage VCC2 of the second input connector J2 are not input, and the voltage VCC3 of the third input connector J3 is input; According to the above principle, only the first MOS transistor Q3 of the second gating circuit 100 will be turned on. The voltage VCC_OUT=the voltage VCC3 of the third input connector J3.

[0041] 4: When the voltage VCC1 of the first input connector J1, the voltage VCC2 of the second input connector J2, and the voltage VCC3 of the third input connector J3 are not input, and the voltage VCC4 of the fourth input connector J4 is input; According to the above schematic diagram, only the first MOS transistor Q3 of the third gating circuit 100 is turned on. The voltage VCC_OUT=the voltage VCC4 of the fourth input connector J4.

[0042] According to the same principle, the present invention can be extended to more multiple-channel gating input power supplies for priority gating.

[0043] In addition, an embodiment of the present invention provides a control method for a multi-channel power supply priority gating circuit, which is applied to the multi-channel power supply priority gating circuit described in any of the above embodiments, and the method includes the following steps: When M-1 of the gating circuits are connected to input connectors, the order of the input connectors is determined, and the input connectors with the highest order are preferentially turned on.

[0044] The embodiments described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. Those skilled in the art can appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present invention are also applicable to similar technical problems.

[0045] Those skilled in the art will appreciate that the technical solutions shown in the figures do not limit the embodiments of the present invention and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0046] The device embodiments described above are merely illustrative, and the circuits described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed over multiple network circuits. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0047] Those skilled in the art will appreciate that all or some of the steps in the method disclosed above, the main control chip, and the functional modules / circuits in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0048] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, main control chip, product or device that includes a series of steps or circuits is not necessarily limited to those steps or circuits clearly listed, but may include other steps or circuits that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] It should be understood that in the present invention, "at least one (item)" refers to one or more, and "plurality" refers to two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can represent: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0050] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above circuits is only a logical function division. There may be other division methods in actual implementation, such as multiple circuits or components can be combined or integrated into another main control chip, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or circuits, which can be electrical, mechanical or other forms.

[0051] The circuits described above as separate components may or may not be physically separated, and the components shown as circuits may or may not be physical circuits, that is, they may be located in one place or distributed over multiple network circuits. Some or all of the circuits may be selected according to actual needs to achieve the purpose of the present embodiment.

[0052] In addition, each functional circuit in each embodiment of the present invention may be integrated into one processing circuit, or each circuit may exist physically separately, or two or more circuits may be integrated into one circuit. The above integrated circuit may be implemented in the form of hardware or in the form of software functional circuit.

[0053] The preferred embodiments of the embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of rights of the embodiments of the present invention is not limited thereby. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present invention should be within the scope of rights of the embodiments of the present invention. Although the description disclosed in the present invention has been quite detailed and several of the embodiments are described in particular, it is not intended to be limited to any of these details or embodiments or any particular embodiment, but should be regarded as providing a broad possible interpretation of these claims by reference to the attached claims, taking into account the prior art, so as to effectively cover the intended scope disclosed by the present invention. In addition, the above describes the present invention with the foreseeable embodiments of the inventor, the purpose of which is to provide a useful description, and those non-substantial changes to the present invention that have not yet been foreseen may still represent equivalent changes to the present disclosure.

Claims

1. A multi-channel power supply priority gating circuit, characterized in that: include: M input connectors, (M-1) selection circuits, a switch circuit and an output power connector; The gating circuit comprises a first power input terminal, a second power input terminal and a power output terminal; the i-th input connector is connected to the second power input terminal of the (i-1)th gating circuit, and is respectively connected to the first power input terminals of the (i-1)th to (M-1)th gating circuits; wherein i≤M-1, and M is an integer greater than 1; The first input connector is also connected to the output power connector through the switch circuit; the Mth input connector is connected to the second power input terminal of the (M-1)th selection circuit; The gating circuit preferentially conducts the path between the first power input terminal and the power output terminal, and the voltage value of the power output terminal is the voltage value output by the input connector with the highest ranking.

2. A multi-channel power supply priority gating circuit according to claim 1, characterized in that: The gating circuit further includes: a first resistor, a first triode, a second triode, a first MOS transistor and a second MOS transistor; The first power input terminal is connected to the power output terminal via a first switch; The second power input terminal is respectively connected to one end of the first resistor and the source of the first MOS tube; The other end of the first resistor is connected to the collector of the first transistor and the base of the second transistor respectively. The emitter of the first transistor is grounded, and the base is connected to the first power input terminal; The emitter of the second triode is grounded, and the collector is connected to the gate of the first MOS tube and the gate of the second MOS tube respectively; The drain of the first MOS tube is connected to the drain of the second MOS tube, and the source of the second MOS tube is connected to the power output end.

3. A multi-channel power supply priority gating circuit according to claim 1, characterized in that: A diode is connected one-to-one between the 1st to (M-1)th input connectors and the first power input terminal of each of the selection circuits, the input connector is connected to the anode of the diode, and the cathode of the diode is connected to the first power input terminal.

4. A multi-channel power supply priority gating circuit according to claim 2, characterized in that: The gating circuit further includes a second resistor, the base of the first transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to the first power input end.

5. A multi-channel power supply priority gating circuit according to claim 2, characterized in that: The first transistor and the second transistor are both NPN transistors.

6. A multi-channel power supply priority gating circuit according to claim 2, characterized in that: The first MOS tube and the second MOS tube are both PMOS tubes.

7. A multi-channel power supply priority gating circuit according to claim 1, characterized in that: The switch circuit includes a third power input terminal, a third resistor, a third MOS tube and a third triode. The third power input terminal is respectively connected to one end of the third resistor and the drain of the third MOS tube, the other end of the third resistor is connected to the base of the third triode, the gate of the third MOS tube is connected to the collector of the third triode, the source of the third MOS tube is connected to the power output terminal, and the emitter of the third triode is grounded.

8. A multi-channel power supply priority gating circuit according to claim 7, characterized in that: The third transistor is an NPN transistor.

9. A multi-channel power supply priority gating circuit according to claim 7, characterized in that: The third MOS tube is a PMOS tube.

10. A control method for a multi-power priority gating circuit, characterized in that: The method applied to the multi-power priority gating circuit according to any one of claims 1 to 9, characterized in that the method comprises the following steps: When M-1 of the gating circuits are connected to input connectors, the order of the input connectors is determined, and the input connectors with the highest order are preferentially turned on.

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