Semiconductor device and preparation method thereof

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By designing a groove structure in the MIM capacitor, the dielectric layer and the first plate layer are in contact at the bottom of the groove, the problem of the existing MIM capacitor failing at the edge of the upper plate layer is solved, and the stability of the capacitor structure is improved and Effects of etching damage.

CN119325235APending Publication Date: 2025-01-17WUHAN XINXIN SEMICON MFG CO LTD

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Patent Information

Application Number: CN202411406207.9
Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner
Filing Date: 2024-10-09
Publication Date: 2025-01-17

AI Technical Summary

Technical Problem

Existing MIM capacitors are prone to failure at the edge of the upper plate layer, resulting in poor stability of the capacitance structure and serious etching damage.

Method used

A capacitive structure is formed using a substrate, a first plate layer, a first dielectric layer, a dielectric layer and a second plate layer, wherein a groove is formed in the first dielectric layer, and the dielectric layer is in contact with the first plate layer, and the second plate layer is in the first dielectric layer. The diode plate layer covers the dielectric layer, forming a recessed structure to reduce etching damage.

Benefits of technology

It effectively avoids edge effects and etching damage of the capacitor structure, improves the stability of the capacitor structure, and reduces the risk of leakage.

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Abstract

The invention provides a semiconductor device which comprises a substrate, a first pole plate layer, a first dielectric layer, a dielectric layer and a second pole plate layer, the first pole plate layer covers part of the surface of the substrate, the first dielectric layer covers the substrate and the first pole plate layer, a groove is formed in the first dielectric layer, the groove penetrates through the first dielectric layer and is exposed out of the first pole plate layer, and the second pole plate layer is exposed out of the first dielectric layer. The dielectric layer at least covers the inner wall of the groove, the second polar plate layer covers the dielectric layer, and the first polar plate layer, the dielectric layer and the second polar plate layer form a capacitor structure. The dielectric layer is in contact with the first polar plate layer at the bottom of the groove, the contact part of the dielectric layer and the first polar plate layer is an effective area of the capacitor structure, the edge effect and etching damage caused when the dielectric layer and the second polar plate layer are etched cannot excessively influence the effective area of the capacitor structure, the capacitor structure is not prone to failure, and stability is better. Correspondingly, the invention also provides a preparation method of the semiconductor device.

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Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The MIM (metal-insulator-metal) capacitor composed of a stacked lower plate, a dielectric layer, and an upper plate has the characteristics of high Q value, good voltage resistance, and low ESR (equivalent series resistance), and has good process compatibility with integrated circuits. It is currently widely used in semiconductor devices.

[0003] The existing process for preparing MIM capacitors is to first form a stacked lower electrode layer, a dielectric layer and an upper electrode layer on a substrate, first etch the upper electrode layer to remove part of the upper electrode layer, and then etch the dielectric layer and the lower electrode layer, with a step between the dielectric layer and the upper electrode layer to facilitate the extraction of the lower electrode layer. Figure 1 This is an electron microscope image of an existing MIM capacitor, such as Figure 1 As shown in the figure, since the etching of the upper plate layer needs to stop on the dielectric layer and requires sufficient over-etching to ensure that the upper plate layer on the partial area of the dielectric layer is etched cleanly, the over-etching leads to a lower thickness of the dielectric layer and etching damage, which can easily cause the MIM capacitor to fail at the edge of the upper plate layer ( Figure 1 ). Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to solve the problem that the MIM capacitor in the existing semiconductor device is prone to failure.

[0005] In order to achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] substrate;

[0007] A first electrode layer, covering a portion of the surface of the substrate;

[0008] A first dielectric layer, covering the substrate and the first electrode layer, wherein the first dielectric layer has a groove, and the groove penetrates the first dielectric layer to expose the first electrode layer;

[0009] a dielectric layer, at least covering an inner wall of the groove and contacting the first electrode layer; and

[0010] The second electrode layer covers the dielectric layer. The first electrode layer, the dielectric layer and the second electrode layer form a capacitor structure.

[0011] Optionally, the first electrode layer is a flat plate structure, and the dielectric layer and the second electrode layer are concave structures.

[0012] Optionally, after being stacked in sequence, the dielectric layer and the second electrode layer are recessed toward the direction close to the substrate to contact with the first electrode layer, and the contact portion between the two is the effective area of the capacitor structure.

[0013] Optionally, the dielectric layer also covers a portion of the surface of the first dielectric layer.

[0014] Optionally, also include:

[0015] a second dielectric layer, covering the first dielectric layer and the capacitor structure;

[0016] a first interconnect structure, located in the first dielectric layer and the second dielectric layer, and electrically connected to the first electrode layer; and

[0017] The second interconnect structure is located in the first dielectric layer and is electrically connected to the second electrode layer.

[0018] Optionally, also include:

[0019] a second dielectric layer, covering the first dielectric layer and the capacitor structure;

[0020] a third dielectric layer, located between the substrate and the first dielectric layer, wherein the third dielectric layer comprises a metal layer, and the first electrode layer is located on the metal layer and is electrically connected to the metal layer;

[0021] a first interconnect structure, located in the first dielectric layer and the second dielectric layer, and electrically connected to the metal layer; and

[0022] The second interconnect structure is located in the first dielectric layer and is electrically connected to the second electrode layer.

[0023] Optionally, the material of the first electrode layer is TIN or W, and the material of the metal layer is Cu.

[0024] Optionally, a metal barrier layer is provided between the metal layer and the first electrode layer; and / or a thickness of the first electrode layer is less than 600 angstroms.

[0025] The present invention also provides a method for preparing a semiconductor device, comprising:

[0026] providing a substrate;

[0027] forming a first electrode layer on a portion of the surface of the substrate;

[0028] forming a first dielectric layer on the substrate and the first electrode layer;

[0029] forming a groove in the first dielectric layer, wherein the groove penetrates the first dielectric layer to expose the first electrode layer;

[0030] A dielectric layer and a second electrode layer are formed on the first dielectric layer. The dielectric layer and the second electrode layer are stacked in sequence and fill the groove. The dielectric layer contacts the first electrode layer. The first electrode layer, the dielectric layer and the second electrode layer constitute a capacitor structure.

[0031] Optionally, the first electrode layer is a flat plate structure, and the dielectric layer and the second electrode layer are concave structures.

[0032] Optionally, after being stacked in sequence, the dielectric layer and the second electrode layer are recessed toward the direction close to the substrate to contact with the first electrode layer, and the contact portion between the two is the effective area of the capacitor structure.

[0033] Optionally, the dielectric layer also covers a portion of the surface of the first dielectric layer.

[0034] Optionally, the step of forming the first electrode layer on a portion of the surface of the substrate includes:

[0035] forming a first electrode material layer on the substrate; and,

[0036] Performing a first etching process to remove the first electrode plate material layer on a portion of the surface of the substrate, and the remaining first electrode plate material layer constitutes the first electrode plate layer;

[0037] performing a second etching process to form the groove in the first dielectric layer;

[0038] The step of forming the dielectric layer and the second polar plate layer on the first dielectric layer comprises:

[0039] Forming a dielectric material layer and a second electrode material layer on the first dielectric layer in sequence, wherein the dielectric material layer and the second electrode material layer are stacked in sequence and filled in the groove, and the dielectric material layer is in contact with the first electrode layer;

[0040] A third etching process is performed to remove at least a portion of the dielectric material layer and the second electrode material layer on the first dielectric layer, and the remaining dielectric material layer and the remaining second electrode material layer constitute the dielectric layer and the second electrode layer respectively.

[0041] Optionally, before performing the first etching process, a first photoresist layer is formed on the first electrode material layer, and the first photoresist layer is patterned using a first photomask, and when performing the first etching process, the first electrode material layer is etched using the patterned first photoresist layer;

[0042] Before performing the second etching process, forming a second photoresist layer on the first dielectric layer, patterning the second photoresist layer using a second photomask, and etching the first dielectric layer using the patterned second photoresist layer when performing the second etching process; and,

[0043] Before executing the third etching process, a third photoresist layer is formed on the second electrode material layer, and the third photoresist layer is patterned using a third mask. When executing the third etching process, the second electrode material layer and the dielectric material layer are etched using the patterned third photoresist layer.

[0044] Optionally, the first light mask, the second light mask and the third light mask are the same light mask.

[0045] Optionally, the second light mask and the third light mask are the same light mask.

[0046] Optionally, after the first photoresist layer is patterned by using the first photomask, a trimming process is performed on the patterned first photoresist layer to reduce the coverage of the patterned first photoresist layer.

[0047] Optionally, after forming the second electrode material layer, a first etch stop material layer is also formed on the second electrode material layer. When performing the third etching process, at least a portion of the first etch stop material layer, the second electrode material layer and the dielectric material layer on the first dielectric layer are removed, and the remaining first etch stop material layer constitutes a first etch stop layer.

[0048] Optionally, after forming the capacitor structure, the preparation method further includes:

[0049] A second dielectric layer is formed on the first dielectric layer and the capacitor structure; and,

[0050] A first interconnect structure is formed in the first dielectric layer and the second dielectric layer, the first interconnect structure is electrically connected to the first electrode layer, and a second interconnect structure is formed in the second dielectric layer, the second interconnect structure is electrically connected to the second electrode layer.

[0051] Optionally, before forming the first electrode layer on a portion of the surface of the substrate, the preparation method further includes:

[0052] forming a third dielectric layer on the substrate;

[0053] forming a metal layer in the third dielectric layer, wherein at least a portion of the surface of the metal layer is exposed by the third dielectric layer;

[0054] After forming the first electrode layer, the first electrode layer is located on the metal layer and is electrically connected to the metal layer;

[0055] After forming the capacitor structure, the preparation method further includes:

[0056] forming a second dielectric layer on the first dielectric layer and the capacitor structure; and,

[0057] A first interconnect structure is formed in the first dielectric layer and the second dielectric layer, the first interconnect structure being electrically connected to the metal layer; and a second interconnect structure is formed in the second dielectric layer, the second interconnect structure being electrically connected to the second electrode layer.

[0058] In the semiconductor device provided by the present invention, it includes a substrate, a first plate layer, a first dielectric layer, a dielectric layer and a second plate layer, wherein the first plate layer covers part of the surface of the substrate, the first dielectric layer covers the substrate and the first plate layer, the first dielectric layer has a groove, the groove penetrates the first dielectric layer to expose the first plate layer, the dielectric layer at least covers the inner wall of the groove and contacts with the first plate layer, the second plate layer covers the dielectric layer, and the first plate layer, the dielectric layer and the second plate layer constitute a capacitor structure. In the present invention, the dielectric layer contacts the first plate layer at the bottom of the groove, and the contacting part of the two is the effective area of the capacitor structure. The edge effect and etching damage caused by etching the dielectric layer and the second plate layer will not have too much impact on the effective area of the capacitor structure, avoiding leakage of the capacitor structure. The capacitor structure is not prone to failure and has better stability. Correspondingly, the present invention also provides a method for preparing a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 This is an electron microscope image of an existing MIM capacitor;

[0060] Figure 2 A flowchart of a method for preparing a semiconductor device provided in Embodiment 1 of the present invention;

[0061] Figure 3 to Figure 17 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in the first embodiment of the present invention, wherein:

[0062] Figure 3 A schematic structural diagram of sequentially forming a metal barrier material layer and a first electrode material layer on a third dielectric layer provided in the first embodiment of the present invention;

[0063] Figure 4 A schematic diagram of a structure of forming a first photoresist layer on a first electrode material layer provided in Embodiment 1 of the present invention;

[0064] Figure 5 A schematic diagram of the structure after the first photoresist layer is patterned using the first photomask provided in the first embodiment of the present invention;

[0065] Figure 6 A schematic diagram of a structure after a trimming process is performed on the patterned first photoresist layer provided in the first embodiment of the present invention;

[0066] Figure 7 A schematic diagram of the structure after the first etching process is performed according to the first embodiment of the present invention;

[0067] Figure 8 A schematic diagram of a structure in which a second etch stop layer and a sub-dielectric layer are sequentially formed on a substrate and a first electrode layer, provided in Embodiment 1 of the present invention;

[0068] Fig. 9 A schematic diagram of a structure in which a second photoresist layer is formed on a first dielectric layer according to a first embodiment of the present invention;

[0069] Fig.10 A schematic structural diagram of patterning the second photoresist layer using a second photomask provided in the first embodiment of the present invention;

[0070] Fig.11 A schematic diagram of the structure after the second etching process is performed according to the first embodiment of the present invention;

[0071] Fig.12 A schematic diagram of a structure in which a dielectric material layer, a second electrode material layer and a first etch stop material layer are sequentially formed conformally on a first dielectric layer and in a groove, provided in the first embodiment of the present invention;

[0072] Fig.13 A schematic structural diagram of forming a third photoresist layer on the first etch stop material layer provided in the first embodiment of the present invention;

[0073] Fig.14 A schematic diagram of the structure after the third photoresist layer is patterned by using a third photomask provided in the first embodiment of the present invention;

[0074] Fig.15 A schematic diagram of the structure after the third etching process is performed according to the first embodiment of the present invention;

[0075] Fig.16 A schematic structural diagram of forming a second dielectric layer on the first dielectric layer and the capacitor structure provided in the first embodiment of the present invention;

[0076] Fig.17 A schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention;

[0077] Fig.18A schematic structural diagram corresponding to corresponding steps of the method for preparing a semiconductor device provided in the second embodiment of the present invention;

[0078] Fig.19 A schematic diagram of the structure of a semiconductor device provided in Embodiment 2 of the present invention;

[0079] Wherein, the accompanying drawings are marked as follows:

[0080] 100-substrate; 201-third dielectric layer; 202-first dielectric layer; 202a-groove; 212-second etch stop layer; 222-sub dielectric layer; 203-second dielectric layer; 300-metal layer; 411-metal barrier material layer; 401-metal barrier layer; 412-first plate material layer; 402-first plate layer; 413-dielectric material layer; 403-dielectric layer; 414-second plate material layer; 40 4-second electrode layer; 415-first etch stop material layer; 405-first etch stop layer; 501-first photoresist layer; 502-second photoresist layer; 503-second photoresist layer; 601-first interconnect structure; 611-first connection pad; 621-first plug; 602-second interconnect structure; 612-second connection pad; 622-second plug; 701-first mask; 702-second mask; 703-third mask. DETAILED DESCRIPTION

[0081] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0082] Embodiment 1

[0083] Fig.17 Schematic diagram of the structure of the semiconductor device provided in this embodiment. Fig.17 As shown, the semiconductor device can be, for example, an image sensor or other device that needs to form a MIM capacitor, and the semiconductor device includes a substrate 100, a first electrode layer 402, a first dielectric layer 202, a dielectric layer 403, a second electrode layer 404, a second dielectric layer 203 and a third dielectric layer 201, wherein the first electrode layer 402, the dielectric layer 403 and the second electrode layer 404 constitute a capacitor structure.

[0084] Specifically, the substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates for carrying electronic components known to those skilled in the art. As an example, the substrate 100 is a silicon wafer. The substrate 100 may have a trench isolation structure, an active area, etc., and various device structures, such as a metal silicide layer, a gate structure, etc., may be formed on the substrate 100.

[0085] The third dielectric layer 201 is located on the substrate 100 and covers the entire surface of the substrate 100. A metal layer 300 is formed in the third dielectric layer 201. The metal layer 300 is entirely located in the third dielectric layer 201, but at least part of the surface of the metal layer 300 needs to be exposed by the third dielectric layer 201. In this embodiment, the third dielectric layer 201 also has a wiring layer ( Fig.17 The wiring layer is used to electrically connect to the device structure on the substrate 100, thereby leading out the device structure on the substrate 100. The metal layer 300 and the wiring layer can be located in the same layer and formed simultaneously, thereby simplifying the preparation process.

[0086] The third dielectric layer 201 may include a single-layer film or a multi-layer film. The material of the third dielectric layer 201 may be selected as needed, for example, it may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride and NDC (Nitrogen doped Silicon Carbide), and may also include borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-on glass (SOG) or tetraethyl orthosilicate (TEOS), etc.

[0087] Please continue reading Fig.17 , the first electrode layer 402 covers a portion of the surface of the substrate 100. Specifically, the first electrode layer 402 is located on the metal layer 300 and covers a portion of the surface of the metal layer 300, so that the first electrode layer 402 can be in contact with and electrically connected to the metal layer 300. In this embodiment, the first electrode layer 402 also covers a portion of the surface of the third dielectric layer 201, but it should not be limited to this, and the first electrode layer 402 can only cover a portion of the surface of the metal layer 300.

[0088] In this embodiment, the material of the first electrode layer 402 is TiN or W, and the material of the metal layer 300 is Cu. Since the conductivity of Cu is better than that of TiN and W, and the first electrode layer 402 and the metal layer 300 are electrically connected, the resistance of the first electrode layer 402 can be reduced, thereby reducing the requirement for the thickness of the first electrode layer 402 (the thickness of the first electrode layer 402 in this embodiment can be less than 600 angstroms), thereby reducing the total thickness of the capacitor structure and improving the integration.

[0089] Furthermore, since Cu ions have strong diffusivity, a metal barrier layer 401 is provided between the first electrode layer 402 and the metal layer 300. The metal barrier layer 401 can block Cu diffusion and avoid metal contamination. The material of the metal barrier layer 401 can be Ta or TaN.

[0090] Of course, in some embodiments, the material of the metal layer 300 may also be other conductive materials such as W, AL, etc., and the metal barrier layer 401 may be omitted.

[0091] Please continue reading Fig.17 , the first dielectric layer 202 covers the substrate 100 and the first electrode layer 402. Specifically, the first dielectric layer 202 is located on the third dielectric layer 201 and covers the first electrode layer 402. The first dielectric layer 202 includes a second etch stop layer 212 and a sub-dielectric layer 222, the second etch stop layer 212 conformally covers the surfaces of the third dielectric layer 201 and the first electrode layer 402, the sub-dielectric layer 222 covers the surface of the second etch stop layer 212, and the surface of the sub-dielectric layer 222 is flat.

[0092] As an optional embodiment, the sub-dielectric layer 222 may include a single-layer film or a multi-layer film. The material of the sub-dielectric layer 222 may be selected as needed, for example, silicon nitride or other high dielectric constant (high-k) materials, for example, at least one of Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfO2, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST) or TiO2. The function of the second etch stop layer 212 will be described below. The material of the second etch stop layer 212 may be silicon nitride, NDC or other dielectric materials.

[0093] Furthermore, the first dielectric layer 202 has a groove 202a, and the groove 202a penetrates the first dielectric layer 202 (penetrates the sub-dielectric layer 222 and the second etch stop layer 212) from the surface of the first dielectric layer 202, and exposes the first plate layer 402. In this embodiment, the dielectric layer 403 covers part of the surface of the first dielectric layer 202 and extends to cover the inner wall of the groove 202a, and the second plate layer 404 covers the dielectric layer 403. The dielectric layer 403 and the second plate layer 404 are stacked in sequence and conformally cover part of the surface of the first dielectric layer 202 and the inner wall of the groove 202a. Fig.17 It can be seen that the dielectric layer 403 is in contact with the first electrode layer 402 at the bottom of the groove 202a, and the contact portion between the two is the effective area of the capacitor structure. The edge effect and etching damage caused when etching the dielectric layer 403 and the second electrode layer 404 will only affect the end of the dielectric layer 403, but will not affect the contact portion between the dielectric layer 403 and the first electrode layer 402. Therefore, it will not have too much impact on the effective area of the capacitor structure, avoiding leakage of the capacitor structure, and the capacitor structure is not prone to failure, and has better stability.

[0094] Furthermore, the first electrode layer 402 is a flat plate structure, and the dielectric layer 403 and the second electrode layer 404 are recessed structures. Specifically, the dielectric layer 403 and the second electrode layer 404 are stacked in sequence and recessed toward the direction close to the substrate 100, and the dielectric layer 403 is in direct contact with the first electrode layer 402, and the contact portion of the two is the effective area of the capacitor structure.

[0095] In this embodiment, the dielectric layer 403 also covers a portion of the surface of the first dielectric layer 202. It can be understood that in some embodiments, when the etching process allows, the dielectric layer 403 may only cover the inner wall of the groove 202a, and does not extend to cover a portion of the surface of the first dielectric layer 202.

[0096] As an optional embodiment, the material of the second electrode layer 404 may be TiN or W, etc.; the second electrode layer 404 may include a single layer or a multilayer film. The material of the dielectric layer 403 may be silicon oxide, silicon nitride or other high dielectric constant (high-k) materials, for example, at least one of Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfO2, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST) or TiO2; the dielectric layer 403 may also include a single layer or a multilayer film.

[0097] Please continue reading Fig.17 , a first etch stop layer 405 is provided on the second electrode layer 404, and the first etch stop layer 405 conformally covers the second electrode layer 404, that is, the first etch stop layer 405 is also a recessed structure, and the function of the first etch stop layer 405 will be described below. The material of the first etch stop layer 405 can be silicon nitride, NDC or other dielectric materials.

[0098] Furthermore, the second dielectric layer 203 covers the first dielectric layer 202 and the capacitor structure. Specifically, the second dielectric layer 203 covers the first dielectric layer 202 and the first etching stop layer 405, and the surface of the second dielectric layer 203 is flat.

[0099] As an optional embodiment, the material of the second dielectric layer 203 can be selected as needed, and may include, for example, one or a combination of silicon oxide, silicon nitride, silicon oxynitride and NDC (Nitrogen doped Silicon Carbide), and may also include borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-on glass (SOG) or tetraethyl orthosilicate (TEOS), etc.

[0100] Furthermore, the second dielectric layer 203 and the first dielectric layer 202 have a first interconnection structure 601, and the first interconnection structure 601 is electrically connected to the metal layer 300, thereby electrically connected to the first electrode layer 402 through the metal layer 300, so as to lead out the first electrode layer 402. The second dielectric layer 203 also has a second interconnection structure 602, and the second interconnection structure 602 is electrically connected to the second electrode layer 404, so as to lead out the second electrode layer 404.

[0101] In this embodiment, the first interconnect structure 601 includes an electrically connected first plug 621 and a first connection pad 611, the first connection pad 611 is located in the second dielectric layer 203, and the surface of the first connection pad 611 is exposed by the second dielectric layer 203, the bottom surface of the first connection pad 611 is in contact with and electrically connected to the surface of the first plug 621, the bottom surface of the first plug 621 is in contact with and electrically connected to the metal layer 300 through the sub-dielectric layer 222 and the second etch stop layer 212, and the second etch stop layer 212 can be used as a stop layer when etching the first through hole accommodating the first plug 621. The second interconnect structure 602 includes an electrically connected second plug 622 and a second connection pad 612, the second plug 622 and the second connection pad 612 are both located in the second dielectric layer 203, the surface of the second connection pad 612 is exposed by the second dielectric layer 203, the bottom surface of the second connection pad 612 is in contact with and electrically connected to the surface of the second plug 622, the bottom surface of the second plug 622 is in contact with and electrically connected to the second electrode layer 404 through the first etch stop layer 405, and the first etch stop layer 405 can be used as a stop layer when etching the second through hole accommodating the second plug 622.

[0102] Based on this, this embodiment also provides a method for preparing the semiconductor device. Figure 2 A flow chart of a method for preparing a semiconductor device provided in this embodiment, such as Figure 2 As shown, the method for preparing the semiconductor device includes:

[0103] Step S100: providing a substrate;

[0104] Step S200: forming a first electrode layer on a portion of the surface of the substrate;

[0105] Step S300: forming a first dielectric layer on the substrate and the first electrode layer;

[0106] Step S400: forming a groove in the first dielectric layer, wherein the groove penetrates the first dielectric layer to expose the first electrode layer;

[0107] Step S500: forming a dielectric layer and a second electrode layer on the first dielectric layer, wherein the dielectric layer and the second electrode layer are stacked in sequence and filled in the groove, wherein the dielectric layer contacts the first electrode layer, and the first electrode layer, the dielectric layer and the second electrode layer constitute a capacitor structure.

[0108] Figure 3 to Figure 17 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in this embodiment. Figure 3 to Figure 17The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0109] like Figure 3 As shown, step S100 is performed to provide the substrate 100, in which a trench isolation structure and / or various doping regions are formed, and device structures such as a gate structure and a metal silicide layer are formed on the substrate 100 ( Figure 3 not shown).

[0110] Please continue reading Figure 3 A third dielectric layer 201 is formed on the substrate 100 , and the third dielectric layer 201 covers the surface of the substrate 100 . Then, a metal layer 300 is formed in the third dielectric layer 201 , and at least part of the surface of the metal layer 300 is exposed by the third dielectric layer 201 .

[0111] Please continue reading Figure 3 , execute step S200, and sequentially form a metal barrier material layer 411 and a first electrode material layer 412 on the third dielectric layer 201, wherein the metal barrier material layer 411 covers the surface of the third dielectric layer 201, and the first electrode material layer 412 covers the surface of the metal barrier material layer 411.

[0112] In some embodiments, the step of forming the metal barrier material layer 411 may be omitted.

[0113] like Figure 4 As shown, a first photoresist layer 501 is formed on the first electrode material layer 412, and the first photoresist layer 501 covers the surface of the first electrode material layer 412. In this embodiment, the first photoresist layer 501 is a positive photoresist layer.

[0114] like Figure 5 As shown, the first photoresist layer 501 is patterned by using a first mask 701 , and the patterned first photoresist layer 501 needs to cover a portion of the metal layer 300 .

[0115] like Figure 6 As shown, a trimming process (trim) is performed on the patterned first photoresist layer 501 to reduce the coverage of the patterned first photoresist layer 501 (but still need to cover part of the metal layer 300). The trimming process can be an overexposure or plasma treatment process.

[0116] like Figure 7As shown, the first etching process is performed, and the patterned first photoresist layer 501 is used as a mask to etch and remove part of the first electrode material layer 412 and the metal barrier material layer 411. The remaining first electrode material layer 412 and the metal barrier material layer 411 respectively constitute the first electrode layer 402 and the metal barrier layer 401. Afterwards, the patterned first photoresist layer 501 is removed. At this time, the first electrode layer 402 and the metal barrier layer 401 only cover part of the surface of the substrate 100. Specifically, the first electrode layer 402 and the metal barrier layer 401 cover part of the surface of the metal layer 300 and the third dielectric layer 201.

[0117] like Figure 8 As shown, step S300 is performed to sequentially form a second etch stop layer 212 and a sub-dielectric layer 222 on the substrate 100 and the first electrode layer 402 , wherein the second etch stop layer 212 and the sub-dielectric layer 222 constitute the first dielectric layer 202 , and the first dielectric layer 202 covers the substrate 100 and the first electrode layer 402 .

[0118] like Fig. 9 As shown, step S400 is performed to form a second photoresist layer 502 on the first dielectric layer 202, wherein the second photoresist layer 502 covers the surface of the first dielectric layer 202 (specifically, covers the surface of the sub-dielectric layer 222). In this embodiment, the second photoresist layer 502 is a negative photoresist layer.

[0119] like Fig.10 As shown, the second photoresist layer 502 is patterned by using a second photomask 702 , and the patterned second photoresist layer 502 needs to expose the first dielectric layer 202 above the first electrode layer 402 .

[0120] like Fig.11 As shown, the second etching process is performed, using the patterned second photoresist layer 502 as a mask, etching the first dielectric layer 202 until the surface of the first electrode layer 402 is exposed, forming a groove 202a, wherein the groove 202a penetrates the first dielectric layer 202 and exposes at least a portion of the surface of the first electrode layer 402. Afterwards, the patterned second photoresist layer 502 is removed.

[0121] like Fig.12 As shown, step S500 is performed to sequentially form a dielectric material layer 413, a second electrode material layer 414 and a first etch stop material layer 415 on the first dielectric layer 202 and in the groove 202a, and the dielectric material layer 413, the second electrode material layer 414 and the first etch stop material layer 415 are stacked in sequence and fill the groove 202a.

[0122] like Fig.13 As shown, a third photoresist layer 503 is formed on the first etch stop material layer 415, and the third photoresist layer 503 covers the surface of the first etch stop material layer 415. In this embodiment, the third photoresist layer 503 is a positive photoresist layer.

[0123] like Fig.14 As shown, the third photoresist layer 503 is patterned using a third mask 703 , and the patterned third photoresist layer 503 at least needs to cover the dielectric material layer 413 , the second electrode material layer 414 and the first etch stop material layer 415 in the groove 202 a .

[0124] like Fig.15 As shown, the third etching process is performed, and the first etching stop material layer 415, the second electrode material layer 414 and the dielectric material layer 413 are etched with the patterned third photoresist layer 503 as a mask until the surface of the first dielectric layer 202 is exposed, and the remaining first etching stop material layer 415, the second electrode material layer 414 and the dielectric material layer 413 constitute the first etching stop layer 405, the second electrode layer 404 and the dielectric layer 403 respectively. Afterwards, the patterned third photoresist layer 503 is removed, and at this time, the first electrode layer 402, the dielectric layer 403 and the second electrode layer 404 constitute a capacitor structure. Fig.15 It can be seen that the first etch stop layer 405, the second electrode layer 404 and the dielectric layer 403 are all recessed structures. The edge effect and etching damage when etching the first etch stop material layer 415, the second electrode material layer 414 and the dielectric material layer 413 will affect the end of the dielectric layer 403 (in this embodiment, the part covering the first dielectric layer 202), and the effective area of the capacitor structure is located at the bottom of the groove 202a, that is, the contact part of the dielectric layer 403 and the first electrode layer 402. Therefore, the edge effect and etching damage when etching the first etch stop material layer 415, the second electrode material layer 414 and the dielectric material layer 413 will not affect the effective area of the capacitor structure, thereby avoiding leakage of the capacitor structure, and the capacitor structure is not prone to failure and has better stability.

[0125] Further, the first electrode layer 402 is a flat plate structure, and the dielectric layer 403, the second electrode layer 404 and the first etch stop layer 405 are recessed structures. Specifically, the dielectric layer 403, the second electrode layer 404 and the first etch stop layer 405 are stacked in sequence and recessed toward the direction close to the substrate 100, and the dielectric layer 403 is in direct contact with the first electrode layer 402, and the contact portion of the two is the effective area of the capacitor structure.

[0126] In this embodiment, the patterns of the first mask 701, the second mask 702 and the third mask 703 are the same, so the first mask 701, the second mask 702 and the third mask 703 can be the same mask, that is, the first etching process, the second etching process and the third etching process use the same mask, and by matching different photoresists and etching methods, the mask is shared, which can save costs. In some embodiments, the first mask 701, the second mask 702 and the third mask 703 can also be different masks.

[0127] like Fig.16 As shown, a second dielectric layer 203 is formed on the first dielectric layer 202 and the capacitor structure, the second dielectric layer 203 covers the first dielectric layer 202 and the first etching stop layer 405, and the surface of the second dielectric layer 203 is flat.

[0128] like Fig.17 As shown, a first interconnect structure 601 is formed in the first dielectric layer 202 and the second dielectric layer 203 , and the first interconnect structure 601 is electrically connected to the metal layer 300 ; at the same time, a second interconnect structure 602 is formed in the second dielectric layer 203 , and the second interconnect structure 602 is electrically connected to the second electrode layer 404 .

[0129] The steps of forming the second dielectric layer 203, the first interconnect structure 601 and the second interconnect structure 602 may be: firstly forming a partial thickness of the second dielectric layer 203 on the first dielectric layer 202 and the capacitor structure; etching the second dielectric layer 203, the sub-dielectric layer 202 and the second etch stop layer 212 to form a first through hole exposing the metal layer 300, and the second etch stop layer 212 serves as an etch stop layer; at the same time, etching the second dielectric layer 203 and the first etch stop layer 405 to form a second through hole exposing the second electrode layer 404, and the first etch stop layer 405 serves as an etch stop layer. Conductive material is filled in the first through hole and the second through hole to form a first plug 621 and a second plug 622, respectively. The first plug 621 contacts and is electrically connected to the metal layer 300, and the second plug 622 contacts and is electrically connected to the second electrode layer 404; the remaining thickness of the second dielectric layer 203 is formed to cover the surfaces of the first plug 621 and the second plug 622; the second dielectric layer 203 is etched to form a third through hole and a fourth through hole that expose the surfaces of the first plug 621 and the second plug 622, respectively; and conductive material is filled in the third through hole and the fourth through hole to form a first connection pad 611 and a second connection pad 612, respectively. The first connection pad 611 contacts and is electrically connected to the first plug 621, and the second connection pad 612 contacts and is electrically connected to the second plug 622.

[0130] Embodiment 2

[0131] Fig.19 Schematic diagram of the structure of the semiconductor device provided in this embodiment. Fig.19 As shown, the difference from the first embodiment is that in this embodiment, the first interconnect structure 601 is located in the first dielectric layer 202 and the second dielectric layer 203, and is electrically connected to the first electrode layer 402, so as to lead out the first electrode layer 402.

[0132] Specifically, the first interconnect structure 601 includes an electrically connected first plug 621 and a first connection pad 611, the first connection pad 611 is located in the second dielectric layer 203, and the surface of the first connection pad 611 is exposed by the second dielectric layer 203, the bottom surface of the first connection pad 611 is in contact with and electrically connected to the surface of the first plug 621, and the bottom surface of the first plug 621 passes through the first dielectric layer 202 and is in contact with and electrically connected to the first electrode layer 402.

[0133] The steps of the method for preparing the semiconductor device in this embodiment are similar to those of the method for preparing the semiconductor device in the first embodiment, see Fig.18 and Figure 7 The only difference is that, when performing the first etching process, this embodiment removes less of the first electrode material layer 412 and the metal barrier material layer 411, so that the formed first electrode layer 402 and the metal barrier layer 401 cover a larger area, and the lateral boundary of the first electrode layer 402 and the metal barrier layer 401 needs to be located outside the lateral boundary of the second electrode layer 404 and the dielectric layer 403 to be formed subsequently, so that when the first interconnection structure 601 is formed, the first interconnection structure 601 can be electrically connected to the first electrode layer 402.

[0134] It should be noted that, in this embodiment, the second light mask 702 and the third light mask 703 can still use the same light mask, while the first light mask 701 needs to be designed separately.

[0135] In summary, in the semiconductor device provided in the embodiment of the present invention, it includes a substrate, a first plate layer, a first dielectric layer, a dielectric layer and a second plate layer, wherein the first plate layer covers part of the surface of the substrate, the first dielectric layer covers the substrate and the first plate layer, the first dielectric layer has a groove, the groove penetrates the first dielectric layer to expose the first plate layer, the dielectric layer at least covers the inner wall of the groove and contacts the first plate layer, the second plate layer covers the dielectric layer, and the first plate layer, the dielectric layer and the second plate layer constitute a capacitor structure. In the present invention, the dielectric layer contacts the first plate layer at the bottom of the groove, and the contact part of the two is the effective area of the capacitor structure. The edge effect and etching damage caused by etching the dielectric layer and the second plate layer will not have too much impact on the effective area of the capacitor structure, avoiding leakage of the capacitor structure, and the capacitor structure is not prone to failure and has better stability. Correspondingly, the present invention also provides a method for preparing a semiconductor device.

[0136] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0137] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0138] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0139] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: substrate; A first electrode layer, covering a portion of the surface of the substrate; A first dielectric layer, covering the substrate and the first electrode layer, wherein the first dielectric layer has a groove, and the groove penetrates the first dielectric layer to expose the first electrode layer; a dielectric layer, at least covering an inner wall of the groove and contacting the first electrode layer; as well as, The second electrode layer covers the dielectric layer. The first electrode layer, the dielectric layer and the second electrode layer form a capacitor structure.

2. The semiconductor device according to claim 1, wherein The first electrode layer is a flat plate structure, and the dielectric layer and the second electrode layer are concave structures.

3. The semiconductor device according to claim 2, wherein: After being stacked in sequence, the dielectric layer and the second electrode layer are recessed toward the direction close to the substrate to contact with the first electrode layer, and the contact portion between the two is the effective area of the capacitor structure.

4. The semiconductor device according to claim 1, wherein The dielectric layer also covers a portion of the surface of the first dielectric layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that Also includes: a second dielectric layer, covering the first dielectric layer and the capacitor structure; A first interconnect structure is located in the first dielectric layer and the second dielectric layer and is electrically connected to the first electrode layer; as well as, The second interconnect structure is located in the first dielectric layer and is electrically connected to the second electrode layer.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that Also includes: a second dielectric layer, covering the first dielectric layer and the capacitor structure; a third dielectric layer, located between the substrate and the first dielectric layer, wherein the third dielectric layer comprises a metal layer, and the first electrode layer is located on the metal layer and is electrically connected to the metal layer; a first interconnect structure, located in the first dielectric layer and the second dielectric layer, and electrically connected to the metal layer; as well as, The second interconnect structure is located in the first dielectric layer and is electrically connected to the second electrode layer.

7. The semiconductor device according to claim 6, wherein: The material of the first electrode layer is TIN or W, and the material of the metal layer is Cu.

8. The semiconductor device according to claim 7, wherein: A metal barrier layer is provided between the metal layer and the first electrode layer; and / or a thickness of the first electrode layer is less than 600 angstroms.

9. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a first electrode layer on a portion of the surface of the substrate; forming a first dielectric layer on the substrate and the first electrode layer; forming a groove in the first dielectric layer, wherein the groove penetrates the first dielectric layer to expose the first electrode layer; A dielectric layer and a second electrode layer are formed on the first dielectric layer. The dielectric layer and the second electrode layer are stacked in sequence and fill the groove. The dielectric layer contacts the first electrode layer. The first electrode layer, the dielectric layer and the second electrode layer constitute a capacitor structure.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The first electrode layer is a flat plate structure, and the dielectric layer and the second electrode layer are concave structures.

11. The method for preparing a semiconductor device according to claim 10, wherein: After being stacked in sequence, the dielectric layer and the second electrode layer are recessed toward the direction close to the substrate to contact with the first electrode layer, and the contact portion between the two is the effective area of the capacitor structure.

12. The method for preparing a semiconductor device according to claim 9, wherein: The dielectric layer also covers a portion of the surface of the first dielectric layer.

13. The method for preparing a semiconductor device according to claim 9, wherein: The step of forming the first electrode layer on a portion of the surface of the substrate comprises: forming a first electrode material layer on the substrate; and, Performing a first etching process to remove the first electrode plate material layer on a portion of the surface of the substrate, and the remaining first electrode plate material layer constitutes the first electrode plate layer; performing a second etching process to form the groove in the first dielectric layer; The step of forming the dielectric layer and the second polar plate layer on the first dielectric layer comprises: Forming a dielectric material layer and a second electrode material layer on the first dielectric layer in sequence, wherein the dielectric material layer and the second electrode material layer are stacked in sequence and filled in the groove, and the dielectric material layer is in contact with the first electrode layer; A third etching process is performed to remove at least a portion of the dielectric material layer and the second electrode material layer on the first dielectric layer, and the remaining dielectric material layer and the remaining second electrode material layer constitute the dielectric layer and the second electrode layer respectively.

14. The method for preparing a semiconductor device according to claim 13, wherein: Before performing the first etching process, a first photoresist layer is formed on the first electrode material layer, the first photoresist layer is patterned using a first photomask, and when performing the first etching process, the first electrode material layer is etched using the patterned first photoresist layer; Before performing the second etching process, a second photoresist layer is formed on the first dielectric layer, the second photoresist layer is patterned using a second photomask, and when performing the second etching process, the first dielectric layer is etched using the patterned second photoresist layer; as well as, Before executing the third etching process, a third photoresist layer is formed on the second electrode material layer, and the third photoresist layer is patterned using a third mask. When executing the third etching process, the second electrode material layer and the dielectric material layer are etched using the patterned third photoresist layer.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The first light mask, the second light mask and the third light mask are the same light mask.

16. The method for preparing a semiconductor device according to claim 14, wherein: The second light mask and the third light mask are the same light mask.

17. The method for preparing a semiconductor device according to claim 15 or 16, characterized in that: After the first photoresist layer is patterned by using the first photomask, a trimming process is performed on the patterned first photoresist layer to reduce the coverage of the patterned first photoresist layer.

18. The method for preparing a semiconductor device according to claim 13, wherein: After forming the second electrode material layer, a first etch stop material layer is also formed on the second electrode material layer. When performing the third etching process, at least part of the first etch stop material layer, the second electrode material layer and the dielectric material layer on the first dielectric layer are removed, and the remaining first etch stop material layer constitutes a first etch stop layer.

19. The method for preparing a semiconductor device according to claim 9, wherein: After forming the capacitor structure, the preparation method further includes: A second dielectric layer is formed on the first dielectric layer and the capacitor structure; and, A first interconnect structure is formed in the first dielectric layer and the second dielectric layer, the first interconnect structure is electrically connected to the first electrode layer, and a second interconnect structure is formed in the second dielectric layer, the second interconnect structure is electrically connected to the second electrode layer.

20. The method for preparing a semiconductor device according to claim 9, wherein: Before forming the first electrode layer on a portion of the surface of the substrate, the preparation method further includes: forming a third dielectric layer on the substrate; forming a metal layer in the third dielectric layer, wherein at least a portion of the surface of the metal layer is exposed by the third dielectric layer; After forming the first electrode layer, the first electrode layer is located on the metal layer and is electrically connected to the metal layer; After forming the capacitor structure, the preparation method further includes: forming a second dielectric layer on the first dielectric layer and the capacitor structure; and, A first interconnect structure is formed in the first dielectric layer and the second dielectric layer, the first interconnect structure being electrically connected to the metal layer; and a second interconnect structure is formed in the second dielectric layer, the second interconnect structure being electrically connected to the second electrode layer.