Semiconductor device and preparation method of semiconductor device

Abstract

The invention provides a semiconductor device and a preparation method of the semiconductor device. The semiconductor device comprises a semiconductor layer, a source region, a field limiting ring, a resistance region, a cut-off ring region, a passivation layer and an electrode layer, the semiconductor layer comprises a first side and a second side which are opposite, the source region is formed on the first side of the semiconductor layer, and the field limiting ring is formed on the peripheral side of the source region. The orthographic projection of the resistance region on the semiconductor layer is located in the orthographic projection of the source region on the semiconductor layer, and the resistance region is arranged close to the field limiting ring. The cut-off ring region is arranged on one side of the field limiting ring away from the source region. The passivation layer covers the resistance region, the field limiting ring and a part of the cut-off ring region. The electrode layer comprises a first electrode layer and a second electrode layer, the first electrode layer is located on the first side of the semiconductor layer, and the second electrode layer is located on the second side of the semiconductor layer. Therefore, through the scheme, the current density at the edge of the semiconductor device can be effectively reduced, the anti-current capability of the edge of the semiconductor device is enhanced, and the dynamic avalanche capability of the semiconductor device is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] With the continuous development of photovoltaic power generation, energy storage, servo motors and other fields, the performance requirements for power semiconductor devices are gradually increasing. Power semiconductor devices must not only have extreme capabilities, but also perform well in stability and reliability. Semiconductor devices (for example, PIN diodes) have high requirements for dynamic avalanche (EAS) capabilities in inductive circuits that require freewheeling. Dynamic avalanche capability refers to the ability of a diode to withstand the maximum voltage and current shocks without being damaged under rapidly changing current conditions. However, existing PIN diodes, especially the edge areas of PIN diodes, are more easily affected when subjected to high current shocks, thereby increasing the risk of PIN diode failure. Summary of the invention

[0003] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a semiconductor device, wherein the semiconductor device comprises:

[0004] a semiconductor layer, wherein the semiconductor layer comprises a first side and a second side opposite to each other;

[0005] a source region formed on a first side of the semiconductor layer;

[0006] A field limiting ring formed on the peripheral side of the source region;

[0007] A resistance region, wherein an orthographic projection of the resistance region on the semiconductor layer is located within an orthographic projection of the source region on the semiconductor layer, and the resistance region is arranged close to the field limiting ring;

[0008] A cut-off ring region, the cut-off ring region being arranged on a side of the field limiting ring away from the source region;

[0009] A passivation layer covering the resistance region, the field limiting ring and a portion of the cut-off ring region;

[0010] The electrode layer includes a first electrode layer and a second electrode layer. The first electrode layer is located on a first side of the semiconductor layer, and the second electrode layer is located on a second side of the semiconductor layer.

[0011] In a possible implementation, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are stacked;

[0012] The source region is formed on a side of the first semiconductor layer away from the second semiconductor layer. The first semiconductor layer is an N+ type semiconductor layer, and the second semiconductor layer is an N- type semiconductor layer.

[0013] In a possible implementation, the first electrode layer is an anode layer, and the second electrode layer is a cathode layer;

[0014] The first electrode layer is at least partially located on the passivation layer, the orthographic projection of the first electrode layer on the semiconductor layer overlaps with the orthographic projection of the passivation layer on the semiconductor layer, and the orthographic projection of the source region on the semiconductor layer is located within the orthographic projection of the first electrode layer on the semiconductor layer.

[0015] In a possible implementation, the source region is a P+ type semiconductor layer, the field limiting ring is a P+ type semiconductor layer, the resistance region is an N+ type semiconductor layer, and the cutoff ring region is an N+ type semiconductor layer.

[0016] Another object of the present application is to provide a method for preparing a semiconductor device, the method being applied to a plurality of the semiconductor devices provided in the present application, the method comprising:

[0017] Providing a semiconductor layer, wherein the semiconductor layer comprises a first side and a second side opposite to each other;

[0018] forming a first oxide layer on a first side of the semiconductor layer;

[0019] Etching the first oxide layer to form a first window for forming the source region and a second window for forming the field limiting ring;

[0020] doping the semiconductor layer with P-type carriers and P+-type carriers through the first window and the second window respectively, forming the source region and the field limiting ring correspondingly, and forming a second oxide layer on the source region and the field limiting ring;

[0021] The first oxide layer and the second oxide layer are etched to form a third window for forming a resistance region and a fourth window for forming a cut-off ring region, and N+ type carriers are doped into the semiconductor layer through the third window and the fourth window respectively to form the resistance region and the cut-off ring region respectively;

[0022] forming a passivation layer on the resistance region, the field limiting ring and a portion of the cut-off ring region;

[0023] The first electrode layer is formed on a first side of the semiconductor layer, and the second electrode layer is formed on a second side of the semiconductor layer.

[0024] In a possible implementation manner, in the step of forming a first oxide layer on the first side of the semiconductor layer, the method includes:

[0025] The semiconductor layer is treated by an oxidation process to form a first oxide layer with a thickness of 1.6um-2.2um on the surface of the semiconductor layer, wherein the temperature of the oxidation process is 1145°C to 1155°C, the treatment time is 300min to 500min, the flow rate of hydrogen is 7.0SLM / min, and the flow rate of oxygen is 5.0SLM / min.

[0026] In a possible implementation, the step of doping the semiconductor layer with P-type carriers and P+-type carriers through the first window and the second window respectively to form the source region and the field limiting ring accordingly, and forming a second oxide layer on the source region and the field limiting ring includes:

[0027] Injecting P-type carriers into the semiconductor layer through the first window and the second window, and correspondingly forming the source region and the field limiting ring through a push-junction process, wherein the push-junction process is processed at a temperature of 1275° C. to 1285° C., a processing time of 60 h to 80 h, a nitrogen flow rate of 10 SLM / min, and an oxygen flow rate of 2 SLM / min;

[0028] P+ type carriers are injected into the semiconductor layer in the first window and the second window, and the source region and the field limiting ring are correspondingly formed through a push-junction process, and the second oxide layer is formed on the source region and the field limiting ring. The temperature of the push-junction process is set to 1145°C to 1155°C, the processing time is set to 120min to 260min, the flow rate of nitrogen is 5.0SLM / min, the flow rate of oxygen is 5.0SLM / min, and the flow rate of hydrogen is 7.0SLM / min.

[0029] In a possible implementation, the first oxide layer and the second oxide layer are etched to form a third window for forming a resistance region and a fourth window for forming a cut-off ring region, and the semiconductor layer is doped with N+ type carriers through the third window and the fourth window respectively, and the steps of correspondingly forming the resistance region and the cut-off ring region include:

[0030] Etching the first oxide layer and the second oxide layer to form a third window for forming the resistance region and a fourth window for forming the cut-off ring region, and performing N+ type carrier injection into the semiconductor layer through the third window and the fourth window;

[0031] Forming a third oxide layer on the semiconductor layer through an oxidation process, wherein the oxidation process is performed at a temperature of 895° C. to 905° C., a treatment time of 200 min to 250 min, a nitrogen flow rate of 5.0 SLM / min, an oxygen flow rate of 5.0 SLM / min, and a hydrogen flow rate of 7.0 SLM / min;

[0032] The resistance area and the cut-off ring area are correspondingly formed at the third window and the fourth window by a push-junction process, and a fourth oxide layer is formed on the resistance area and the cut-off ring area, wherein the push-junction process is processed at a temperature of 1045°C to 1055°C, a processing time of 100min to 200min, a nitrogen flow rate of 5.0SLM / min, an oxygen flow rate of 5.0SLM / min, and a hydrogen flow rate of 7.0SLM / min.

[0033] In a possible implementation manner, before the steps of manufacturing the first electrode layer on the first side of the semiconductor layer and manufacturing the second electrode layer on the second side of the semiconductor layer, the method includes:

[0034] The semiconductor device is subjected to lead etching through photolithography and corrosion processes to form a lead hole structure.

[0035] In a possible implementation manner, in the step of manufacturing the first electrode layer on the first side of the semiconductor layer and manufacturing the second electrode layer on the second side of the semiconductor layer, the method includes:

[0036] A first electrode layer is manufactured by depositing a metal layer on a first side of the semiconductor layer;

[0037] A second electrode layer is formed by depositing a metal layer on the second side of the semiconductor layer.

[0038] Based on any of the above aspects, the embodiments of the present application provide a semiconductor device and a method for manufacturing the semiconductor device. Thus, the above solution can disperse the electric field by adding a resistance region at the edge of the source region to avoid excessive concentration, thereby reducing the current density at the edge of the semiconductor device, enhancing the current resistance of the edge of the semiconductor device, and thus improving the dynamic avalanche capability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of a semiconductor device provided in this embodiment;

[0041] Figure 2 A schematic diagram of a process for preparing a semiconductor device provided in this embodiment;

[0042] Figure 3a and Figure 3b for Figure 2 The corresponding process diagram;

[0043] Figure 4 Part of the process flow diagram provided for this embodiment.

[0044] Icon: 10-semiconductor layer, 100-first semiconductor layer, 110-second semiconductor layer, 20-source region, 200-first window, 30-field limiting ring, 300-second window, 40-resistance region, 400-third window, 50-cut-off ring region, 500-fourth window, 60-passivation layer, 600-first oxide layer, 610-second oxide layer, 620-third oxide layer, 630-fourth oxide layer, 70-electrode layer, 700-first electrode layer, 710-second electrode layer. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0048] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0049] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0050] In order to solve the technical problems mentioned in the aforementioned background technology, the inventor innovatively designed the following technical solution, and the specific implementation solution of the present application will be described in detail below with reference to the accompanying drawings.

[0051] See also Figure 1 , Figure 1 The schematic diagram of a semiconductor device 1 provided in this embodiment is as follows. The semiconductor device 1 comprises a semiconductor layer 10 , a source region 20 , a field limiting ring 30 , a resistor region 40 , a cut-off ring region 50 , a passivation layer 60 and an electrode layer 70 .

[0052] The semiconductor layer 10 includes a first side and a second side opposite to each other, and the source region 20 is formed on the first side of the semiconductor layer 10 . The field limiting ring 30 is formed on the peripheral side of the source region 20 .

[0053] In this embodiment, the semiconductor layer 10 can be an N-type high-resistance substrate polishing sheet, which is usually made of silicon, germanium or other semiconductor materials. The source region 20 is formed on the first side of the semiconductor layer 10, and the field limiting ring 30 is formed around the source region 20 to control the electric field distribution, reduce the electric field concentration, prevent the semiconductor device 1 from breaking down under high voltage, and help improve the voltage resistance of the semiconductor device 1.

[0054] The orthographic projection of the resistor region 40 on the semiconductor layer 10 is located within the orthographic projection of the source region 20 on the semiconductor layer 10 , and the resistor region 40 is disposed close to the field limiting ring 30 . The stop ring region 50 is disposed on a side of the field limiting ring 30 away from the source region 20 .

[0055] In this embodiment, the resistance region 40 is formed in the source region 20. The resistance region 40 can disperse the electric field and reduce the edge current of the semiconductor device 1, thereby reducing the edge current density of the semiconductor device 1, improving the edge current resistance, and improving the dynamic avalanche capability of the semiconductor device 1. The function of the cut-off ring region 50 is to further control the electric field distribution, improve the withstand voltage capability of the semiconductor device 1, and prevent edge breakdown under high voltage.

[0056] The passivation layer 60 covers the resistor region 40, the field limiting ring 30 and part of the cut-off ring region 50. The electrode layer 70 includes a first electrode layer 700 and a second electrode layer 710. The first electrode layer 700 is located on the first side of the semiconductor layer 10, and the second electrode layer 710 is located on the second side of the semiconductor layer 10.

[0057] It is worth noting that the passivation layer 60 can be made of silicon dioxide or other insulating materials. The function of the passivation layer 60 is to protect the surface of the semiconductor device, prevent the generation of surface states, and improve the stability and reliability of the semiconductor device.

[0058] Further, please see again Figure 1 The semiconductor layer 10 includes a first semiconductor layer 100 and a second semiconductor layer 110, and the first semiconductor layer 100 and the second semiconductor layer 110 are stacked;

[0059] The source region 20 is formed on a side of the first semiconductor layer 100 away from the second semiconductor layer 110 . The first semiconductor layer 100 is an N-type semiconductor layer (N-type lightly doped semiconductor layer), and the second semiconductor layer 110 is an N+ type semiconductor layer (N-type heavily doped semiconductor layer).

[0060] In this embodiment, the second semiconductor layer 110, as the bottom layer of the device, has a higher doping concentration to ensure good electron injection and collection. The first semiconductor layer 100 has a lower doping concentration, and as a base region or drift region, the N-type semiconductor layer provides a low electric field region, allowing electrons to drift therein and not recombine quickly.

[0061] Further, please see again Figure 1 The first electrode layer 700 is an anode layer, and the second electrode layer 710 is a cathode layer.

[0062] The first electrode layer 700 is at least partially located on the passivation layer 60 , the orthographic projection of the first electrode layer 700 on the semiconductor layer 10 overlaps with the orthographic projection of the passivation layer 60 on the semiconductor layer 10 , and the orthographic projection of the source region 20 on the semiconductor layer 10 is located within the orthographic projection of the first electrode layer 700 on the semiconductor layer 10 .

[0063] In this embodiment, the first electrode layer 700 is an anode layer, and its main function is to inject holes. The second electrode layer 710 is a cathode layer, and its main function is to inject electrons. This structure can achieve charge separation and current control inside the semiconductor device 1. In addition, the orthographic projection of the source region 20 on the semiconductor layer 10 is located within the orthographic projection of the first electrode layer 700 on the semiconductor layer 10, which helps to control the injection and collection of current and is a key factor in improving the performance of the semiconductor device 1.

[0064] Further, the source region 20 is a P+ type semiconductor layer (P-type heavily doped semiconductor layer), the field limiting ring 30 is a P+ type semiconductor layer, the resistance region 40 is an N+ type semiconductor layer, and the cutoff ring region 50 is an N+ type semiconductor layer.

[0065] In this embodiment, the source region 20 is a P+ type semiconductor layer, which is doped with a higher concentration of donor impurities to provide a large number of electrons and form a low-resistance ohmic contact. The field limiting ring 30 is also a P+ type semiconductor layer, and the electric field concentration is reduced by introducing an additional doping area to improve the withstand voltage of the semiconductor device. The resistance region 40 of the N+ type semiconductor layer is usually doped with a higher concentration of donor impurities. The design of the resistance region 40 helps to control the flow of current and has a damping effect on the current at the edge of the semiconductor device. The cut-off ring region 50 is also an N+ type semiconductor layer. Its design helps to prevent the flow of current in the off state and improve the cut-off capability of the semiconductor device 1.

[0066] Based on the same concept, the present application also provides a method for preparing a semiconductor device 1, which is applied to the semiconductor device 1 in the above embodiment, see Figure 2 , Figure 3a and Figure 3b , Figure 3a and Figure 3b for Figure 2 Corresponding to the process flow chart, the method includes the following steps.

[0067] Step S110, providing a semiconductor layer 10, wherein the semiconductor layer 10 includes a first side and a second side opposite to each other;

[0068] In this step, the semiconductor layer 10 can be an N-type high-resistance substrate polishing sheet, and the semiconductor layer 10 includes a first semiconductor layer 100 and a second semiconductor layer 110. The first semiconductor layer 100 is an N-type semiconductor layer, and the second semiconductor layer 110 is an N+ type semiconductor layer. The first semiconductor layer 100 and the second semiconductor layer 110 are stacked.

[0069] Step S120, forming a first oxide layer 600 on the first side of the semiconductor layer 10;

[0070] In this embodiment, a thin first oxide layer 600 is grown or deposited on the first side of the semiconductor layer 10. The first oxide layer 600 is usually silicon dioxide. The first oxide layer 600 helps to protect the surface of the semiconductor layer 10 and prevent contamination during subsequent processing.

[0071] Step S130 , etching the first oxide layer 600 to form a first window 200 for forming the source region 20 and a second window 300 for forming the field limiting ring 30 .

[0072] In this step, the first window 200 and the second window 300 are etched on the first oxide layer 600 by photolithography and etching techniques. These windows will be used in the subsequent doping steps to form the source region 20 and the field limiting ring 30.

[0073] In step S140 , the semiconductor layer 10 is doped with P-type carriers and P+-type carriers through the first window 200 and the second window 300 , respectively, to form the source region 20 and the field limiting ring 30 , and a second oxide layer 610 is formed on the source region 20 and the field limiting ring 30 .

[0074] In this embodiment, P-type carriers and P+ type carriers can be doped into the semiconductor layer 10 by ion implantation or diffusion. A second oxide layer 610 is grown on the newly formed source region 20 and field limiting ring 30 and stacked on the first oxide layer 600 for further protection and isolation.

[0075] In step S150, the first oxide layer 600 and the second oxide layer 610 are etched to form a third window 400 for forming the resistance area 40 and a fourth window 500 for forming the cut-off ring area 50. N+ type carriers are doped into the semiconductor layer 10 through the third window 400 and the fourth window 500, respectively, to form the resistance area 40 and the cut-off ring area 50 accordingly.

[0076] In this embodiment, the third window 400 and the fourth window 500 are etched on the first oxide layer 600 and the second oxide layer 610 by photolithography and etching techniques, and these windows will be used to form the resistance area 40 and the cut-off ring area 50. Then, the semiconductor layer 10 is doped with N+ type carriers by ion implantation or diffusion and other doping techniques to form the resistance area 40 and the cut-off ring area 50.

[0077] In step S160 , a passivation layer 60 is formed on the resistor region 40 , the field limiting ring 30 and a portion of the stop ring region 50 .

[0078] In the present embodiment, the passivation layer 60 includes a first oxide layer 600, a second oxide layer 610, a third oxide layer 620, and a fourth oxide layer 630. In addition, the stacked first oxide layer 600, the second oxide layer 610, the third oxide layer 620, and the fourth oxide layer 630 can be directly used as the passivation layer 60, or additional passivation materials can be added through additional chemical vapor deposition (CVD) or physical vapor deposition (PVD) steps to enhance the passivation effect. The functions of the passivation layer 60 include reducing surface states and interface states, reducing the surface recombination rate of carriers, improving the withstand voltage and stability of the device, and reducing the parasitic capacitance of the device.

[0079] Step S170 , forming a first electrode layer 700 on the first side of the semiconductor layer 10 , and forming a second electrode layer 710 on the second side of the semiconductor layer 10 .

[0080] In this step, the first electrode layer 700 is an anode layer, and the second electrode layer 710 is a cathode layer. These electrode layers 70 are the key to connecting the device with an external circuit and are used to transfer current and apply voltage.

[0081] Furthermore, step S120 may also be implemented in the following manner:

[0082] The semiconductor layer 10 is treated by an oxidation process to form a first oxide layer 600 with a thickness of 1.6um-2.2um on the surface of the semiconductor layer 10, wherein the temperature of the oxidation process is 1145°C~1155°C, the processing time is 300min~500min, the flow rate of hydrogen is 7.0SLM / min, and the flow rate of oxygen is 5.0SLM / min.

[0083] In this embodiment, the semiconductor layer 10 can be placed in a special oxidation furnace, and the formed first oxide layer 600 not only provides physical protection to prevent the semiconductor layer 10 from being contaminated during subsequent processing, but also has the function of insulation and controlling the flow of electrons.

[0084] Furthermore, step S140 may also be implemented in the following manner:

[0085] First, P-type carriers are injected into the semiconductor layer 10 through the first window 200 and the second window 300, and the source region 20 and the field limiting ring 30 are correspondingly formed through a push-junction process, wherein the push-junction process is processed at a temperature of 1275°C to 1285°C, a processing time of 60h to 80h, a nitrogen flow rate of 10SLM / min, and an oxygen flow rate of 2SLM / min.

[0086] Next, P+ type carriers are injected into the semiconductor layer 10 through the first window 200 and the second window 300, and a source region 20 and a field limiting ring are correspondingly formed through a push-junction process. At the same time, a second oxide layer is formed on the source region 20 and the field limiting ring. The temperature of the push-junction process is set to 1145°C to 1155°C, the processing time is set to 120min to 260min, the flow rate of nitrogen is 5.0SLM / min, the flow rate of oxygen is 5.0SLM / min, and the flow rate of hydrogen is 7.0SLM / min.

[0087] In this embodiment, the main purpose of the push-junction process is to diffuse dopants (such as P-type carriers) further in the semiconductor layer 10 through high temperature treatment. First, the injection of P-type carriers can form a region with a lower doping concentration, which is used to create a low electric field region to help control the electric field distribution in the semiconductor device 1. Subsequently, the injection of P+ type carriers is used to form a region with a high doping concentration, and then a PN junction is formed through the push-junction process. At the same time, a second oxide layer 610 is formed on the source region 20 and the field limiting ring 30 to provide additional protection and insulation.

[0088] For further information, see Figure 4 , Figure 4 for Figure 2 In the preparation flow chart of step S150, step S150 can also be implemented in the following manner:

[0089] First, the first oxide layer 600 and the second oxide layer 610 are etched to form a third window 400 for forming the resistance region 40 and a fourth window 500 for forming the cut-off ring region 50 , and N+ type carriers are injected into the semiconductor layer 10 from the third window 400 and the fourth window 500 .

[0090] Next, a third oxide layer 620 is formed on the semiconductor layer 10 by an oxidation process, wherein the oxidation process temperature is 895°C to 905°C, the processing time is 200min to 250min, the flow rate of nitrogen is 5.0SLM / min, the flow rate of oxygen is 5.0SLM / min, and the flow rate of hydrogen is 7.0SLM / min.

[0091] Finally, a push-junction process is performed at the third window 400 and the fourth window 500 to form a resistance area 40 and a cut-off ring area 50 respectively, and a fourth oxide layer 630 is formed on the resistance area 40 and the cut-off ring area 50, wherein the push-junction process is performed at a temperature of 1045°C to 1055°C, a processing time of 100min to 200min, a nitrogen flow rate of 5.0SLM / min, an oxygen flow rate of 5.0SLM / min, and a hydrogen flow rate of 7.0SLM / min.

[0092] Further, before step S170, the method includes:

[0093] The semiconductor device 1 is subjected to lead etching through photolithography and etching processes to form a lead hole structure.

[0094] In this step, after the passivation layer 60 is formed on the semiconductor device 1, a desired lead hole structure pattern is formed on the semiconductor device 1 through photolithography and etching processes. For example, a photoresist (which may be a positive photoresist or a negative photoresist) may be coated on the surface of the semiconductor device 1, and then the pattern may be transferred through an exposure and development step, and then the portion of the passivation layer 60 not protected by the photoresist may be removed through an etching process, so as to form a contact hole on the semiconductor device 1 for connecting the electrode layer 70.

[0095] Furthermore, step S170 may also be implemented in the following manner:

[0096] First, a first electrode layer 700 is manufactured by depositing a metal layer on a first side of the semiconductor layer 10 .

[0097] Next, a metal layer is deposited on the second side of the semiconductor layer 10 to obtain a second electrode layer 710 .

[0098] In this embodiment, a metal layer is deposited on the first side and the second side of the semiconductor layer 10 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a first electrode layer 700 and a second electrode layer 710. These metals generally have good electrical conductivity and adhesion, such as aluminum, copper, gold or their alloys.

[0099] In summary, the present application provides a semiconductor device and a method for preparing a semiconductor device. The semiconductor device includes a semiconductor layer, a source region, a field limiting ring, a resistor region, a cut-off ring region, a passivation layer and an electrode layer. The semiconductor includes a first side and a second side relative to each other. The source region is formed on the first side of the semiconductor layer, and the field limiting ring is formed on the peripheral side of the source region. The orthographic projection of the resistor region on the semiconductor layer is located within the orthographic projection of the source region on the semiconductor layer, and the resistor region is arranged close to the field limiting ring. The cut-off ring region is arranged on the side of the field limiting ring away from the source region. The passivation layer covers the resistor region, the field limiting ring and part of the cut-off ring region. The electrode layer includes a first electrode layer and a second electrode layer, the first electrode layer is located on the first side of the semiconductor layer, and the second electrode layer is located on the second side of the semiconductor layer. In this way, through the above scheme, the current density at the edge of the semiconductor device can be effectively reduced, the edge current resistance of the semiconductor device can be enhanced, and the dynamic avalanche capability of the semiconductor device can be improved.

[0100] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a semiconductor layer, wherein the semiconductor layer comprises a first side and a second side opposite to each other; a source region formed on a first side of the semiconductor layer; A field limiting ring formed on the peripheral side of the source region; A resistance region, wherein an orthographic projection of the resistance region on the semiconductor layer is located within an orthographic projection of the source region on the semiconductor layer, and the resistance region is arranged close to the field limiting ring; A cut-off ring region, the cut-off ring region being arranged on a side of the field limiting ring away from the source region; A passivation layer covering the resistance region, the field limiting ring and a portion of the cut-off ring region; The electrode layer includes a first electrode layer and a second electrode layer. The first electrode layer is located on a first side of the semiconductor layer, and the second electrode layer is located on a second side of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein The semiconductor layer includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are stacked; The source region is formed on a side of the first semiconductor layer away from the second semiconductor layer. The first semiconductor layer is an N+ type semiconductor layer, and the second semiconductor layer is an N- type semiconductor layer.

3. The semiconductor device according to claim 1, wherein The first electrode layer is an anode layer, and the second electrode layer is a cathode layer; The first electrode layer is at least partially located on the passivation layer, the orthographic projection of the first electrode layer on the semiconductor layer overlaps with the orthographic projection of the passivation layer on the semiconductor layer, and the orthographic projection of the source region on the semiconductor layer is located within the orthographic projection of the first electrode layer on the semiconductor layer.

4. The semiconductor device according to claim 1, wherein The source region is a P+ type semiconductor layer, the field limiting ring is a P+ type semiconductor layer, the resistance region is an N+ type semiconductor layer, and the cutoff ring region is an N+ type semiconductor layer.

5. A method for preparing a semiconductor device, the method being used to prepare the semiconductor device according to any one of claims 1 to 4, the method comprising: Providing a semiconductor layer, wherein the semiconductor layer comprises a first side and a second side opposite to each other; forming a first oxide layer on a first side of the semiconductor layer; Etching the first oxide layer to form a first window for forming the source region and a second window for forming the field limiting ring; doping the semiconductor layer with P-type carriers and P+-type carriers through the first window and the second window respectively, forming the source region and the field limiting ring correspondingly, and forming a second oxide layer on the source region and the field limiting ring; The first oxide layer and the second oxide layer are etched to form a third window for forming a resistance region and a fourth window for forming a cut-off ring region, and N+ type carriers are doped into the semiconductor layer through the third window and the fourth window respectively to form the resistance region and the cut-off ring region respectively; forming a passivation layer on the resistance region, the field limiting ring and a portion of the cut-off ring region; The first electrode layer is formed on a first side of the semiconductor layer, and the second electrode layer is formed on a second side of the semiconductor layer.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: In the step of forming a first oxide layer on the first side of the semiconductor layer, the method comprises: The semiconductor layer is treated by an oxidation process to form a first oxide layer with a thickness of 1.6um-2.2um on the surface of the semiconductor layer, wherein the temperature of the oxidation process is 1145°C to 1155°C, the treatment time is 300min to 500min, the flow rate of hydrogen is 7.0SLM / min, and the flow rate of oxygen is 5.0SLM / min.

7. The method for preparing a semiconductor device according to claim 5, characterized in that: The step of doping the semiconductor layer with P-type carriers and P+-type carriers through the first window and the second window respectively to form the source region and the field limiting ring accordingly, and forming a second oxide layer on the source region and the field limiting ring at the same time, comprises: Injecting P-type carriers into the semiconductor layer through the first window and the second window, and correspondingly forming the source region and the field limiting ring through a push-junction process, wherein the push-junction process is processed at a temperature of 1275° C. to 1285° C., a processing time of 60 h to 80 h, a nitrogen flow rate of 10 SLM / min, and an oxygen flow rate of 2 SLM / min; P+ type carriers are injected into the semiconductor layer in the first window and the second window, and the source region and the field limiting ring are correspondingly formed through a push-junction process, and the second oxide layer is formed on the source region and the field limiting ring. The temperature of the push-junction process is set to 1145°C to 1155°C, the processing time is set to 120min to 260min, the flow rate of nitrogen is 5.0SLM / min, the flow rate of oxygen is 5.0SLM / min, and the flow rate of hydrogen is 7.0SLM / min.

8. The method for preparing a semiconductor device according to claim 5, wherein: The step of etching the first oxide layer and the second oxide layer to form a third window for forming a resistance region and a fourth window for forming a cut-off ring region, and performing N+ type carrier doping on the semiconductor layer through the third window and the fourth window to form the resistance region and the cut-off ring region respectively, comprises: Etching the first oxide layer and the second oxide layer to form a third window for forming the resistance region and a fourth window for forming the cut-off ring region, and performing N+ type carrier injection into the semiconductor layer through the third window and the fourth window; Forming a third oxide layer on the semiconductor layer through an oxidation process, wherein the oxidation process is performed at a temperature of 895° C. to 905° C., a treatment time of 200 min to 250 min, a nitrogen flow rate of 5.0 SLM / min, an oxygen flow rate of 5.0 SLM / min, and a hydrogen flow rate of 7.0 SLM / min; The resistance area and the cut-off ring area are correspondingly formed at the third window and the fourth window by a push-junction process, and a fourth oxide layer is formed on the resistance area and the cut-off ring area, wherein the push-junction process is processed at a temperature of 1045°C to 1055°C, a processing time of 100min to 200min, a nitrogen flow rate of 5.0SLM / min, an oxygen flow rate of 5.0SLM / min, and a hydrogen flow rate of 7.0SLM / min.

9. The method for preparing a semiconductor device according to claim 5, wherein: Before the steps of manufacturing the first electrode layer on the first side of the semiconductor layer and manufacturing the second electrode layer on the second side of the semiconductor layer, the method comprises: The semiconductor device is subjected to lead etching through photolithography and corrosion processes to form a lead hole structure.

10. The method for preparing a semiconductor device according to claim 5, wherein: In the step of manufacturing the first electrode layer on the first side of the semiconductor layer and manufacturing the second electrode layer on the second side of the semiconductor layer, the method comprises: A first electrode layer is manufactured by depositing a metal layer on a first side of the semiconductor layer; A second electrode layer is formed by depositing a metal layer on the second side of the semiconductor layer.

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