Gating material, semiconductor device and memory

Abstract

The invention relates to a gate material, a semiconductor device and a memory. The gate material comprises a base material and a doping element doped in the base material. The base material comprises a chalcogenide amorphous compound, and the doping element is at least bonded and connected with a chalcogenide element in the chalcogenide amorphous compound to form a complete tetrahedral structure and / or octahedral structure. The doping element is added into the matrix material of the gating material, so that the content of the stable tetrahedral structure and / or octahedral structure in the gating material is increased, the amorphous thermal stability of the gating material can be effectively improved, the current control capability of the gating layer is improved, and the performance of the gating layer is improved. Therefore, the reliability of the semiconductor device with the gating layer is improved, and the power consumption of the semiconductor device is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a gating material, a semiconductor device and a memory. Background Art

[0002] Phase Change Memory (PCM) is a new type of non-volatile memory. In order to improve storage density, PCM often uses a cross memory array. In order to suppress the influence of crosstalk current on the cross memory array, in addition to the phase change memory layer for data storage, the PCM usually includes a selector arranged in series with the phase change memory layer. The selector is one of the core components of the phase change memory, and its structure includes a selector layer and a bottom electrode and a top electrode located on opposite sides of the selector layer.

[0003] At present, the gating layer is usually an Ovonic Threshold Switch (OTS) made of sulfur-based amorphous materials. The principle of OTS gating is to achieve the change from high resistance to low resistance through the threshold switching of sulfur-based amorphous materials, thereby controlling the current to complete the process of writing (SET), erasing (RESET), and reading (READ) data in the phase change storage layer. Usually, the thermal influence of the gating layer will cause the sulfur-based amorphous material in the gating layer to face the risk of amorphous instability and crystallization. If the gating material crystallizes, the gating tube will be unable to distinguish between high resistance and low resistance states, and the ability to control current will be weakened, causing data to be miswritten, erased, or misread, reducing the data reliability and cycle durability of the phase change memory. Therefore, in order to improve the performance of the phase change memory, it is necessary to improve the temperature resistance of the gating tube.

[0004] Currently, amorphous sulfur compounds based on GeAsSe or AsSe are commonly used materials for the gating layer. However, the amorphous sulfur compounds are greatly affected by the thermal disturbance of the phase change memory layer and are prone to crystallization, which weakens the gating tube's ability to control current, thereby reducing the reliability of data storage in the phase change memory and increasing power consumption. Summary of the invention

[0005] The purpose of the present application is to provide a gating material, a semiconductor device and a memory, aiming to provide a gating material with high amorphous thermal stability, so as to improve the control ability of the gating layer over the current, thereby improving the reliability of the semiconductor device using the gating layer and reducing the power consumption of the semiconductor device.

[0006] In order to achieve the above object, according to a first aspect of the present application, a gating material is provided, wherein the semiconductor device comprises a gating layer, and the gating material comprises a base material and a doping element doped in the base material;

[0007] Among them, the matrix material includes a chalcogenide amorphous compound, and the doping element is bonded to at least the chalcogen element in the chalcogenide amorphous compound to form a complete tetrahedral structure and / or octahedral structure.

[0008] In some embodiments, the doping element is bonded to any one element in the chalcogenide amorphous compound, and the bond energy of the chemical bond formed between the doping element and any one element in the chalcogenide amorphous compound is greater than the bond energy of the chemical bond formed between the same element or different elements in the chalcogenide amorphous compound.

[0009] In some embodiments, the atomic radius of the doping element is greater than the atomic radius of any one element in the chalcogenide amorphous compound, and the percentage range of the atomic radius difference between the doping element and any one element in the chalcogenide amorphous compound is 15% to 30%.

[0010] In some embodiments, the electronegativity of the doping element is less than the electronegativity of any one element in the chalcogenide amorphous compound, and the absolute value of the electronegativity difference between the doping element and the elements in the chalcogenide amorphous compound is greater than the absolute value of the electronegativity difference between different elements in the chalcogenide amorphous compound.

[0011] In some embodiments, the doping element includes at least one of Sc element, Hf element, Zr element, In element and Nb element.

[0012] In some embodiments, the chalcogenide amorphous compound includes As element and Se element, and the chemical general formula of the gate material is T a As x Se (100-a-x) , where T represents the doping element, and both a and x represent the molar percentages of the elements, 0 < a ≤ 10, and 25 ≤ x ≤ 45.

[0013] In some embodiments, the gate material includes at least one of Zr5As 35 Se 60 and Hf5As 35 Se 60 .

[0014] In some embodiments, the chalcogenide amorphous compound includes Ge element, As element and Se element, and the chemical general formula of the gate material is T a Ge x As y Se (100-a-x-y) , where T represents the doping element, and a, x and y all represent the molar percentages of the elements, 0 < a ≤ 10, 0 < x ≤ 25, 25 ≤ y ≤ 45.

[0015] In some embodiments, the gating material comprises Hf5Ge 18 As 30 Se 47 and Zr3In5Ge 15 As 27 Se 50 At least one of .

[0016] According to a second aspect of the present application, a semiconductor device is provided. The semiconductor device includes a gating layer, and a material of the gating layer includes the gating material described above.

[0017] According to a third aspect of the present application, a memory is provided, comprising a storage layer and a gating layer connected in series, wherein a material of the gating layer comprises the gating material described above.

[0018] The present application provides a gating material, a semiconductor device and a memory. The base material of the gating material is a sulfur-based amorphous compound. Since the doping element is at least bonded to the sulfur-based element in the sulfur-based amorphous compound to form a complete tetrahedral structure and / or octahedral structure, the doping element is used to perform single element doping or multi-element combination co-doping in the sulfur-based amorphous compound, so that the number of stable tetrahedral structures and / or octahedral structures in the gating material increases, the crystallization temperature of the gating material is increased, and thus the amorphous thermal stability of the gating material is improved. Improving the amorphous thermal stability of the gating material improves the tolerance of the gating material to the ambient temperature, thereby improving the control ability of the gating layer to the current, which is beneficial to improving the reliability of the semiconductor device using the gating layer and reducing the power consumption of the semiconductor device.

[0019] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0021] Figure 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor device provided in an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of a tetrahedral structure formed by combining a doping element and a chalcogenide element provided in an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of an octahedral structure formed by combining a doping element and a chalcogenide element provided in an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of the structure of a memory provided by an embodiment of the present application;

[0025] Figure 5 It is a schematic diagram of a partial three-dimensional structure of a phase change memory provided in an embodiment of the present application;

[0026] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure of the middle A area;

[0027] Figure 7 It is a structural diagram of a storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0030] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0031] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer and one or more dielectric layers.

[0032] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0033] Typically, a phase change memory (PCM) includes a plurality of phase change memory cells distributed in an array. In order to prevent the leakage current of the read, erase, and write operations of the target phase change memory cell from affecting the adjacent phase change memory cell, a selector that acts as a switch is configured for each phase change memory cell. The phase change memory uses a selector to select addresses and is beneficial for reducing the leakage current of the memory cell. Therefore, the stability of the electrical characteristics of the selector (such as the ability to control current) directly determines the reliability of the memory cell. Typically, the select layer in the selector is an Ovonic Threshold Switching (OTS) made of a sulfur compound, and its gating function needs to be realized in an amorphous structure state. Therefore, the gating material needs to have strong amorphous thermal stability. It can be understood that the gating material is the material of the gating layer.

[0034] Methods for improving the temperature resistance of the gate tube generally include the following two methods: the first method is to add a thermal barrier to the gate tube, such as adding a heat shielding layer between the phase change memory layer and the gate layer to block the temperature of the phase change memory layer and prevent heat from being transferred to the gate layer; the second method is to increase the crystallization temperature of the sulfur-based amorphous material in the gate layer, thereby improving the amorphous thermal stability of the gate material. However, the first method will increase the complexity of the phase change memory structure and increase the process cost and difficulty of preparation. Compared with the first method, the second method has less impact on the semiconductor preparation process flow and has better compatibility with various current phase change memory structures.

[0035] At present, in the relevant research on phase change storage layer materials, it is proposed to increase the crystallization temperature of the phase change storage layer material by doping with specific elements (such as scandium (Sc) elements, tantalum (Ta) elements, etc.), so as to enhance the amorphous stability of the phase change storage layer material. In addition, in the patent CN111463346B on the gating material, it is proposed to enhance the amorphous thermal stability of the gating material by doping with TT elements. Therefore, element doping modification based on the sulfur-based amorphous material in the gating layer can improve the amorphous stability of the gating material.

[0036] Since the characteristic of amorphous materials is that there is no long-range ordered atomic arrangement inside the material, amorphous materials can be obtained by destroying the long-range order in the crystal structure. Introducing defects into the crystal structure is a common method to destroy its internal long-range order. Defects can be introduced into the crystal structure by applying external stress, irradiation, element doping, rapid cooling of the melt, etc. Among them, the element doping method conforms to the preparation process of the gated material and has good process adaptability.

[0037] When introducing defects by element doping, the selection of doping elements has the following specific requirements: the selected doping elements need to have a certain size difference with the matrix elements to ensure that the doping elements can destroy the regular arrangement in the original crystal structure and realize the transformation from crystalline to amorphous state; at the same time, the doping elements (or doping atoms) can form a relatively stable chemical bond with the matrix elements (or matrix atoms). On the one hand, the doping elements can connect the matrix elements to form an irregular network to prevent the matrix elements from being locally enriched to produce a long-range ordered structure and crystallize. On the other hand, the doping elements can try not to interfere with the stability of the matrix structure itself and even help improve the stability. Therefore, when the matrix material is doped with doping elements that meet the above requirements, it can not only increase the proportion of amorphous structure in the gate material, but also ensure the stability of the amorphous state. Therefore, element doping is a reliable method to improve the thermal stability of the amorphous state of the gate material.

[0038] With respect to the sulfur-based amorphous material based on Ge (germanium) As (arsenic) Se (selenium) / AsSe material, the inventors have found through research that the fundamental reasons for the poor thermal stability of the amorphous state are as follows: on the one hand, there are more defective octahedral structures and fewer complete tetrahedral structures inside the sulfur-based amorphous material based on GeAsSe / AsSe material. Due to the poor stability of the defective octahedral structure, it is easy to undergo structural changes under thermal disturbance, thereby reducing the stability of the amorphous structure; on the other hand, the atomic radius and electronegativity differences between the Ge element, the As element and the Se element are small, which makes it easy for the sulfur-based amorphous material based on GeAsSe / AsSe material to undergo atomic rearrangement under thermal disturbance, resulting in local atoms being regularly arranged to form localized tiny crystal seeds, and these tiny crystal seeds can serve as the core of grain growth. Under certain temperature conditions, they will quickly grow into grains, thereby causing the material to transform from an amorphous state to a crystalline state, and then causing the amorphous stability of the material to be reduced.

[0039] In combination with the above-mentioned requirements for the selection of doping elements and the characteristics of the sulfide amorphous material based on GeAsSe / AsSe material, the embodiment of the present application selects at least one of Sc, hafnium (Hf), zirconium (Zr), indium (In) and niobium (Nb) as a doping element to dope the GeAsSe / AsSe sulfide amorphous material to improve the amorphous thermal stability of the gating material. Please refer to the description of the following embodiments for details.

[0040] See also Figure 1 , Figure 1 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor device provided in an embodiment of the present application. The semiconductor device 100 may be a wafer or a three-dimensional memory, or a part of a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or gaming products, etc.

[0041] The semiconductor device 100 includes a first electrode 101, a second electrode 102 disposed opposite to the first electrode 101, and a gate layer 103 sandwiched between the first electrode 101 and the second electrode 102 and having a bidirectional threshold switching characteristic. The material of the gate layer 103 includes a base material and a doping element doped in the base material; wherein the base material includes a sulfide amorphous compound, the doping element is at least bonded to the sulfide element in the sulfide amorphous compound, and the doping element and the sulfide element are bonded to form a complete tetrahedral structure and / or octahedral structure; the doping element includes at least one of Sc element, Hf element, Zr element, In element and Nb element.

[0042] For the convenience of description, in the embodiment of the present application, the material of the gating layer 103 may be referred to as a gating material.

[0043] Since the doping elements bond with the sulfur series elements to form a complete tetrahedral structure and / or octahedral structure, on the one hand, the content of the more stable tetrahedral structure and / or octahedral structure inside the gating material can be increased, which is beneficial to improving the stability of the internal structure of the gating material, thereby improving the ability of the gating material to resist thermal disturbances, and further improving the amorphous thermal stability of the gating material; on the other hand, the addition of doping elements to the matrix material causes a small change in the atomic connection mode, and the doping compatibility is high, which can reduce the deterioration of the stability of the matrix material caused by doping, thereby improving the amorphous thermal stability of the gating material.

[0044] In some embodiments, the base material of the gate layer 103 is Ge x As y Se 1-x-y / Asx Se 1-x The amorphous sulfur compounds of the system, because the doping elements can bond with the Se element to form a complete tetrahedral structure and / or octahedral structure, and the stability of the complete tetrahedral structure and octahedral structure is stronger than the stability of the defective octahedral structure, so by doping the doping elements in Ge x As y Se 1-x-y / As x Se 1-x The amorphous sulfur compounds of the system can reduce the content of defective octahedral structures inside the material, while increasing the content of stable tetrahedral and octahedral structures, thereby facilitating the improvement of the amorphous thermal stability of the gating layer 103 material.

[0045] In some embodiments, the doping element is bonded to any one element in the sulfide amorphous compound, and the bond energy of the chemical bond formed between the doping element and any one element in the sulfide amorphous compound is greater than the bond energy of the chemical bond formed between the same element or different elements in the sulfide amorphous compound.

[0046] Since the bond energy of the chemical bond formed between the doping element and any element in the sulfur-based amorphous compound is greater than the bond energy of the chemical bond formed between the same element or different elements in the sulfur-based amorphous compound, the connection between atoms in the gating layer 103 material is more stable, which reduces the probability of rearrangement of atoms to form tiny crystal seeds and avoids the formation of large-sized grains, thereby contributing to the stability of the amorphous state of the material.

[0047] It can be understood that the doping elements make the connection between atoms in the gate layer 103 material more stable, so that the temperature required for the gate layer 103 material to transform from an amorphous state to a crystalline state is higher, thereby improving the amorphous thermal stability of the gate layer 103 material.

[0048] In some embodiments, the atomic radius of the doping element is greater than the atomic radius of any element in the chalcogenide amorphous compound, and the atomic radius difference percentage between the doping element and any element in the chalcogenide amorphous compound is in a range of 15% to 30%. This design is conducive to improving the bond energy of the chemical bond formed between the doping element and the element in the chalcogenide amorphous compound, thereby facilitating improving the amorphous thermal stability of the gating layer 103 material.

[0049] Furthermore, if a doping element with an atomic radius difference percentage of less than 15% is used for doping, the difference between the atomic radius of the doping element and the atomic radius of the element in the matrix material is small. At this time, the concentration of the defect structure must be increased by increasing the doping concentration, and the electrical properties of the gating layer 103 are sensitive to changes in material composition. The introduction of a large number of doping elements can easily lead to deterioration of the electrical properties of the gating layer 103. If a doping element with an atomic radius difference percentage greater than 30% is used for doping, the atomic radius of the doping element is too large, which can easily cause problems such as difficulty in doping, insufficient concentration, and reduced material structure stability. Therefore, it is a reasonable choice for the embodiment of the present application to select a doping element with an atomic radius difference percentage of 15% to 30%.

[0050] In some embodiments, the electronegativity of the doping element is less than the electronegativity of any element in the chalcogenide amorphous compound, and the absolute value of the electronegativity difference between the doping element and the element in the chalcogenide amorphous compound is greater than the absolute value of the electronegativity difference between different elements in the chalcogenide amorphous compound. This design is conducive to increasing the bond energy of the chemical bond formed between the doping element and the element in the chalcogenide amorphous compound, thereby facilitating the improvement of the amorphous thermal stability of the gating layer 103 material.

[0051] In some embodiments, the chalcogenide amorphous compound in the matrix material of the gate layer 103 includes As and Se. In a specific embodiment, the chemical formula of the chalcogenide amorphous compound in the matrix material is As2Se3.

[0052] Specifically, at least one of the Sc, Hf, Zr, In and Nb elements can be used as a doping element to form bonds with the As and Se atoms in the matrix material, so that the structure after doping has strong compatibility; and the atomic connection mode caused by the doping of Sc, Hf, Zr, In and Nb elements changes little, and the doping compatibility is high, which can reduce the deterioration of material stability caused by doping, and is beneficial to improving the amorphous thermal stability of the gating layer 103 material.

[0053] See also Figure 2 and Figure 3 , Figure 2 is a schematic diagram of a tetrahedral structure formed by combining a doping element and a chalcogenide element provided in an embodiment of the present application, Figure 3 Schematic diagram of an octahedral structure formed by combining a doping element and a chalcogenide element provided in an embodiment of the present application. Figure 2 As shown in FIG. 1 , the tetrahedral structure formed by the combination of the doping element (such as Hf or Zr) and the chalcogenide element (Se element) is a complete tetrahedral structure. Taking the doping element as Hf element as an example, the chemical structure formed by the combination of Hf element and Se element is HfSe2. Figure 3As shown, the octahedral structure formed by the combination of the doping element (such as Sc element) and the chalcogenide element (Se element) is a complete octahedral structure. Taking the doping element as Sc element as an example, the chemical structure formed by the combination of Sc element and Se element is Sc2Se3. Figure 2 and Figure 3 Both structures shown have stronger stability than the defective octahedral structure. Therefore, by doping the doping element into the matrix material, the content of the unstable octahedral structure inside the AsSe material is reduced, so that the stability of the internal structure of the material is enhanced, thereby improving the ability of the gating layer 103 material to resist thermal disturbances, and further improving the amorphous thermal stability of the gating layer 103 material.

[0054] Furthermore, the atomic radius and electronegativity of As, Se, Sc, Zr, Zr, In and Nb elements are shown in Table 1. As can be seen from Table 1, the atomic radius of any doping element is greater than the atomic radius of As and Se, and the electronegativity of any doping element is less than the atomic radius of As and Se. Furthermore, when Se is used as a reference element, the percentage difference in atomic radius between In, Sc, Zr, Zr and Nb elements and Se element is between 15% and 30%. In addition, the absolute value of the electronegativity difference between any doping element and As or Se is greater than the absolute value of the electronegativity difference between As and Se.

[0055] Table 1 Atomic parameters of each element

[0056]

[0057] Since the atomic size of the doping element is relatively large, the rearrangement and crystallization problems caused by the close atomic size between As and Se can be avoided. In addition, since the electronegativity difference between the doping element and As and Se is greater than the electronegativity difference between As and Se, and there is a certain atomic radius difference between the doping element and As and Se, the bond energy of the chemical bond formed between the doping element and As and Se is higher, thereby making the connection between atoms in the gating layer 103 material more stable, reducing the probability of rearrangement between atoms to form tiny crystal seeds, avoiding the formation of large-sized grains, and contributing to the amorphous stability of the gating layer 103 material.

[0058] Therefore, selecting at least one of Sc, Hf, Zr, In and Nb as the doping element can improve the amorphous thermal stability of the material of the gating layer 103 while ensuring the electrical properties of the gating layer 103, while also avoiding problems such as doping difficulties, insufficient concentration, and reduced material structure stability.

[0059] In a specific embodiment, the chemical formula of the material of the gate layer 103 is T a As x Se(100-a-x) , where T represents a doping element, a and x both represent the molar percentages of elements, 0 < a ≤ 10, and 25 ≤ x ≤ 45.

[0060] It can be understood that the element T is selected from at least one of the elements Sc, Hf, Zr, In, and Nb.

[0061] For example, the material of the select gate layer 103 includes Zr5As 35 Se 60 and Hf5As 35 Se 60 or at least one of them, but not limited thereto.

[0062] It should be noted that the content of the doping element cannot be too much. Adding the element T to the AsSe material can improve the stability of the amorphous structure. However, if the doping content of the element T exceeds 10%, it will cause an increase in the threshold voltage and the corresponding leakage current of the select gate layer 103, making it difficult for the select gate layer 103 to switch, and at the same time increasing the power consumption of the semiconductor device 100. Therefore, in the embodiments of the present application, controlling the content of the doping element between 0 and 10% is beneficial to improving the amorphous thermal stability of the material of the select gate layer 103, reducing the leakage current and power consumption.

[0063] The embodiments of the present application also provide various electrical performance parameters of the select gate layer when using the AsSe material and the GeSe material as the matrix materials of the select gate layer respectively. As can be seen from Table 2, when using the AsSe material as the matrix material of the select gate layer, the select gate layer has better turn-off current and selectivity. Therefore, doping at least one of the elements Sc, Hf, Zr, In, and Nb in the AsSe material in the present application is beneficial to obtaining a select gate material with high thermal stability, small turn-off current, and large selectivity, and a semiconductor device or memory containing the select gate layer.

[0064] Table 2 Electrical performance parameters of the select gate layer of different materials

[0065]

[0066] In some other embodiments, the chalcogenide amorphous compound includes Ge element, As element, and Se element, and the doping element includes at least one of Sc element, Hf element, Zr element, In element, and Nb element.

[0067] It can be understood that compared with the foregoing embodiments, Ge element is further added to the matrix material of the select gate layer 103 in this embodiment.

[0068] As can be seen from Table 2, the atomic radii of Ge, As and Se are similar, and are all smaller than the atomic radius of the doping element; and the electronegativity of Ge, As and Se is similar, and is greater than the electronegativity of the doping element. The doping element provided in the embodiment of the present application can also form a bond with the Ge element, and the atomic radius difference percentage between the doping element and Ge, As, and Se in the matrix material is between 15% and 30%, and the electronegativity difference between the doping element and Ge, the electronegativity difference between the doping element and As, and the electronegativity difference between the doping element and Se are greater than the electronegativity difference between any two elements of Ge, As and Se.

[0069] Therefore, at least one of Sc, Hf, Zr, In and Nb is selected as the doping element, which can form a bond with the Ge, As and Se atoms in the matrix material of the gating layer 103, so that the structural compatibility is strong, and the atomic connection mode caused by element doping changes less, the doping compatibility is high, and the material stability deterioration caused by doping can be reduced, which is beneficial to improve the amorphous thermal stability of the gating layer 103 material. In addition, since the atomic size of the doping element is large, the rearrangement and crystallization problems caused by the close atomic size between Ge, As and Se can be avoided, which is beneficial to further improve the amorphous thermal stability of the gating layer 103 material.

[0070] Specifically, the chemical formula of the material of the gate layer 103 is T a Ge x As y Se (100-a-x-y) , wherein T represents the doping element, a, x and y all represent the molar percentage of the element, <a≤10,0<x≤25,25≤y≤45。

[0071] It can be understood that the T element is at least one selected from Sc, Hf, Zr, In and Nb elements.

[0072] In a specific embodiment, the material of the gate layer 103 includes Hf5Ge 18 As 30 Se 47 and Zr3In5Ge 15 As 27 Se 50 At least one of, but not limited to.

[0073] In the embodiment of the present application, an appropriate amount of Ge element is added to the base material of the gating layer 103. Since the crystallization temperature of Ge is higher than that of Se, the crystallization temperature of the base material is increased to a certain extent, which is beneficial to improving the amorphous thermal stability of the gating layer 103 material; and the on-state current density is increased, thereby improving the durability of the gating layer 103.

[0074] Specifically, changes in the content of As or Ge in the matrix material may lead to changes in the performance of the gating material. For example, since the crystallization temperature of Ge is higher than that of Se, and Ge is concentrated near the grain boundary to inhibit the growth of small grains and seeds, when the content of Ge in the matrix material increases, the amorphous stability of the material can be improved. However, when the content of Ge is too high, the leakage current of the gating layer 103 increases. Of course, too much As in the matrix material is not conducive to reducing the leakage current.

[0075] Therefore, in the embodiment of the present application, the Ge content in the gating layer 103 material is controlled to be no more than 12%, and the As content is between 25% and 45%, so as to reduce the leakage current of the gating layer 103 on the basis of improving the amorphous thermal stability of the gating layer 103 material.

[0076] In some embodiments, the material of the gating layer 103 can be prepared by any one of processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and plasma doping.

[0077] In a specific implementation manner, the present application embodiment provides a method for manufacturing a gating layer 103 using a PVD process as an example, and the manufacturing method includes the following steps:

[0078] A target (such as Sc, Hf, Zr, In and Nb targets or alloy targets formed by the above elements), B target (such as Ge target), As target and Se target are respectively placed on the sputtering target material in the sputtering chamber and fixed;

[0079] Evacuating the sputtering chamber and introducing argon gas to adjust the pressure in the sputtering chamber; and

[0080] Adjust the power knob of the target to co-sputter and form the gate material on the substrate.

[0081] It can be understood that the method for preparing the material of the gating layer 103 provided in the embodiment of the present application is not limited thereto.

[0082] In some embodiments, the materials of the first electrode 101 and the second electrode 102 include but are not limited to at least one of amorphous carbon (C), platinum (Pt), titanium (Ti), tungsten (W), gold (Au), ruthenium (Ru), aluminum (Al), titanium tungsten (TiW), titanium nitride (TiN), tantalum nitride (TaN), iridium dioxide (IrO2), indium tin oxide (ITO), and indium zinc oxide (IZO).

[0083] It can be understood that the electrode materials used for the first electrode 101 and the second electrode 102 can be the same or different, and can be adaptively selected according to the actual application scenario.

[0084] In some embodiments, when the semiconductor device 100 is a gate tube, the semiconductor device 100 also includes a substrate layer and an insulating dielectric layer, the first electrode 102, the gate layer 103 and the second electrode 102 are stacked in sequence on the substrate layer, and the insulating dielectric layer covers the side wall of the gate layer 103.

[0085] It can be understood that two oppositely disposed ends of the gating layer 103 are electrically connected to the first electrode 101 and the second electrode 102 respectively, and the gating function can be achieved by applying a voltage or a current to the first electrode 101 and the second electrode 102 .

[0086] In some embodiments, the substrate layer may be a semiconductor substrate. For example, the material of the substrate layer includes but is not limited to silicon dioxide, silicon carbide, silicon wafer, sapphire or diamond.

[0087] In some embodiments, the insulating dielectric layer has insulating properties, which can prevent the first electrode 101 and the second electrode 102 from short-circuiting; and when the insulating dielectric layer is a heat-insulating material, it can have a heat-insulating effect on the gating layer, which is beneficial to improving its thermal stability. In some embodiments, the material of the insulating dielectric layer includes but is not limited to silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0088] Specifically, the material of the gating layer 103 provided in the embodiment of the present application is suitable for phase change memory, but is not limited thereto.

[0089] It can be understood that the semiconductor device 100 provided in the embodiment of the present application can be a gate tube, or a storage unit or memory or other electronic device containing a gate tube, but is not limited thereto.

[0090] In the embodiment of the present application, the base material of the gating layer 103 is a chalcogenide amorphous compound, and a doping element (such as Sc, Hf, Zr, In and Nb) is used to perform single element doping or multi-element combination co-doping in the chalcogenide amorphous compound, so that the number of stable tetrahedral structures and / or octahedral structures in the gating layer 103 material increases, the crystallization temperature of the gating layer 103 material is increased, and thus the amorphous thermal stability of the gating layer 103 material is improved. Improving the amorphous thermal stability of the gating layer 103 material improves the tolerance of the gating layer 103 material to the ambient temperature, thereby improving the control capability of the gating layer 103 to the current, which is beneficial to improving the reliability of the semiconductor device 100 and reducing the power consumption of the semiconductor device 100.

[0091] Moreover, a more stable chemical bond can be formed between the doping elements provided in the embodiments of the present application and the elements in the matrix material. The addition of the above-mentioned doping elements into the matrix material causes a small change in the atomic connection mode, and the doping compatibility is high. The rearrangement and crystallization of atoms in the matrix material can be avoided, which is beneficial to reducing the deterioration of the stability of the matrix material caused by doping, thereby further improving the amorphous thermal stability of the gating layer 103 material.

[0092] Therefore, the embodiment of the present application can effectively improve the amorphous thermal stability of the gating layer 103 material, thereby improving the tolerance of the gating layer 103 material to ambient temperature, which is beneficial to improving the data storage reliability of the phase change memory using the gating layer 103 material and is beneficial to reducing the power consumption of the phase change memory.

[0093] The embodiment of the present application further provides a gating material, and the gating material includes the material of the gating layer 103 described in the above embodiment. The description of the gating material can refer to the above embodiment, and will not be repeated here.

[0094] The base material of the gating material provided in the embodiment of the present application is a sulfur-based amorphous compound. Since the doping element is at least bonded to the sulfur-based element in the sulfur-based amorphous compound to form a complete tetrahedral structure and / or octahedral structure, the doping element is used to perform single element doping or multi-element combination co-doping in the sulfur-based amorphous compound, so that the number of stable tetrahedral structures and / or octahedral structures in the gating material increases, the crystallization temperature of the gating material is increased, and thus the amorphous thermal stability of the gating material is improved. Improving the amorphous thermal stability of the gating material improves the tolerance of the gating material to the ambient temperature, thereby improving the control ability of the gating layer to the current, which is beneficial to improving the reliability of semiconductor devices using the gating layer and reducing the power consumption of the semiconductor devices.

[0095] See also Figure 4 , Figure 4 Schematic diagram of a memory structure provided by an embodiment of the present application. Figure 4 As shown, an embodiment of the present application further provides a memory 200, which includes a peripheral circuit 300 and the semiconductor device 100 described in the above embodiments, and the peripheral circuit 300 is electrically connected to the semiconductor device 100, for example, the peripheral circuit 300 is electrically connected to the first electrode and / or the second electrode of the semiconductor device 100, and is used to provide a driving signal to the semiconductor device.

[0096] In some embodiments, the memory 200 includes a phase change memory, such as a three-dimensional phase change memory, but is not limited thereto. When the memory 200 is a phase change memory, the semiconductor device 100 can be a phase change memory unit or a gate transistor in a phase change memory unit, which is not limited in the present application.

[0097] See also Figure 5 and Figure 6 , Figure 5 is a partial three-dimensional structural diagram of a phase change memory provided in an embodiment of the present application, Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure of area A in the middle.

[0098] like Figure 6 As shown, an embodiment of the present application further provides a semiconductor device 400, which is a phase change memory unit. The difference from the semiconductor device 100 provided in the aforementioned embodiment is that the semiconductor device 400 further includes a phase change memory layer 401 and a third electrode 402 connected in series with the selection layer 102, the phase change memory layer 401 is located on a side of the first electrode 101 away from the selection layer 103 or on a side of the second electrode 102 away from the selection layer 103, and the third electrode 402 is located on a side of the phase change memory layer 401 away from the selection layer 103.

[0099] In a specific embodiment, Figure 6 As shown, the semiconductor device 400 includes a first electrode 102 , a gating layer 103 , a second electrode 102 , a phase change memory layer 401 and a third electrode 402 which are sequentially stacked from bottom to top.

[0100] It can be understood that the first electrode 101 is a bottom electrode (BE), the second electrode 102 is an intermediate electrode, and the third electrode 402 is a top electrode (TE); correspondingly, the gating layer 103 is located between the first electrode 101 and the second electrode 102, and the phase change memory layer 401 is located between the second electrode 102 and the third electrode 402. It can be understood that the phase change memory layer 401 and the gating layer 103 are connected in series through the second electrode 102.

[0101] In some embodiments, the memory 200 also includes a bit line (BL) and a word line (WL) for address selection; the first electrode 101 is electrically connected to the bit line (BL), and the second electrode 102 is electrically connected to the word line (WL); or, the first electrode 101 is electrically connected to the word line (WL), and the second electrode 102 is electrically connected to the bit line (BL).

[0102] In some embodiments, the memory 200 includes a phase change memory having a cross-point lattice structure (eg Figure 5 The phase change memory 500 is shown, but is not limited thereto.

[0103] like Figure 5As shown, a phase change memory 500 with a cross-point lattice structure includes a first address line 501, a first phase change memory unit 502, and a second address line (which may include Figure 5 There are two layers as shown, or there may be only one layer) 503, a second phase change memory unit 504 and a third address line 505; wherein the first phase change memory unit 502 and the second phase change memory unit 504 have the same structure and are both the semiconductor device 400 described in the aforementioned embodiment. For example, the first phase change memory unit 502 and the second phase change memory unit 504 both include a first electrode 101, a selection layer 103, a second electrode 102, a phase change memory layer 401 and a third electrode 402 stacked in sequence from bottom to top.

[0104] The phase change memory 500 can be based on heating and quenching the phase change memory layer 401 in the first phase change memory unit 502 and the second phase change memory unit 504, so that the phase change memory layer 401 in the first phase change memory unit 502 and the second phase change memory unit 504 can be converted between the amorphous state and the crystalline state, and then the difference between the resistivity of the phase change memory layer 401 in the first phase change memory unit 502 and the second phase change memory unit 504 in the amorphous state and the crystalline state can be used to implement data writing, erasing, reading and other processes. In addition, in order to prevent the leakage current of the read, erase, and write operations of the target phase change memory unit from affecting the adjacent phase change memory unit, it is necessary to use the threshold switching of the selection layer 103 to achieve the change from high resistance to low resistance, so as to control the switching of the current in the selected phase change memory unit.

[0105] like Figure 5 As shown, the first address line 501 is parallel to the third address line 505, and the first address line 501 and the third address line 505 are both perpendicular to the second address line 503; at the same time, the first phase change memory unit 502 is located at the intersection of the first address line 501 and the second address line 503, and the second phase change memory unit 504 is located at the intersection of the second address line 503 and the third address line 505.

[0106] Specifically, the first address line 501 and the third address line 505 can be used as bit lines (BL), and the second address line 503 can be used as word lines (WL); or, the first address line 501 and the third address line 505 can be used as word lines (WL), and the second address line 503 can be used as bit lines (BL).

[0107] In practical applications, the phase-change memory cells connected to both the selected word line and the selected bit line are selected by activating the selected word line and the selected bit line.

[0108] Of course, in other embodiments, the memory may also be other types of memories different from phase change memories, and the memory includes a storage layer and a gating layer connected in series, and the material of the gating layer includes the gating material described above. The embodiments of the present application do not limit the structure of the storage layer connected in series with the gating layer.

[0109] In the embodiment of the present application, since the material of the selection layer 103 in the memory 200 has high amorphous thermal stability, the tolerance of the selection layer 103 to the ambient temperature is improved, which effectively improves the data storage reliability of the memory 200 (or the phase change memory 500) and effectively reduces the power consumption of the memory 200 (or the phase change memory 500).

[0110] See also Figure 7 , Figure 7 6 is a schematic diagram of the structure of the storage system provided in the embodiment of the present application. The storage system 600 includes a memory 601 and a controller 602. The memory 601 may be a memory in any of the above embodiments. The memory 601 may include any semiconductor device in the above embodiments. The controller 602 is connected to the memory 601 and is used to control the memory 601 to store data. The memory 601 may perform an operation of storing data based on the control of the controller 602.

[0111] Specifically, the controller 601 is electrically connected to the peripheral circuit in the memory 601 , and controls the change of the working state of the memory 601 by providing a control signal to the peripheral circuit.

[0112] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0113] In the embodiment of the present application, since the gating material in the memory 601 has high amorphous thermal stability, the reliability of the memory 601 is effectively improved, thereby improving the reliability of the storage system 600.

[0114] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments. The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0115] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A gating material, characterized in that: comprising a base material and a doping element doped in the base material; Wherein, the matrix material includes a sulfide amorphous compound, and the doping element is bonded to at least the sulfide element in the sulfide amorphous compound to form a complete tetrahedral structure and / or octahedral structure.

2. The gating material according to claim 1, characterized in that: The doping element is bonded to any one element in the sulfide amorphous compound, and the bond energy of the chemical bond formed between the doping element and any one element in the sulfide amorphous compound is greater than the bond energy of the chemical bond formed between the same element or different elements in the sulfide amorphous compound.

3. The gating material according to claim 2, characterized in that: The atomic radius of the doping element is greater than the atomic radius of any element in the sulfide amorphous compound, and the atomic radius difference percentage between the doping element and any element in the sulfide amorphous compound ranges from 15% to 30%.

4. The gating material according to claim 2, characterized in that: The electronegativity of the doping element is less than the electronegativity of any element in the sulfur-based amorphous compound, and the absolute value of the electronegativity difference between the doping element and the element in the sulfur-based amorphous compound is greater than the absolute value of the electronegativity difference between different elements in the sulfur-based amorphous compound.

5. The gating material according to any one of claims 1 to 4, characterized in that: The doping element includes at least one of Sc, Hf, Zr, In and Nb.

6. The gating material according to any one of claims 1 to 4, characterized in that: The chalcogenide amorphous compound includes As element and Se element, and the chemical general formula of the select material is T a As x Se (100-a-x) , where T represents the doping element, and both a and x represent the molar percentages of the elements, 0 < a ≤ 10, and 25 ≤ x ≤ 45.

7. The gating material according to claim 6, characterized in that The gating material includes Zr5As 35 Se 60 and Hf5As 35 Se 60 At least one of .

8. The gating material according to any one of claims 1 to 4, characterized in that: The chalcogenide amorphous compound includes Ge, As and Se elements. The chemical formula of the gating material is T a Ge x As y Se (100-a-x-y) , wherein T represents the doping element, a, x and y all represent the molar percentage of the element, <a≤10,0<x≤25,25≤y≤45。 9. The gating material according to claim 8, characterized in that The gating material includes Hf5Ge 18 As 30 Se 47 and Zr3In5Ge 15 As 27 Se 50 At least one of .

10. A semiconductor device, characterized in that: A gate layer is included, wherein a material of the gate layer includes the gate material according to any one of claims 1 to 9.

11. A memory, characterized in that: The invention comprises a storage layer and a gate layer connected in series, wherein a material of the gate layer comprises the gate material according to any one of claims 1 to 9.

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