Copper features and related forming methods

Abstract

The disclosure relates to copper features and related methods of formation. Embodiments of a method of forming a copper feature may include: providing a copper layer having a thickness greater than 1 mm; cutting a trench partially through the thickness using a laser, leaving a remaining thickness; and after cutting, removing the remaining thickness using a water jet.

Description

Technical Field

[0001] Aspects of this document generally relate to semiconductor packaging. More specific implementations relate to systems and methods for forming copper features. Background Art

[0002] Semiconductor packages have been designed to provide electrical and mechanical connections to a motherboard or other circuit board. Various semiconductor packages are also used to provide protection for a semiconductor die included in the semiconductor package from moisture or electrostatic discharge. Summary of the invention

[0003] A specific implementation of a method of forming a copper feature may include providing a copper layer having a thickness greater than 1 mm; cutting a trench partially through the thickness using a laser, leaving a remaining thickness; and removing the remaining thickness using a water jet after cutting.

[0004] A specific implementation of a method of forming a copper feature may include one, all, or any of the following:

[0005] The method may include coupling the copper layer to a dielectric substrate.

[0006] The dielectric substrate may include one of aluminum oxide or boron nitride.

[0007] The method may further include forming a layer on the copper layer before lasing and removing the layer after cutting.

[0008] The method may include reducing copper oxide in the copper layer by exposing the copper layer to a forming gas.

[0009] The copper layer can be a first copper layer, and the method may also include: coupling a second metal layer having a thickness greater than 1 mm to the dielectric substrate; using a laser to cut a groove partially through the thickness of the second metal layer, leaving a remaining thickness of the second metal layer; and after the laser action, using a water jet to cut through the remaining thickness of the second metal layer.

[0010] The copper layer can be a first copper layer, and the method may also include: coupling a heat sink including a second metal layer having a thickness greater than 1 mm to a dielectric substrate; using a laser to cut a groove partially through the thickness of the second metal layer, leaving a remaining thickness of the second metal layer; and after the laser action, using a water jet to cut into the remaining thickness of the second metal layer to form fins of the heat sink.

[0011] A specific implementation of a method of forming a copper feature may include providing a copper layer having a thickness greater than 1 mm; cutting a trench partially through the thickness using a water jet, leaving a remaining thickness; and after cutting, etching through the remaining thickness.

[0012] A specific implementation of a method of forming a copper feature may include one, all, or any of the following:

[0013] The method may include coupling the copper layer to a dielectric substrate.

[0014] The dielectric substrate may include one of aluminum oxide or boron nitride.

[0015] The method may further include forming a layer on the copper layer before lasing and removing the layer after etching.

[0016] The method may include reducing copper oxide in the copper layer by exposing the copper layer to a forming gas.

[0017] The copper layer can be a first copper layer, and the method may also include: coupling a second metal layer having a thickness greater than 1 mm to the dielectric substrate; using a water jet to cut a groove partially through the thickness of the second metal layer, leaving a remaining thickness of the second metal layer; and after cutting, etching through the remaining thickness of the second metal layer.

[0018] The copper layer may be a first copper layer, and the method may further include: coupling a heat sink including a second metal layer having a thickness greater than 1 mm to a dielectric substrate; and using a water jet to cut a groove partially through the thickness of the second metal layer, leaving a remaining thickness of the second metal layer to form fins of the heat sink.

[0019] A specific implementation of a method of forming an insulated copper feature may include providing a copper layer including a thickness; forming a plurality of trenches through the thickness; and permanently filling the plurality of trenches with at least one polymer material immediately after forming the plurality of trenches.

[0020] A specific implementation of a method of forming an insulated copper feature may include one, all, or any of the following:

[0021] The method may include coupling the copper layer to a dielectric substrate.

[0022] Permanently filling the trenches may also include printing at least one polymer material into the plurality of trenches.

[0023] The at least one polymer material may extend beyond the thickness of the copper layer.

[0024] The method may include coupling a thinned semiconductor die to a copper layer, wherein at least one polymer material extends around one or more edges of the thinned semiconductor die.

[0025] The method may include a submodule to the copper layer, wherein at least one polymer material extends around one or more edges of the submodule.

[0026] The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the detailed description and accompanying drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Specific implementations will be described below in conjunction with the accompanying drawings, in which like reference numerals represent like elements, and:

[0028] Figure 1 is a side cross-sectional view of a copper layer during cutting with a laser, removal of a protective layer, coupling with a dielectric substrate, and after etching the remaining thickness of the copper layer;

[0029] Figure 2 is a side cross-sectional view of a copper layer during cutting with a laser, coupling with a dielectric substrate, cutting remaining thickness of the copper layer with a water jet, and removing a protective layer coupled to the copper layer;

[0030] Figure 3 is a side cross-sectional view of a copper layer during water jet cutting, after coupling with a dielectric substrate, after removing a protective layer, and after etching a remaining thickness of the copper layer;

[0031] Figure 4 is a specific implementation of an integrated semiconductor substrate having a semiconductor die coupled to the integrated semiconductor substrate;

[0032] Figure 5 is a specific implementation of a semiconductor package having a spacer and a semiconductor die coupled to the semiconductor package;

[0033] Figure 6 is a specific implementation of a semiconductor package having a semiconductor die and wire bonds including a ball grid array;

[0034] Figure 7 is a specific implementation of a semiconductor package having an integrated substrate including a heat sink formed by laser action;

[0035] Figure 8 is a specific implementation of a copper layer coupled to a dielectric substrate;

[0036] Fig. 9 FIG. 1 shows a copper layer after forming a feature by forming a plurality of trenches in the copper layer. Figure 8 The copper layer;

[0037] Fig.10 shows the polymer material after it has been applied into the plurality of grooves. Fig. 9 The copper layer;

[0038] Fig.11 shows the thinned semiconductor die after coupling to the copper layer Fig.10 The copper layer;

[0039] Fig.12 Another implementation of the copper layer after applying the polymer material into the plurality of trenches is shown;

[0040] Fig.13 shows the semiconductor die after coupling to the copper layer Fig.12 The copper layer;

[0041] Fig.14 Another implementation of the copper layer after applying the polymer material into the plurality of trenches is shown;

[0042] Fig.15 shows the semiconductor die after coupling to the copper layer Fig.14 The copper layer;

[0043] Fig.16 Another implementation of the copper layer after applying the first polymer material and the second polymer material into the plurality of trenches is shown; and

[0044] Fig.17 Another implementation of a copper layer is shown after applying a polymer material into the plurality of trenches and coupling a submodule to the copper layer. DETAILED DESCRIPTION

[0045] The present disclosure, its aspects, and specific implementations are not limited to the specific components, assembly processes, or method elements disclosed herein. Many additional components, assembly processes, and / or method elements known in the art that are consistent with the intended copper features and related methods will be readily apparent for use with specific specific implementations of the present disclosure. Thus, for example, although the present invention discloses specific implementations, such specific implementations and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, etc., and implementation components and methods known in the art for such copper features and related methods that are consistent with the intended operation and methods.

[0046] refer to Figure 1 , an implementation of copper layer 2 is shown. In various implementations disclosed herein, the copper layer is greater than 1 mm thick, which presents significant challenges for forming traces and features therein and through using only etching due to the amount of material that needs to be removed to form the features. Various method implementations disclosed herein are designed to facilitate forming features in such thick copper layers. In various implementations, copper layer 2 may be a stand-alone film; in other implementations, copper layer 2 may have been coupled to a dielectric substrate. However, in Figure 1 In the specific implementation of the method shown, the copper layer 2 is an independent film. Then, Figure 1The copper layer is shown during cutting / lasing using a laser beam 174 after applying a protective layer 3 on the copper layer 2. As shown, after the cutting process, slag 4 in the form of molten copper and material from the protective layer 3 is present on both sides of the groove 5 and at the bottom of the groove. In various specific implementations, the protective layer can be formed of a resin material, such as, as a non-limiting example, a resin material sold by Disco Corporation of Tokyo, Japan under the trade name HOGOMAX. In other specific implementations, the material can be a flux, a polyimide material, a photoresist, a metal film separated from the copper layer (such as, as a non-limiting example, titanium, titanium tungsten, HOGOMAX, or any combination of the foregoing).

[0047] The copper layer 2 has a thickness 7, but the laser cutting process does not remove all of the copper from within each trench, leaving a residual thickness of the copper layer at the bottom of each trench. The value / amount of the residual thickness may depend on consideration of various factors, including, by way of non-limiting example, the degree of mechanical stability required of the copper layer 2 after cutting, the amount of slag generated during the cutting process, the economic operating rate of the cutting process, the material properties of the copper layer, or any other economic or mechanical considerations. In addition, as Figure 1 As shown, a certain minimum distance B is maintained between each trench (thus forming a minimum width or head B of each copper feature being formed). This minimum width / head B can be determined by the minimum bottom measurement (trench bottom width) that needs to be maintained to ensure successful etching / forming of copper features in various implementations. In various method implementations disclosed herein, pure copper can be used, and any other copper alloy can also be processed.

[0048] Figure 1The copper layer of the next step after the copper layer 2 has been coupled to the dielectric substrate 8 is shown. In various specific implementations, as non-limiting examples, the substrate can be formed of aluminum oxide, aluminum nitride, boron nitride, FR4, or any other ceramic or dielectric material capable of mechanically supporting the copper layer. For those specific implementations using boron nitride, the substrate can be an epoxy resin sheet including boron nitride particles as a filler. The thermal expansion coefficient of this specific implementation of the dielectric substrate can be about 17ppm-19ppm, and the thermal conductivity can be about 16.5W / K, which can achieve thermal resistance performance comparable to or better than the ceramic dielectric layer materials previously disclosed in this document. In various specific implementations, because the dielectric substrate can be made of epoxy resin sheets, the layer is flexible enough to allow it to be folded / folded back onto itself. Such dielectric materials are very different from the rigid ceramic dielectric layer materials previously discussed in this document, and therefore have significant mechanical flexibility advantages. For example, the use of a dielectric layer containing boron nitride can enable the use of a common molding compound with a CTE of about 14ppm-17ppm for the molding process, which can reduce the overall packaging cost. In addition, the dielectric layer containing boron nitride can exhibit higher thermal conductivity and breakdown voltage than ceramic dielectric materials containing aluminum oxide or aluminum nitride.

[0049] Here, if Figure 1 As shown, the copper layer 2 forms an integrated substrate having a heat sink 6 coupled thereto after being coupled to the dielectric substrate 8. Figure 1 As shown, the thickness 7 (A) of the copper layer 2 matches or substantially matches the thickness A of the largest planar portion of the heat sink 6. In this way, warping of the copper layer 2 and the dielectric substrate 8 can be minimized during operation and during manufacturing. Figure 1 The specific implementation in illustrates use of the method in the context of an integrated substrate, but the various method implementations disclosed herein may also be used in conjunction with any of a variety of substrate types including, as non-limiting examples, direct bonded copper (DBC) substrates, integrated metal substrates (IMS), or any other substrate type. Figure 1 It is also shown how the protective layer 3 is removed together with most of the slag 4, but some of the slag 4 remains in the groove 5. In the case where the material of the protective layer is a resin, water or deionized water can be used for the removal process. In the case where the material of the protective layer is a polyimide or a photoresist, the removal process may involve a solvent stripping / cleaning process or an ashing process. In the case where the material of the protective layer includes a separate metal layer, if the metal layer is titanium or titanium tungsten, wet etching using hydrogen peroxide or hydrogen fluoride can be used to remove the metal layer and the remaining copper slag. A variety of removal processes can be selected depending on the material present in the protective layer.

[0050] Figure 1The final figure shows integrated substrate 10 after etching the remaining thickness of the plurality of trenches 5 to form traces / features 12 formed of copper, which are now coupled to dielectric substrate 8. In various method implementations, etching is performed using wet etching using various chemistries capable of etching copper. Figure 1 Also shown is how the heat sink 6 includes various fins / pins 14 for increasing the surface area of ​​the heat sink 6 and improving heat transfer from the final assembled semiconductor package.

[0051] refer to Figure 2 , shows a set of figures detailing a copper layer 16 after processing using a particular implementation of the method of forming copper features. The copper layer 16 can be any copper layer disclosed in this document, and in this case is a copper film. Figure 2 The copper layer 16 is shown after being cut using a laser beam 18 after applying a protective film 20. The material of the protective layer 20 can be any material disclosed in this document. Figure 2 As shown, slag 21 from the laser action process is deposited around trenches 22 formed in the material of copper layer 16 . Figure 2 It is also shown how the laser beam cutting process does not completely cut through the thickness A of the copper layer 16, but leaves a residual thickness at the bottom of each trench 22. Moreover, depending on the specific method implementation, a minimum width / head distance B may be maintained between the trench edges to ensure proper subsequent processing. However, in the case where the removal of the residual thickness of the copper layer 16 is not performed using etching, the need to maintain the minimum width / head distance B may not be necessary or critical.

[0052] Figure 2 Also shown is the cut copper layer 16 after being coupled to a dielectric substrate 24 to which a heat sink 26 has also been coupled, thereby forming a structure similar to Figure 1 The heat sink 26 can be any heat sink type disclosed in this document, and the dielectric substrate 24 can be any substrate type disclosed in this document. Figure 2 It is shown how a water jet 28 can be used to cut the remaining thickness of the copper layer 16 after cutting using the laser beam 18 to complete the formation of the copper features coupled to the dielectric substrate 24. Figure 2 Note also that similar to Figure 1 In a specific implementation of the integrated substrate, the thickness A of the copper layer 16 is the same or substantially the same as the thickness A of the largest planar portion of the heat sink 26 to help prevent / reduce warping of the dielectric substrate 24.

[0053] exist Figure 2The final figure of FIG. 1 shows the integrated substrate 30 after the protective layer 20 and the remaining slag 21 therewith are removed, leaving the copper features 32 of the copper layer 16 on one side of the dielectric substrate 24, with the heat sink 26 coupled to the other side of the dielectric substrate. Figure 2 As shown, the heat sink 26 includes various pins / fins 34 for increasing the surface area of ​​the heat sink 26 and the corresponding heat transfer rate. The material used for the heat sink disclosed herein can be any of a variety of thermally conductive materials, including, as non-limiting examples, pure copper, copper alloys, metals, or any other thermally conductive material. In various implementations, the material of the heat sink can be the same as the copper features to help match the thermal expansion coefficient between the copper features and the heat sink during operation and avoid warping / stress in the final package.

[0054] refer to Figure 3 , shows a specific implementation of a copper-containing layer 36 that includes a copper layer 38 and one or more metal layers 40 coupled to the copper layer. The one or more layers 40 may include any of a variety of metals, including, by way of non-limiting example, copper, nickel, titanium, tungsten, palladium, gold, silver, tin, any combination thereof, or any other conductive material. Figure 3 Also shown is how water jets 42 are used to directly form trenches 44 and how slag 46 is deposited at the bottom of trenches 44 and on top of protective layer 48. Protective layer 48 may be made of any material and formed using any of the methods for forming protective layers disclosed in this document.

[0055] As previously described, water jet 42 does not remove the entire thickness A of copper-containing layer 36, but rather leaves a residual amount of thickness to allow copper-containing layer 36 to be coupled to dielectric layer 50 (if cut prior to being coupled to the dielectric layer). However, in other implementations, where copper-containing layer 36 is coupled to dielectric layer 50 prior to the cutting process using the water jet, the method implementation still includes partially cutting through copper-containing layer 36 to leave a residual thickness. Figure 3 As shown, the second copper layer 52 is coupled to the side of the dielectric layer 50 opposite to the side to which the copper-containing layer 36 is coupled. In this manner, the resulting substrate is a direct-bonded copper substrate, and in various method implementations, any of the methods for coupling the second copper layer 52 and the copper-containing layer 36 to the specific material of the dielectric layer 50 may be used, including, by way of non-limiting example, sintering, bonding, gluing, thermal compression bonding, brazing, active metal brazing, or any other method for coupling the specific material of the dielectric layer 50 to the two metal layers 36, 52. The material of the dielectric layer 40 may be any dielectric material disclosed in this document. Figure 3 As shown, the thickness A of the copper-containing layer 36 and the thickness A of the second copper layer 52 may be the same or substantially the same.

[0056] Figure 3Also shown is a direct bonded copper substrate 54 after removing the protective layer 48 and etching the remaining thickness of the copper-containing layer 36 to form traces 56. The removal of the protective layer 48 can be performed using any method disclosed herein that is consistent with the material of the protective layer. The etching of the remaining thickness can be performed using any method disclosed herein to remove copper or the material of one or more metal layers 40, or consistent with the removal of a specific metal in one or more metal layers. In various method implementations, etching can occur before removing the protective layer 40; in other implementations, the protective layer 40 can be removed first and the remaining thickness in the trench can be etched subsequently. The resulting direct bonded copper substrate 54 has various copper-containing features / traces 56 formed thereon and is ready for additional processing to form a finished semiconductor package.

[0057] In various method implementations disclosed thus far, the copper material may be pure copper, and thus after etching, it may be necessary to reduce copper oxide that has formed on the traces during the processing step. In various method implementations, reducing the copper oxide may be performed by exposing the copper features to a reducing atmosphere (e.g., forming gas) to reduce any copper oxide to copper prior to additional processing. In other implementations, the one or more metal layers applied to the copper layer may be layers that can be used to protect the copper layer from oxidation during processing and are removed prior to processing with an etching step to prevent the formation of copper oxide, for example, prior to wire bonding. As non-limiting examples, the material of the one or more layers may be titanium or titanium tungsten.

[0058] refer to Figure 4 , shows a specific implementation of an integrated substrate 58 that includes a copper feature 60, a heat sink 62, and a dielectric layer 64. The substrate 58 is shown in a subsequent step with respect to package formation, wherein a semiconductor die 66 has been bonded / attached to the copper feature 60. The substrate 58 may then proceed through additional processing steps as needed to allow for the formation of additional interconnects to the semiconductor die 66, the addition of a mold compound in the case of an air-cooled package, or the formation of other protective layers as part of the remainder of the packaging process (in the case of an immersion-cooled package). Figure 5 An implementation of package 68 is shown containing a direct bonded copper substrate 70 having a copper feature 72 formed using an implementation of the method disclosed herein, to which a spacer 74 and a thinned semiconductor die 76 have been attached. An encapsulant 78 has been applied to form the outer surface of the package, and electrical connectors / pins 80 extend out of the encapsulant 78.

[0059] The various method implementations disclosed herein may also be used with a variety of other semiconductor package types. Figure 682 is shown prior to application of a mold compound / encapsulant, showing a copper feature 84 formed using an implementation of the method disclosed herein, with a die 86 coupled to the copper feature, showing a bond wire 88 electrically coupling the die 86 to a second layer 90 of the substrate 82, and a bond wire 92 electrically coupling the copper feature 94 to the second layer 90 of the substrate 82. In various implementations, the second layer 90 of the substrate may be a single metal layer or may be a plurality of layers that allow electrical signals to be routed to the substrate. Figure 6 The interposer or redistribution layer of the ball grid array 96 is shown. Figure 7 , shows a semiconductor package 98 including an integrated substrate 100 during the formation of a heat sink 102 using a laser beam 104, indicating that the fins / pins 106 of the heat sink 102 can be formed as a final step in the package formation, rather than during the processing of the substrate itself in various method implementations. The semiconductor package 98 similarly includes a copper feature 108 formed using a method implementation disclosed herein, a semiconductor die 110 has been attached to the copper feature and encapsulated with an encapsulant / mold compound 112, with pins 114 extending out of the encapsulant / mold compound. These non-limiting examples show how the principles disclosed herein can be used with a variety of substrate types and a variety of packaging configurations.

[0060] Furthermore, the semiconductor die utilized in the implementations disclosed in this document may include / serve as any of a variety of semiconductor device types, including, as non-limiting examples, transistors, diodes, power devices, metal oxide field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), thyristors, rectifiers, or any other semiconductor device type. The various semiconductor die in this document may include a semiconductor substrate material, which may be, as non-limiting examples, silicon, silicon carbide, silicon on insulator, gallium arsenide, ruby, sapphire, or any other semiconductor material type.

[0061] refer to Figure 8 , shows an implementation of a substrate 116 having a thick copper layer 118 coupled to a dielectric layer 120. The thick copper layer 118 has a thickness of 1 mm or greater, similar to those previously disclosed in this document, and may include any composition disclosed herein. The dielectric layer may be any dielectric material disclosed in this document, including resin materials such as FR4 or other laminate materials. Although the substrate 116 is shown as having only a single metal layer thereon, any of the substrate implementations disclosed subsequently herein may include a second metal layer (such as in the case of a direct bonded copper substrate or an integrated metal substrate) or a heat sink (in the case of an integrated substrate). In various implementations, the substrate may also include an interposer or a redistribution layer.

[0062] Fig. 9 The substrate 116 is shown after various copper features / traces 122 are formed from the copper layer 118. The copper features 122 can be formed using any of the methods previously disclosed in this document that are capable of forming such features from thick copper layers (including various combinations thereof), including, as non-limiting examples, laser only, laser + water jet, laser + etching, water jet only, or water jet + etching. The ability to use laser and water jet removal techniques with thick copper layers as disclosed herein allows for tighter / smaller spacing between copper features 122. As the spacing between copper features decreases, the aspect ratio of the trench 124 increases accordingly. As a result, smaller particles can cause bridging or shorting defects between copper features during operation / testing. This problem may be particularly relevant when methods such as sintering are employed in subsequent packaging steps, in the presence of increased levels of particles. Furthermore, in the presence of particles, ions in the materials in the semiconductor package will migrate to the particles, resulting in an increase in conductive material at the particle, which can lead to shorts and bridging (which can be observed by failure under high temperature reverse bias [HTRB] testing). Furthermore, when conductive die attach materials or solder are used to couple the die and other devices, the excess material can lead to an increased probability of bridging between two copper features, resulting in the rejection of the entire substrate.

[0063] Fig.10 The substrate 116 is shown after electrically insulating material 126 has been formed into each trench 124. The formation process may be performed by printing electrically insulating material 126, overmolding followed by grinding, painting, stenciling, or any other technique capable of accurately placing the electrically insulating material into the trenches while leaving the copper features 122 exposed for further packaging processing steps. As non-limiting examples, electrically insulating material 126 may be an encapsulant, a molding compound, a resin, an epoxy, spin-on glass, a glass, a polymer material, or another flowable dielectric material capable of curing / drying in place within trench 124. As shown in FIG. Fig.10 As shown, the upper layer of electrically insulating material 126 is higher than the upper planar surface / bonding surface of each copper feature 122 .

[0064] refer to Fig.11 , shows substrate 116 after semiconductor die 130 is bonded to copper feature 122 using solder material 128. Note that in this implementation, raised electrically insulating material 126 prevents solder 128 from flowing into trench 124, which could potentially cause shorts between adjacent copper features 122. Thus, the ability to raise electrically insulating material 126 above the level of the surface of copper feature 122 can provide a greater processing latitude during subsequent processing steps. Additionally, in the case where semiconductor die 130 is a thinned semiconductor die, Fig.11 It is shown how the material of the electrically insulating material extends around the edge of the semiconductor die 130. Depending on tolerances, this can help to help strengthen / protect the edge of the thinned semiconductor die during subsequent processing operations, and / or act as a dam to prevent other materials subsequently applied during packaging operations from contacting the edge of the thinned semiconductor die. In some implementations, the raised electrically insulating material 126 can be used to "self-align" the semiconductor die into a desired position when the semiconductor die is placed over the die attach material during chip ejection and subsequent curing operations to help mitigate die float and / or die tilt. In such implementations, the raised electrically insulating material can be present around all sides of the semiconductor die or can be present only at the corners or a subset of the corners of the semiconductor die.

[0065] refer to Fig.12 , shows another implementation of substrate 132 after forming copper features 134 and forming electrically insulating material 136 into trenches 138. In this method implementation, the electrically insulating material is flush or substantially flush with the largest planar surface / upper surface / bonding surface of copper features 134. In various implementations, this can be achieved by precisely metering the amount of electrically insulating material dispensed / printed into trenches 138 or by overmolding followed by grinding. Fig.13 Substrate 132 is shown after semiconductor die 140 is bonded to copper features 134 using die attach material 142. Note that the die attach material is close to but does not cross the material of electrically insulating material 136 due to surface tension or other material incompatibility forces preventing die attach material 142 from bridging to adjacent copper features 134. This capability may involve selecting electrically insulating material and die attach material that have this type of material / surface tension / surface energy relationship with each other. However, in other implementations, die attach material 142 may flow over electrically insulating material 136, but the flow may be significantly slowed due to the material change from copper features 134 to electrically insulating material 136, thus preventing the formation of bridges between adjacent copper features 134.

[0066] Fig.14 Substrate 144 is shown after forming copper features 146 and electrically insulating material 148 into trenches 150. Note that in this implementation, the level of electrically insulating material 148 in trenches 150 is below the top surface / bonding surface of copper features 146. In this method implementation, this can be achieved by ensuring that less material is dispensed / printed into trenches 150 (which is needed to fill the trenches) or by selectively etching back electrically insulating material 146 after dispensing. The specific etching chemistry and technique (dry / wet) will depend on what is needed to remove the specific electrically insulating material employed. Fig.15Substrate 144 is shown after semiconductor die 152 is bonded to copper features 146 using die attach material 154, which may be any disclosed in this document. Fig.15 It is shown how the surface tension of the edges of the copper features 146 can be sufficient to prevent the die attach material 154 from flowing downward into the trenches 150, however, in the event that such flow were to occur, the surface energy of the material of the electrically insulating material 148 can be selected so that the die attach material 154 flows along and against the edges of the copper features (into and out of the page) rather than across the electrically insulating material 148, thereby preventing bridging from occurring.

[0067] refer to Fig.16 , a substrate 156 is shown including a copper feature 158. Although the foregoing examples of electrically insulating materials have included a single material, multiple layers of the same or different electrically insulating materials may be employed. Fig.16 The illustrated implementation of substrate 156 utilizes two different materials that form a first layer 160 that is conformally formed into trench 164, followed by a second layer 162 that is formed into first layer 160. In these implementations, as shown, only one of these layers may extend above the top surface / bonding surface of copper feature 158. However, in other implementations, both layers may be flush with or below the top surface / bonding surface. In implementations that employ multiple layers, the first layer may be formed using a deposition / spraying process that coats the sides of the trench and is then stabilized, while the second layer may be formed using a printing / dispensing / brushing process similar to that previously disclosed. In some implementations, the deposition process of first layer 160 may involve chemical vapor deposition or sputtering.

[0068] refer to Fig.17 , shows a specific implementation of a substrate 166 that includes a set of copper features 168 in which an electrically insulating material 170 is formed using any of the methods disclosed in this document. The electrically insulating material 170 is higher than the largest flat surface of the copper features 168. As shown, a die submodule 172 has been bonded to the copper features 168, and the electrically insulating material 170 now extends around the edge of the die submodule 172 and adjacent to (or in some implementations against) the edge of the die submodule. The die submodule 172 may include one or more dies bonded together using a lead frame or clip, which itself is covered by a molding compound or encapsulant, allowing them to be electrically connected to the material of the copper features 168 through various exposed pads / connectors. In this way, the copper features 168 can act like a lead frame or redistribution layer for the die submodule 172. In various specific implementations, the principles disclosed in this document can be used to construct a combination of semiconductor dies bonded to copper features and die submodules.

[0069] Where the above description relates to specific implementations and implementation components, sub-components, methods and sub-methods of copper features, it should be apparent that various modifications may be made without departing from the essence thereof, and that these implementations, implementation components, sub-components, methods and sub-methods may be applied to other copper features.

Claims

1. A method of forming a copper feature, the method comprising: Provide a copper layer with a thickness greater than 1mm; cutting a groove partially through the thickness using a laser, leaving a residual thickness; as well as After cutting, the remaining thickness is removed using a water jet. 2 . The method of claim 1 , further comprising coupling the copper layer to a dielectric substrate.

3. The method of claim 2, wherein the dielectric substrate comprises one of aluminum oxide or boron nitride.

4. The method according to claim 1, further comprising: forming a layer on the copper layer before laser action; as well as The layers are removed after cutting.

5. The method of claim 1, further comprising reducing copper oxide in the copper layer by exposing the copper layer to a forming gas.

6. The method of claim 2, wherein the copper layer is a first copper layer, and the method further comprises: coupling a second metal layer having a thickness greater than 1 mm to the dielectric substrate; cutting a groove partially through the thickness of the second metal layer using the laser, leaving a remaining thickness of the second metal layer; as well as After lasing, the water jet is used to cut through the remaining thickness of the second metal layer.

7. The method of claim 2, wherein the copper layer is a first copper layer, and the method further comprises: coupling a heat sink including a second metal layer having a thickness greater than 1 mm to the dielectric substrate; cutting a groove partially through the thickness of the second metal layer using the laser, leaving a remaining thickness of the second metal layer; as well as After the laser action, the water jet is used to cut into the remaining thickness of the second metal layer to form the fins of the heat sink.

8. A method of forming a copper feature, the method comprising: Provide a copper layer with a thickness greater than 1mm; using a water jet to cut a groove partially through the thickness, leaving a residual thickness; as well as After cutting, etching is performed through the remaining thickness.

9. The method of claim 8, further comprising coupling the copper layer to a dielectric substrate.

10. The method of claim 9, wherein the dielectric substrate comprises one of aluminum oxide or boron nitride.

11. The method according to claim 8, further comprising: forming a layer on the copper layer before laser action; as well as The layer is removed after etching.

12. The method of claim 8, further comprising reducing copper oxide in the copper layer by exposing the copper layer to a forming gas.

13. The method of claim 9, wherein the copper layer is a first copper layer, and the method further comprises: coupling a second metal layer having a thickness greater than 1 mm to the dielectric substrate; cutting a groove partially through the thickness of the second metal layer using the water jet, leaving a remaining thickness of the second metal layer; as well as After cutting, etching is performed through the remaining thickness of the second metal layer.

14. The method of claim 9, wherein the copper layer is a first copper layer, and the method further comprises: coupling a heat sink including a second metal layer having a thickness greater than 1 mm to the dielectric substrate; as well as The water jet is used to cut grooves partially through the thickness of the second metal layer, leaving a remaining thickness of the second metal layer to form fins of the heat sink.

15. A method of forming an insulated copper feature, the method comprising: providing a copper layer including a thickness; forming a plurality of grooves through the thickness; as well as The plurality of trenches are permanently filled with at least one polymer material immediately after forming the plurality of trenches.

16. The method of claim 15, further comprising coupling the copper layer to a dielectric substrate.

17. The method of claim 15, wherein permanently filling the trench further comprises: The at least one polymer material is printed into the plurality of grooves.

18. The method of claim 15, wherein the at least one polymer material extends above the thickness of the copper layer.

19. The method of claim 18, further comprising coupling a thinned semiconductor die to the copper layer, wherein the at least one polymer material extends around one or more edges of the thinned semiconductor die.

20. The method of claim 18, further comprising sub-module to the copper layer, wherein the at least one polymer material extends around one or more edges of the sub-module.

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